1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefixes=CHECK,FAST-INCDEC 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SLOW-INCDEC 4 5define i64 @imm1_Oz(i32 %x, i32 %y) minsize nounwind { 6; CHECK-LABEL: imm1_Oz: 7; CHECK: # %bb.0: 8; CHECK-NEXT: # kill: def $esi killed $esi def $rsi 9; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 10; CHECK-NEXT: leal 1(%rdi), %eax 11; CHECK-NEXT: incl %esi 12; CHECK-NEXT: addq %rsi, %rax 13; CHECK-NEXT: retq 14 %x1 = add i32 %x, 1 15 %y1 = add i32 %y, 1 16 %x1z = zext i32 %x1 to i64 17 %y1z = zext i32 %y1 to i64 18 %r = add i64 %x1z, %y1z 19 ret i64 %r 20} 21 22define i64 @imm1_Os(i32 %x, i32 %y) optsize nounwind { 23; CHECK-LABEL: imm1_Os: 24; CHECK: # %bb.0: 25; CHECK-NEXT: # kill: def $esi killed $esi def $rsi 26; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 27; CHECK-NEXT: leal 1(%rdi), %eax 28; CHECK-NEXT: incl %esi 29; CHECK-NEXT: addq %rsi, %rax 30; CHECK-NEXT: retq 31 %x1 = add i32 %x, 1 32 %y1 = add i32 %y, 1 33 %x1z = zext i32 %x1 to i64 34 %y1z = zext i32 %y1 to i64 35 %r = add i64 %x1z, %y1z 36 ret i64 %r 37} 38 39define i64 @imm1_O2(i32 %x, i32 %y) nounwind { 40; FAST-INCDEC-LABEL: imm1_O2: 41; FAST-INCDEC: # %bb.0: 42; FAST-INCDEC-NEXT: # kill: def $esi killed $esi def $rsi 43; FAST-INCDEC-NEXT: # kill: def $edi killed $edi def $rdi 44; FAST-INCDEC-NEXT: leal 1(%rdi), %eax 45; FAST-INCDEC-NEXT: incl %esi 46; FAST-INCDEC-NEXT: addq %rsi, %rax 47; FAST-INCDEC-NEXT: retq 48; 49; SLOW-INCDEC-LABEL: imm1_O2: 50; SLOW-INCDEC: # %bb.0: 51; SLOW-INCDEC-NEXT: # kill: def $esi killed $esi def $rsi 52; SLOW-INCDEC-NEXT: # kill: def $edi killed $edi def $rdi 53; SLOW-INCDEC-NEXT: leal 1(%rdi), %eax 54; SLOW-INCDEC-NEXT: addl $1, %esi 55; SLOW-INCDEC-NEXT: addq %rsi, %rax 56; SLOW-INCDEC-NEXT: retq 57 %x1 = add i32 %x, 1 58 %y1 = add i32 %y, 1 59 %x1z = zext i32 %x1 to i64 60 %y1z = zext i32 %y1 to i64 61 %r = add i64 %x1z, %y1z 62 ret i64 %r 63} 64