1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4define i64 @test1(i32 %x) nounwind { 5; CHECK-LABEL: @test1( 6; CHECK-NEXT: ret i64 0 7; 8 %y = lshr i32 %x, 1 9 %r = udiv i32 %y, -1 10 %z = sext i32 %r to i64 11 ret i64 %z 12} 13define i64 @test2(i32 %x) nounwind { 14; CHECK-LABEL: @test2( 15; CHECK-NEXT: ret i64 0 16; 17 %y = lshr i32 %x, 31 18 %r = udiv i32 %y, 3 19 %z = sext i32 %r to i64 20 ret i64 %z 21} 22 23; The udiv instructions shouldn't be optimized away, and the 24; sext instructions should be optimized to zext. 25 26define i64 @test1_PR2274(i32 %x, i32 %g) nounwind { 27; CHECK-LABEL: @test1_PR2274( 28; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 30 29; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]] 30; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[R]] to i64 31; CHECK-NEXT: ret i64 [[TMP1]] 32; 33 %y = lshr i32 %x, 30 34 %r = udiv i32 %y, %g 35 %z = sext i32 %r to i64 36 ret i64 %z 37} 38define i64 @test2_PR2274(i32 %x, i32 %v) nounwind { 39; CHECK-LABEL: @test2_PR2274( 40; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 31 41; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]] 42; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[R]] to i64 43; CHECK-NEXT: ret i64 [[TMP1]] 44; 45 %y = lshr i32 %x, 31 46 %r = udiv i32 %y, %v 47 %z = sext i32 %r to i64 48 ret i64 %z 49} 50 51; The udiv should be simplified according to the rule: 52; X udiv (C1 << N), where C1 is `1<<C2` --> X >> (N+C2) 53@b = external global [1 x i16] 54 55define i32 @PR30366(i1 %a) { 56; CHECK-LABEL: @PR30366( 57; CHECK-NEXT: [[Z:%.*]] = zext i1 [[A:%.*]] to i32 58; CHECK-NEXT: [[D:%.*]] = lshr i32 [[Z]], zext (i16 ptrtoint ([1 x i16]* @b to i16) to i32) 59; CHECK-NEXT: ret i32 [[D]] 60; 61 %z = zext i1 %a to i32 62 %d = udiv i32 %z, zext (i16 shl (i16 1, i16 ptrtoint ([1 x i16]* @b to i16)) to i32) 63 ret i32 %d 64} 65 66; OSS-Fuzz #4857 67; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4857 68define i177 @ossfuzz_4857(i177 %X, i177 %Y) { 69; CHECK-LABEL: @ossfuzz_4857( 70; CHECK-NEXT: store i1 false, i1* undef, align 1 71; CHECK-NEXT: ret i177 0 72; 73 %B5 = udiv i177 %Y, -1 74 %B4 = add i177 %B5, -1 75 %B2 = add i177 %B4, -1 76 %B6 = mul i177 %B5, %B2 77 %B3 = add i177 %B2, %B2 78 %B9 = xor i177 %B4, %B3 79 %B13 = ashr i177 %Y, %B2 80 %B22 = add i177 %B9, %B13 81 %B1 = udiv i177 %B5, %B6 82 %C9 = icmp ult i177 %Y, %B22 83 store i1 %C9, i1* undef 84 ret i177 %B1 85} 86 87define i32 @udiv_demanded(i32 %a) { 88; CHECK-LABEL: @udiv_demanded( 89; CHECK-NEXT: [[U:%.*]] = udiv i32 [[A:%.*]], 12 90; CHECK-NEXT: ret i32 [[U]] 91; 92 %o = or i32 %a, 3 93 %u = udiv i32 %o, 12 94 ret i32 %u 95} 96 97define i32 @udiv_exact_demanded(i32 %a) { 98; CHECK-LABEL: @udiv_exact_demanded( 99; CHECK-NEXT: [[O:%.*]] = and i32 [[A:%.*]], -3 100; CHECK-NEXT: [[U:%.*]] = udiv exact i32 [[O]], 12 101; CHECK-NEXT: ret i32 [[U]] 102; 103 %o = and i32 %a, -3 104 %u = udiv exact i32 %o, 12 105 ret i32 %u 106} 107