1; RUN: opt -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s 2; RUN: opt -verify-memoryssa -passes='loop-mssa(unswitch),verify<loops>' -S < %s | FileCheck %s 3 4define i32 @test(i32* %A, i1 %C) { 5entry: 6 br label %no_exit 7no_exit: ; preds = %no_exit.backedge, %entry 8 %i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ] ; <i32> [#uses=3] 9 %gep.upgrd.1 = zext i32 %i.0.0 to i64 ; <i64> [#uses=1] 10 %tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1 ; <i32*> [#uses=4] 11 %tmp.13 = load i32, i32* %tmp.7 ; <i32> [#uses=2] 12 %tmp.14 = add i32 %tmp.13, 1 ; <i32> [#uses=1] 13 store i32 %tmp.14, i32* %tmp.7 14 br i1 %C, label %then, label %endif 15then: ; preds = %no_exit 16 %tmp.29 = load i32, i32* %tmp.7 ; <i32> [#uses=1] 17 %tmp.30 = add i32 %tmp.29, 2 ; <i32> [#uses=1] 18 store i32 %tmp.30, i32* %tmp.7 19 %inc9 = add i32 %i.0.0, 1 ; <i32> [#uses=2] 20 %tmp.112 = icmp ult i32 %inc9, 100000 ; <i1> [#uses=1] 21 br i1 %tmp.112, label %no_exit.backedge, label %return 22no_exit.backedge: ; preds = %endif, %then 23 %i.0.0.be = phi i32 [ %inc9, %then ], [ %inc, %endif ] ; <i32> [#uses=1] 24 br label %no_exit 25endif: ; preds = %no_exit 26 %inc = add i32 %i.0.0, 1 ; <i32> [#uses=2] 27 %tmp.1 = icmp ult i32 %inc, 100000 ; <i1> [#uses=1] 28 br i1 %tmp.1, label %no_exit.backedge, label %return 29return: ; preds = %endif, %then 30 ret i32 %tmp.13 31} 32 33; This simple test would normally unswitch, but should be inhibited by the presence of 34; the noduplicate call. 35 36; CHECK-LABEL: @test2( 37define i32 @test2(i32* %var) { 38 %mem = alloca i32 39 store i32 2, i32* %mem 40 %c = load i32, i32* %mem 41 42 br label %loop_begin 43 44loop_begin: 45 46 %var_val = load i32, i32* %var 47 48 switch i32 %c, label %default [ 49 i32 1, label %inc 50 i32 2, label %dec 51 ] 52 53inc: 54 call void @incf() noreturn nounwind 55 br label %loop_begin 56dec: 57; CHECK: call void @decf() 58; CHECK-NOT: call void @decf() 59 call void @decf() noreturn nounwind noduplicate 60 br label %loop_begin 61default: 62 br label %loop_exit 63loop_exit: 64 ret i32 0 65; CHECK: } 66} 67 68; This simple test would normally unswitch, but should be inhibited by the presence of 69; the convergent call that is not control-dependent on the unswitch condition. 70 71; CHECK-LABEL: @test3( 72define i32 @test3(i32* %var) { 73 %mem = alloca i32 74 store i32 2, i32* %mem 75 %c = load i32, i32* %mem 76 77 br label %loop_begin 78 79loop_begin: 80 81 %var_val = load i32, i32* %var 82 83; CHECK: call void @conv() 84; CHECK-NOT: call void @conv() 85 call void @conv() convergent 86 87 switch i32 %c, label %default [ 88 i32 1, label %inc 89 i32 2, label %dec 90 ] 91 92inc: 93 call void @incf() noreturn nounwind 94 br label %loop_begin 95dec: 96 call void @decf() noreturn nounwind 97 br label %loop_begin 98default: 99 br label %loop_exit 100loop_exit: 101 ret i32 0 102; CHECK: } 103} 104 105; Make sure we don't unswitch, as we can not find an input value %a 106; that will effectively unswitch 0 or 3 out of the loop. 107; 108; CHECK: define void @and_or_i2_as_switch_input(i2 109; CHECK: entry: 110; This is an indication that the loop has NOT been unswitched. 111; CHECK-NOT: icmp 112; CHECK: br 113define void @and_or_i2_as_switch_input(i2 %a) { 114entry: 115 br label %for.body 116 117for.body: 118 %i = phi i2 [ 0, %entry ], [ %inc, %for.inc ] 119 %and = and i2 %a, %i 120 %or = or i2 %and, %i 121 switch i2 %or, label %sw.default [ 122 i2 0, label %sw.bb 123 i2 3, label %sw.bb1 124 ] 125 126sw.bb: 127 br label %sw.epilog 128 129sw.bb1: 130 br label %sw.epilog 131 132sw.default: 133 br label %sw.epilog 134 135sw.epilog: 136 br label %for.inc 137 138for.inc: 139 %inc = add nsw i2 %i, 1 140 %cmp = icmp slt i2 %inc, 3 141 br i1 %cmp, label %for.body, label %for.end 142 143for.end: 144 ret void 145} 146 147; Make sure we don't unswitch, as we can not find an input value %a 148; that will effectively unswitch true/false out of the loop. 149; 150; CHECK: define void @and_or_i1_as_branch_input(i1 151; CHECK: entry: 152; This is an indication that the loop has NOT been unswitched. 153; CHECK-NOT: icmp 154; CHECK: br 155define void @and_or_i1_as_branch_input(i1 %a) { 156entry: 157 br label %for.body 158 159for.body: 160 %i = phi i1 [ 0, %entry ], [ %inc, %for.inc ] 161 %and = and i1 %a, %i 162 %or = or i1 %and, %i 163 br i1 %or, label %sw.bb, label %sw.bb1 164 165sw.bb: 166 br label %sw.epilog 167 168sw.bb1: 169 br label %sw.epilog 170 171sw.epilog: 172 br label %for.inc 173 174for.inc: 175 %inc = add nsw i1 %i, 1 176 %cmp = icmp slt i1 %inc, 1 177 br i1 %cmp, label %for.body, label %for.end 178 179for.end: 180 ret void 181} 182 183declare void @incf() noreturn 184declare void @decf() noreturn 185declare void @conv() convergent 186