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Name Date Size #Lines LOC

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AsmParser/03-May-2024-1,3311,072

Disassembler/03-May-2024-697564

InstPrinter/03-May-2024-282217

MCTargetDesc/03-May-2024-1,5231,083

TargetInfo/03-May-2024-5540

CMakeLists.txtD03-May-20241.1 KiB3531

DelaySlotFiller.cppD03-May-202414.9 KiB515348

LLVMBuild.txtD03-May-20241 KiB3733

LeonFeatures.tdD03-May-20244.2 KiB9275

LeonPasses.cppD03-May-202433.5 KiB934600

LeonPasses.hD03-May-20245.8 KiB200144

README.txtD03-May-20241.5 KiB5947

Sparc.hD03-May-20245.3 KiB168138

Sparc.tdD03-May-20245.7 KiB161134

SparcAsmPrinter.cppD03-May-202416.3 KiB452367

SparcCallingConv.tdD03-May-20245.6 KiB145130

SparcFrameLowering.cppD03-May-202413.2 KiB370239

SparcFrameLowering.hD03-May-20242.4 KiB6932

SparcISelDAGToDAG.cppD03-May-202414.6 KiB413288

SparcISelLowering.cppD03-May-2024138.6 KiB3,5772,646

SparcISelLowering.hD03-May-20249.9 KiB224159

SparcInstr64Bit.tdD03-May-202421.6 KiB542451

SparcInstrAliases.tdD03-May-202420.6 KiB507399

SparcInstrFormats.tdD03-May-202410.3 KiB370303

SparcInstrInfo.cppD03-May-202418.6 KiB507398

SparcInstrInfo.hD03-May-20244 KiB10755

SparcInstrInfo.tdD03-May-202467.9 KiB1,6931,465

SparcInstrVIS.tdD03-May-202411.1 KiB264220

SparcMCInstLower.cppD03-May-20243.3 KiB10975

SparcMachineFunctionInfo.cppD03-May-2024448 153

SparcMachineFunctionInfo.hD03-May-20241.9 KiB5729

SparcRegisterInfo.cppD03-May-20248.1 KiB238153

SparcRegisterInfo.hD03-May-20241.7 KiB5123

SparcRegisterInfo.tdD03-May-202413.7 KiB379342

SparcSchedule.tdD03-May-20246.4 KiB125118

SparcSubtarget.cppD03-May-20243.2 KiB10559

SparcSubtarget.hD03-May-20244.4 KiB13594

SparcTargetMachine.cppD03-May-20247.8 KiB213157

SparcTargetMachine.hD03-May-20242.7 KiB8050

SparcTargetObjectFile.cppD03-May-20241.6 KiB4425

SparcTargetObjectFile.hD03-May-20241,014 3619

SparcTargetStreamer.hD03-May-20241.5 KiB5028

README.txt

1To-do
2-----
3
4* Keep the address of the constant pool in a register instead of forming its
5  address all of the time.
6* We can fold small constant offsets into the %hi/%lo references to constant
7  pool addresses as well.
8* When in V9 mode, register allocate %icc[0-3].
9* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
10* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
11  not clear how to write a pattern for this though:
12
13float %t1(int %a, int* %p) {
14        %C = seteq int %a, 0
15        br bool %C, label %T, label %F
16T:
17        store int 123, int* %p
18        br label %F
19F:
20        ret float undef
21}
22
23codegens to this:
24
25t1:
26        save -96, %o6, %o6
271)      subcc %i0, 0, %l0
281)      bne .LBBt1_2    ! F
29        nop
30.LBBt1_1:       ! T
31        or %g0, 123, %l0
32        st %l0, [%i1]
33.LBBt1_2:       ! F
34        restore %g0, %g0, %g0
35        retl
36        nop
37
381) should be replaced with a brz in V9 mode.
39
40* Same as above, but emit conditional move on register zero (p192) in V9
41  mode.  Testcase:
42
43int %t1(int %a, int %b) {
44        %C = seteq int %a, 0
45        %D = select bool %C, int %a, int %b
46        ret int %D
47}
48
49* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
50  with the Y register, if they are faster.
51
52* Codegen bswap(load)/store(bswap) -> load/store ASI
53
54* Implement frame pointer elimination, e.g. eliminate save/restore for
55  leaf fns.
56* Fill delay slots
57
58* Use %g0 directly to materialize 0. No instruction is required.
59