1; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s 2; rdar://7329206 3 4; Use sbb x, x to materialize carry bit in a GPR. The value is either 5; all 1's or all 0's. 6 7define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { 8entry: 9; CHECK-LABEL: t1: 10; CHECK: xorl %eax, %eax 11; CHECK: seta %al 12; CHECK: shll $5, %eax 13 %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1] 14 %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1] 15 ret i16 %iftmp.1.0 16} 17 18define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp { 19entry: 20; CHECK-LABEL: t2: 21; CHECK: sbbl %eax, %eax 22; CHECK: andl $32, %eax 23 %0 = icmp ult i16 %x, 26 ; <i1> [#uses=1] 24 %iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1] 25 ret i16 %iftmp.0.0 26} 27 28define i64 @t3(i64 %x) nounwind readnone ssp { 29entry: 30; CHECK-LABEL: t3: 31; CHECK: sbbq %rax, %rax 32; CHECK: andl $64, %eax 33 %0 = icmp ult i64 %x, 18 ; <i1> [#uses=1] 34 %iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1] 35 ret i64 %iftmp.2.0 36} 37 38@v4 = common global i32 0, align 4 39 40define i32 @t4(i32 %a) { 41entry: 42; CHECK-LABEL: t4: 43; CHECK: movq _v4@GOTPCREL(%rip), %rax 44; CHECK: cmpl $1, (%rax) 45; CHECK: sbbl %eax, %eax 46; CHECK: andl $32768, %eax 47; CHECK: leal 65536(%rax,%rax), %eax 48 %0 = load i32, i32* @v4, align 4 49 %not.tobool = icmp eq i32 %0, 0 50 %conv.i = sext i1 %not.tobool to i16 51 %call.lobit = lshr i16 %conv.i, 15 52 %add.i.1 = add nuw nsw i16 %call.lobit, 1 53 %conv4.2 = zext i16 %add.i.1 to i32 54 %add = shl nuw nsw i32 %conv4.2, 16 55 ret i32 %add 56} 57 58define i8 @t5(i32 %a) #0 { 59entry: 60; CHECK-LABEL: t5: 61; CHECK: testl %edi, %edi 62; CHECK: setns %al 63 %.lobit = lshr i32 %a, 31 64 %trunc = trunc i32 %.lobit to i8 65 %.not = xor i8 %trunc, 1 66 ret i8 %.not 67} 68 69define zeroext i1 @t6(i32 %a) #0 { 70entry: 71; CHECK-LABEL: t6: 72; CHECK: testl %edi, %edi 73; CHECK: setns %al 74 %.lobit = lshr i32 %a, 31 75 %trunc = trunc i32 %.lobit to i1 76 %.not = xor i1 %trunc, 1 77 ret i1 %.not 78} 79 80attributes #0 = { "target-cpu"="skylake-avx512" } 81