1 /*
2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #ifdef DRV_I915
8
9 #include <assert.h>
10 #include <errno.h>
11 #include <stdbool.h>
12 #include <stdio.h>
13 #include <string.h>
14 #include <sys/mman.h>
15 #include <unistd.h>
16 #include <xf86drm.h>
17
18 #include "drv_priv.h"
19 #include "external/i915_drm.h"
20 #include "helpers.h"
21 #include "util.h"
22
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
25
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
31
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
33
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
36
37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_Y_TILED,
38 I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR };
39
40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
41 DRM_FORMAT_MOD_LINEAR };
42
43 struct modifier_support_t {
44 const uint64_t *order;
45 uint32_t count;
46 };
47
48 struct i915_device {
49 uint32_t gen;
50 int32_t has_llc;
51 int32_t has_hw_protection;
52 struct modifier_support_t modifier;
53 int device_id;
54 bool is_adlp;
55 };
56
i915_info_from_device_id(struct i915_device * i915)57 static void i915_info_from_device_id(struct i915_device *i915)
58 {
59 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
60 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
61 const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
62 const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
63 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
64 const uint16_t adlp_ids[] = { 0x46A0, 0x46A1, 0x46A2, 0x46A3, 0x46A6,
65 0x46A8, 0x46AA, 0x462A, 0x4626, 0x4628,
66 0x46B0, 0x46B1, 0x46B2, 0x46B3, 0x46C0,
67 0x46C1, 0x46C2, 0x46C3 };
68 unsigned i;
69 i915->gen = 4;
70 i915->is_adlp = false;
71
72 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
73 if (gen3_ids[i] == i915->device_id)
74 i915->gen = 3;
75
76 /* Gen 11 */
77 for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
78 if (gen11_ids[i] == i915->device_id)
79 i915->gen = 11;
80
81 /* Gen 12 */
82 for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
83 if (gen12_ids[i] == i915->device_id)
84 i915->gen = 12;
85
86 for (i = 0; i < ARRAY_SIZE(adlp_ids); i++)
87 if (adlp_ids[i] == i915->device_id) {
88 i915->is_adlp = true;
89 i915->gen = 12;
90 }
91 }
92
i915_get_modifier_order(struct i915_device * i915)93 static void i915_get_modifier_order(struct i915_device *i915)
94 {
95 if (i915->gen == 11) {
96 i915->modifier.order = gen11_modifier_order;
97 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
98 } else {
99 i915->modifier.order = gen_modifier_order;
100 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
101 }
102 }
103
unset_flags(uint64_t current_flags,uint64_t mask)104 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
105 {
106 uint64_t value = current_flags & ~mask;
107 return value;
108 }
109
i915_add_combinations(struct driver * drv)110 static int i915_add_combinations(struct driver *drv)
111 {
112 struct i915_device *i915 = drv->priv;
113
114 const uint64_t scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
115 const uint64_t render = BO_USE_RENDER_MASK;
116 const uint64_t texture_only = BO_USE_TEXTURE_MASK;
117 // HW protected buffers also need to be scanned out.
118 const uint64_t hw_protected =
119 i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
120
121 const uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
122 BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY |
123 BO_USE_SW_WRITE_RARELY;
124
125 struct format_metadata metadata_linear = { .tiling = I915_TILING_NONE,
126 .priority = 1,
127 .modifier = DRM_FORMAT_MOD_LINEAR };
128
129 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
130 &metadata_linear, scanout_and_render);
131
132 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_linear,
133 render);
134
135 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats),
136 &metadata_linear, texture_only);
137
138 drv_modify_linear_combinations(drv);
139
140 /* NV12 format for camera, display, decoding and encoding. */
141 /* IPU3 camera ISP supports only NV12 output. */
142 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata_linear,
143 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
144 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
145 hw_protected);
146
147 /* Android CTS tests require this. */
148 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata_linear, BO_USE_SW_MASK);
149
150 /*
151 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
152 * from camera and input/output from hardware decoder/encoder.
153 */
154 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata_linear,
155 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
156 BO_USE_HW_VIDEO_ENCODER);
157
158 const uint64_t render_not_linear = unset_flags(render, linear_mask);
159 const uint64_t scanout_and_render_not_linear = render_not_linear | BO_USE_SCANOUT;
160
161 struct format_metadata metadata_x_tiled = { .tiling = I915_TILING_X,
162 .priority = 2,
163 .modifier = I915_FORMAT_MOD_X_TILED };
164
165 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_x_tiled,
166 render_not_linear);
167 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
168 &metadata_x_tiled, scanout_and_render_not_linear);
169
170 struct format_metadata metadata_y_tiled = { .tiling = I915_TILING_Y,
171 .priority = 3,
172 .modifier = I915_FORMAT_MOD_Y_TILED };
173
174 /* Support y-tiled NV12 and P010 for libva */
175 #ifdef I915_SCANOUT_Y_TILED
176 const uint64_t nv12_usage =
177 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
178 const uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected |
179 (i915->gen >= 11 ? BO_USE_SCANOUT : 0);
180 #else
181 const uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
182 const uint64_t p010_usage = nv12_usage;
183 #endif
184 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata_y_tiled, nv12_usage);
185 drv_add_combination(drv, DRM_FORMAT_P010, &metadata_y_tiled, p010_usage);
186
187 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_y_tiled,
188 render_not_linear);
189
190 // Y-tiled scanout isn't available on old platforms so we add
191 // |scanout_render_formats| without that USE flag.
192 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
193 &metadata_y_tiled, render_not_linear);
194 return 0;
195 }
196
i915_align_dimensions(struct bo * bo,uint32_t tiling,uint32_t * stride,uint32_t * aligned_height)197 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
198 uint32_t *aligned_height)
199 {
200 struct i915_device *i915 = bo->drv->priv;
201 uint32_t horizontal_alignment;
202 uint32_t vertical_alignment;
203
204 switch (tiling) {
205 default:
206 case I915_TILING_NONE:
207 /*
208 * The Intel GPU doesn't need any alignment in linear mode,
209 * but libva requires the allocation stride to be aligned to
210 * 16 bytes and height to 4 rows. Further, we round up the
211 * horizontal alignment so that row start on a cache line (64
212 * bytes).
213 */
214 #ifdef LINEAR_ALIGN_256
215 /*
216 * If we want to import these buffers to amdgpu they need to
217 * their match LINEAR_ALIGNED requirement of 256 byte alignement.
218 */
219 horizontal_alignment = 256;
220 #else
221 horizontal_alignment = 64;
222 #endif
223 vertical_alignment = 4;
224 break;
225
226 case I915_TILING_X:
227 horizontal_alignment = 512;
228 vertical_alignment = 8;
229 break;
230
231 case I915_TILING_Y:
232 if (i915->gen == 3) {
233 horizontal_alignment = 512;
234 vertical_alignment = 8;
235 } else {
236 horizontal_alignment = 128;
237 vertical_alignment = 32;
238 }
239 break;
240 }
241
242 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
243 if (i915->gen > 3) {
244 *stride = ALIGN(*stride, horizontal_alignment);
245 } else {
246 while (*stride > horizontal_alignment)
247 horizontal_alignment <<= 1;
248
249 *stride = horizontal_alignment;
250 }
251
252 /* stride must be power-of-two aligned for ADL-P tiled buffers*/
253 if (i915->is_adlp && (*stride > 1) && (tiling != I915_TILING_NONE))
254 *stride = 1 << (32 - __builtin_clz(*stride -1));
255
256 if (i915->gen <= 3 && *stride > 8192)
257 return -EINVAL;
258
259 return 0;
260 }
261
i915_clflush(void * start,size_t size)262 static void i915_clflush(void *start, size_t size)
263 {
264 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
265 void *end = (void *)((uintptr_t)start + size);
266
267 __builtin_ia32_mfence();
268 while (p < end) {
269 __builtin_ia32_clflush(p);
270 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
271 }
272 }
273
i915_init(struct driver * drv)274 static int i915_init(struct driver *drv)
275 {
276 int ret;
277 struct i915_device *i915;
278 drm_i915_getparam_t get_param = { 0 };
279
280 i915 = calloc(1, sizeof(*i915));
281 if (!i915)
282 return -ENOMEM;
283
284 get_param.param = I915_PARAM_CHIPSET_ID;
285 get_param.value = &(i915->device_id);
286 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
287 if (ret) {
288 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
289 free(i915);
290 return -EINVAL;
291 }
292 /* must call before i915->gen is used anywhere else */
293 i915_info_from_device_id(i915);
294
295 i915_get_modifier_order(i915);
296
297 memset(&get_param, 0, sizeof(get_param));
298 get_param.param = I915_PARAM_HAS_LLC;
299 get_param.value = &i915->has_llc;
300 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
301 if (ret) {
302 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
303 free(i915);
304 return -EINVAL;
305 }
306
307 if (i915->gen >= 12)
308 i915->has_hw_protection = 1;
309
310 drv->priv = i915;
311 return i915_add_combinations(drv);
312 }
313
314 /*
315 * Returns true if the height of a buffer of the given format should be aligned
316 * to the largest coded unit (LCU) assuming that it will be used for video. This
317 * is based on gmmlib's GmmIsYUVFormatLCUAligned().
318 */
i915_format_needs_LCU_alignment(uint32_t format,size_t plane,const struct i915_device * i915)319 static bool i915_format_needs_LCU_alignment(uint32_t format, size_t plane, const struct i915_device* i915)
320 {
321 switch (format) {
322 case DRM_FORMAT_NV12:
323 case DRM_FORMAT_P010:
324 case DRM_FORMAT_P016:
325 return (i915->gen == 11 || i915->gen == 12) && plane == 1;
326 }
327 return false;
328 }
329
i915_bo_from_format(struct bo * bo,uint32_t width,uint32_t height,uint32_t format)330 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
331 {
332 uint32_t offset;
333 size_t plane;
334 int ret, pagesize;
335 struct i915_device *i915 = bo->drv->priv;
336
337 offset = 0;
338 pagesize = getpagesize();
339
340 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
341 uint32_t stride = drv_stride_from_format(format, width, plane);
342 uint32_t plane_height = drv_height_from_format(format, height, plane);
343
344 if (bo->meta.tiling != I915_TILING_NONE)
345 assert(IS_ALIGNED(offset, pagesize));
346
347 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
348 if (ret)
349 return ret;
350
351 if (i915_format_needs_LCU_alignment(format, plane, i915)) {
352 /*
353 * Align the height of the V plane for certain formats to the
354 * largest coded unit (assuming that this BO may be used for video)
355 * to be consistent with gmmlib.
356 */
357 plane_height = ALIGN(plane_height, 64);
358 }
359
360 bo->meta.strides[plane] = stride;
361 bo->meta.sizes[plane] = stride * plane_height;
362 bo->meta.offsets[plane] = offset;
363 offset += bo->meta.sizes[plane];
364 }
365
366 bo->meta.total_size = ALIGN(offset, pagesize);
367
368 return 0;
369 }
370
i915_bo_compute_metadata(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags,const uint64_t * modifiers,uint32_t count)371 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
372 uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
373 {
374 uint64_t modifier;
375 struct i915_device *i915 = bo->drv->priv;
376 bool huge_bo = (i915->gen < 11) && (width > 4096);
377
378 if (modifiers) {
379 modifier =
380 drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
381 } else {
382 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
383 if (!combo)
384 return -EINVAL;
385 modifier = combo->metadata.modifier;
386 }
387
388 /*
389 * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
390 * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
391 */
392 if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
393 modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
394 uint32_t i;
395 for (i = 0; modifiers && i < count; i++) {
396 if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
397 break;
398 }
399 if (i == count)
400 modifier = DRM_FORMAT_MOD_LINEAR;
401 else
402 modifier = I915_FORMAT_MOD_X_TILED;
403 }
404
405 /*
406 * Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
407 * Pick y tiled modifier if it has been passed in, otherwise use linear
408 */
409 if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
410 uint32_t i;
411 for (i = 0; modifiers && i < count; i++) {
412 if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
413 break;
414 }
415 if (i == count)
416 modifier = DRM_FORMAT_MOD_LINEAR;
417 else
418 modifier = I915_FORMAT_MOD_Y_TILED;
419 }
420
421 switch (modifier) {
422 case DRM_FORMAT_MOD_LINEAR:
423 bo->meta.tiling = I915_TILING_NONE;
424 break;
425 case I915_FORMAT_MOD_X_TILED:
426 bo->meta.tiling = I915_TILING_X;
427 break;
428 case I915_FORMAT_MOD_Y_TILED:
429 case I915_FORMAT_MOD_Y_TILED_CCS:
430 bo->meta.tiling = I915_TILING_Y;
431 break;
432 }
433
434 bo->meta.format_modifier = modifier;
435
436 if (format == DRM_FORMAT_YVU420_ANDROID) {
437 /*
438 * We only need to be able to use this as a linear texture,
439 * which doesn't put any HW restrictions on how we lay it
440 * out. The Android format does require the stride to be a
441 * multiple of 16 and expects the Cr and Cb stride to be
442 * ALIGN(Y_stride / 2, 16), which we can make happen by
443 * aligning to 32 bytes here.
444 */
445 uint32_t stride = ALIGN(width, 32);
446 drv_bo_from_format(bo, stride, height, format);
447 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
448 /*
449 * For compressed surfaces, we need a color control surface
450 * (CCS). Color compression is only supported for Y tiled
451 * surfaces, and for each 32x16 tiles in the main surface we
452 * need a tile in the control surface. Y tiles are 128 bytes
453 * wide and 32 lines tall and we use that to first compute the
454 * width and height in tiles of the main surface. stride and
455 * height are already multiples of 128 and 32, respectively:
456 */
457 uint32_t stride = drv_stride_from_format(format, width, 0);
458 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
459 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
460 uint32_t size = width_in_tiles * height_in_tiles * 4096;
461 uint32_t offset = 0;
462
463 bo->meta.strides[0] = width_in_tiles * 128;
464 bo->meta.sizes[0] = size;
465 bo->meta.offsets[0] = offset;
466 offset += size;
467
468 /*
469 * Now, compute the width and height in tiles of the control
470 * surface by dividing and rounding up.
471 */
472 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
473 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
474 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
475
476 /*
477 * With stride and height aligned to y tiles, offset is
478 * already a multiple of 4096, which is the required alignment
479 * of the CCS.
480 */
481 bo->meta.strides[1] = ccs_width_in_tiles * 128;
482 bo->meta.sizes[1] = ccs_size;
483 bo->meta.offsets[1] = offset;
484 offset += ccs_size;
485
486 bo->meta.num_planes = 2;
487 bo->meta.total_size = offset;
488 } else {
489 i915_bo_from_format(bo, width, height, format);
490 }
491 return 0;
492 }
493
i915_bo_create_from_metadata(struct bo * bo)494 static int i915_bo_create_from_metadata(struct bo *bo)
495 {
496 int ret;
497 size_t plane;
498 uint32_t gem_handle;
499 struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
500 struct i915_device *i915 = bo->drv->priv;
501
502 if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
503 struct drm_i915_gem_object_param protected_param = {
504 .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
505 .data = 1,
506 };
507
508 struct drm_i915_gem_create_ext_setparam setparam_protected = {
509 .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
510 .param = protected_param,
511 };
512
513 struct drm_i915_gem_create_ext create_ext = {
514 .size = bo->meta.total_size,
515 .extensions = (uintptr_t)&setparam_protected,
516 };
517
518 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
519 if (ret) {
520 drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
521 create_ext.size);
522 return -errno;
523 }
524
525 gem_handle = create_ext.handle;
526 } else {
527 struct drm_i915_gem_create gem_create = { 0 };
528 gem_create.size = bo->meta.total_size;
529 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
530 if (ret) {
531 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
532 return -errno;
533 }
534
535 gem_handle = gem_create.handle;
536 }
537
538 for (plane = 0; plane < bo->meta.num_planes; plane++)
539 bo->handles[plane].u32 = gem_handle;
540
541 gem_set_tiling.handle = bo->handles[0].u32;
542 gem_set_tiling.tiling_mode = bo->meta.tiling;
543 gem_set_tiling.stride = bo->meta.strides[0];
544
545 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
546 if (ret) {
547 struct drm_gem_close gem_close = { 0 };
548 gem_close.handle = bo->handles[0].u32;
549 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
550
551 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
552 return -errno;
553 }
554
555 return 0;
556 }
557
i915_close(struct driver * drv)558 static void i915_close(struct driver *drv)
559 {
560 free(drv->priv);
561 drv->priv = NULL;
562 }
563
i915_bo_import(struct bo * bo,struct drv_import_fd_data * data)564 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
565 {
566 int ret;
567 struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
568
569 ret = drv_prime_bo_import(bo, data);
570 if (ret)
571 return ret;
572
573 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
574 gem_get_tiling.handle = bo->handles[0].u32;
575
576 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
577 if (ret) {
578 drv_gem_bo_destroy(bo);
579 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
580 return ret;
581 }
582
583 bo->meta.tiling = gem_get_tiling.tiling_mode;
584 return 0;
585 }
586
i915_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)587 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
588 {
589 int ret;
590 void *addr = MAP_FAILED;
591
592 if (bo->meta.format_modifier == I915_FORMAT_MOD_Y_TILED_CCS)
593 return MAP_FAILED;
594
595 if (bo->meta.tiling == I915_TILING_NONE) {
596 struct drm_i915_gem_mmap gem_map = { 0 };
597 /* TODO(b/118799155): We don't seem to have a good way to
598 * detect the use cases for which WC mapping is really needed.
599 * The current heuristic seems overly coarse and may be slowing
600 * down some other use cases unnecessarily.
601 *
602 * For now, care must be taken not to use WC mappings for
603 * Renderscript and camera use cases, as they're
604 * performance-sensitive. */
605 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
606 !(bo->meta.use_flags &
607 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
608 gem_map.flags = I915_MMAP_WC;
609
610 gem_map.handle = bo->handles[0].u32;
611 gem_map.offset = 0;
612 gem_map.size = bo->meta.total_size;
613
614 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
615 /* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
616 * file and returns a user space address directly, ie,
617 * doesn't go through mmap. If we try that on a
618 * dma-buf that doesn't have a shm file, i915.ko
619 * returns ENXIO. Fall through to
620 * DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
621 * will mmap on the drm fd instead. */
622 if (ret == 0)
623 addr = (void *)(uintptr_t)gem_map.addr_ptr;
624 }
625
626 if (addr == MAP_FAILED) {
627 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
628
629 gem_map.handle = bo->handles[0].u32;
630 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
631 if (ret) {
632 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
633 return MAP_FAILED;
634 }
635
636 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
637 bo->drv->fd, gem_map.offset);
638 }
639
640 if (addr == MAP_FAILED) {
641 drv_log("i915 GEM mmap failed\n");
642 return addr;
643 }
644
645 vma->length = bo->meta.total_size;
646 return addr;
647 }
648
i915_bo_invalidate(struct bo * bo,struct mapping * mapping)649 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
650 {
651 int ret;
652 struct drm_i915_gem_set_domain set_domain = { 0 };
653
654 set_domain.handle = bo->handles[0].u32;
655 if (bo->meta.tiling == I915_TILING_NONE) {
656 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
657 if (mapping->vma->map_flags & BO_MAP_WRITE)
658 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
659 } else {
660 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
661 if (mapping->vma->map_flags & BO_MAP_WRITE)
662 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
663 }
664
665 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
666 if (ret) {
667 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
668 return ret;
669 }
670
671 return 0;
672 }
673
i915_bo_flush(struct bo * bo,struct mapping * mapping)674 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
675 {
676 struct i915_device *i915 = bo->drv->priv;
677 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
678 i915_clflush(mapping->vma->addr, mapping->vma->length);
679
680 return 0;
681 }
682
683 const struct backend backend_i915 = {
684 .name = "i915",
685 .init = i915_init,
686 .close = i915_close,
687 .bo_compute_metadata = i915_bo_compute_metadata,
688 .bo_create_from_metadata = i915_bo_create_from_metadata,
689 .bo_destroy = drv_gem_bo_destroy,
690 .bo_import = i915_bo_import,
691 .bo_map = i915_bo_map,
692 .bo_unmap = drv_bo_munmap,
693 .bo_invalidate = i915_bo_invalidate,
694 .bo_flush = i915_bo_flush,
695 .resolve_format = drv_resolve_format_helper,
696 };
697
698 #endif
699