1 /*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdatomic.h>
10 #include <stdint.h>
11 #include <string.h>
12 #include <sys/mman.h>
13 #include <xf86drm.h>
14
15 #include "drv_priv.h"
16 #include "external/virgl_hw.h"
17 #include "external/virgl_protocol.h"
18 #include "external/virtgpu_drm.h"
19 #include "helpers.h"
20 #include "util.h"
21 #include "virtgpu.h"
22
23 #define PIPE_TEXTURE_2D 2
24
25 #define MESA_LLVMPIPE_TILE_ORDER 6
26 #define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
27
28 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
29 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
30 DRM_FORMAT_XRGB8888 };
31
32 static const uint32_t dumb_texture_source_formats[] = {
33 DRM_FORMAT_R8, DRM_FORMAT_R16, DRM_FORMAT_YVU420,
34 DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_YVU420_ANDROID
35 };
36
37 static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21,
38 DRM_FORMAT_R8, DRM_FORMAT_R16,
39 DRM_FORMAT_RG88, DRM_FORMAT_YVU420_ANDROID };
40
41 extern struct virtgpu_param params[];
42
43 struct virgl_priv {
44 int caps_is_v2;
45 union virgl_caps caps;
46 int host_gbm_enabled;
47 atomic_int next_blob_id;
48 };
49
translate_format(uint32_t drm_fourcc)50 static uint32_t translate_format(uint32_t drm_fourcc)
51 {
52 switch (drm_fourcc) {
53 case DRM_FORMAT_BGR888:
54 case DRM_FORMAT_RGB888:
55 return VIRGL_FORMAT_R8G8B8_UNORM;
56 case DRM_FORMAT_XRGB8888:
57 return VIRGL_FORMAT_B8G8R8X8_UNORM;
58 case DRM_FORMAT_ARGB8888:
59 return VIRGL_FORMAT_B8G8R8A8_UNORM;
60 case DRM_FORMAT_XBGR8888:
61 return VIRGL_FORMAT_R8G8B8X8_UNORM;
62 case DRM_FORMAT_ABGR8888:
63 return VIRGL_FORMAT_R8G8B8A8_UNORM;
64 case DRM_FORMAT_ABGR16161616F:
65 return VIRGL_FORMAT_R16G16B16A16_FLOAT;
66 case DRM_FORMAT_RGB565:
67 return VIRGL_FORMAT_B5G6R5_UNORM;
68 case DRM_FORMAT_R8:
69 return VIRGL_FORMAT_R8_UNORM;
70 case DRM_FORMAT_R16:
71 return VIRGL_FORMAT_R16_UNORM;
72 case DRM_FORMAT_RG88:
73 return VIRGL_FORMAT_R8G8_UNORM;
74 case DRM_FORMAT_NV12:
75 return VIRGL_FORMAT_NV12;
76 case DRM_FORMAT_NV21:
77 return VIRGL_FORMAT_NV21;
78 case DRM_FORMAT_YVU420:
79 case DRM_FORMAT_YVU420_ANDROID:
80 return VIRGL_FORMAT_YV12;
81 default:
82 drv_log("Unhandled format:%d\n", drm_fourcc);
83 return 0;
84 }
85 }
86
virgl_bitmask_supports_format(struct virgl_supported_format_mask * supported,uint32_t drm_format)87 static bool virgl_bitmask_supports_format(struct virgl_supported_format_mask *supported,
88 uint32_t drm_format)
89 {
90 uint32_t virgl_format = translate_format(drm_format);
91 if (!virgl_format)
92 return false;
93
94 uint32_t bitmask_index = virgl_format / 32;
95 uint32_t bit_index = virgl_format % 32;
96 return supported->bitmask[bitmask_index] & (1 << bit_index);
97 }
98
99 // The metadata generated here for emulated buffers is slightly different than the metadata
100 // generated by drv_bo_from_format. In order to simplify transfers in the flush and invalidate
101 // functions below, the emulated buffers are oversized. For example, ignoring stride alignment
102 // requirements to demonstrate, a 6x6 YUV420 image buffer might have the following layout from
103 // drv_bo_from_format:
104 //
105 // | Y | Y | Y | Y | Y | Y |
106 // | Y | Y | Y | Y | Y | Y |
107 // | Y | Y | Y | Y | Y | Y |
108 // | Y | Y | Y | Y | Y | Y |
109 // | Y | Y | Y | Y | Y | Y |
110 // | Y | Y | Y | Y | Y | Y |
111 // | U | U | U | U | U | U |
112 // | U | U | U | V | V | V |
113 // | V | V | V | V | V | V |
114 //
115 // where each plane immediately follows the previous plane in memory. This layout makes it
116 // difficult to compute the transfers needed for example when the middle 2x2 region of the
117 // image is locked and needs to be flushed/invalidated.
118 //
119 // Emulated multi-plane buffers instead have a layout of:
120 //
121 // | Y | Y | Y | Y | Y | Y |
122 // | Y | Y | Y | Y | Y | Y |
123 // | Y | Y | Y | Y | Y | Y |
124 // | Y | Y | Y | Y | Y | Y |
125 // | Y | Y | Y | Y | Y | Y |
126 // | Y | Y | Y | Y | Y | Y |
127 // | U | U | U | | | |
128 // | U | U | U | | | |
129 // | U | U | U | | | |
130 // | V | V | V | | | |
131 // | V | V | V | | | |
132 // | V | V | V | | | |
133 //
134 // where each plane is placed as a sub-image (albeit with a very large stride) in order to
135 // simplify transfers into 3 sub-image transfers for the above example.
136 //
137 // Additional note: the V-plane is not placed to the right of the U-plane due to some
138 // observed failures in media framework code which assumes the V-plane is not
139 // "row-interlaced" with the U-plane.
virgl_get_emulated_metadata(const struct bo * bo,struct bo_metadata * metadata)140 static void virgl_get_emulated_metadata(const struct bo *bo, struct bo_metadata *metadata)
141 {
142 uint32_t y_plane_height;
143 uint32_t c_plane_height;
144 uint32_t original_width = bo->meta.width;
145 uint32_t original_height = bo->meta.height;
146
147 metadata->format = DRM_FORMAT_R8;
148 switch (bo->meta.format) {
149 case DRM_FORMAT_NV12:
150 case DRM_FORMAT_NV21:
151 // Bi-planar
152 metadata->num_planes = 2;
153
154 y_plane_height = original_height;
155 c_plane_height = DIV_ROUND_UP(original_height, 2);
156
157 metadata->width = original_width;
158 metadata->height = y_plane_height + c_plane_height;
159
160 // Y-plane (full resolution)
161 metadata->strides[0] = metadata->width;
162 metadata->offsets[0] = 0;
163 metadata->sizes[0] = metadata->width * y_plane_height;
164
165 // CbCr-plane (half resolution, interleaved, placed below Y-plane)
166 metadata->strides[1] = metadata->width;
167 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
168 metadata->sizes[1] = metadata->width * c_plane_height;
169
170 metadata->total_size = metadata->width * metadata->height;
171 break;
172 case DRM_FORMAT_YVU420:
173 case DRM_FORMAT_YVU420_ANDROID:
174 // Tri-planar
175 metadata->num_planes = 3;
176
177 y_plane_height = original_height;
178 c_plane_height = DIV_ROUND_UP(original_height, 2);
179
180 metadata->width = ALIGN(original_width, 32);
181 metadata->height = y_plane_height + (2 * c_plane_height);
182
183 // Y-plane (full resolution)
184 metadata->strides[0] = metadata->width;
185 metadata->offsets[0] = 0;
186 metadata->sizes[0] = metadata->width * original_height;
187
188 // Cb-plane (half resolution, placed below Y-plane)
189 metadata->strides[1] = metadata->width;
190 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
191 metadata->sizes[1] = metadata->width * c_plane_height;
192
193 // Cr-plane (half resolution, placed below Cb-plane)
194 metadata->strides[2] = metadata->width;
195 metadata->offsets[2] = metadata->offsets[1] + metadata->sizes[1];
196 metadata->sizes[2] = metadata->width * c_plane_height;
197
198 metadata->total_size = metadata->width * metadata->height;
199 break;
200 default:
201 break;
202 }
203 }
204
205 struct virtio_transfers_params {
206 size_t xfers_needed;
207 struct rectangle xfer_boxes[DRV_MAX_PLANES];
208 };
209
virgl_get_emulated_transfers_params(const struct bo * bo,const struct rectangle * transfer_box,struct virtio_transfers_params * xfer_params)210 static void virgl_get_emulated_transfers_params(const struct bo *bo,
211 const struct rectangle *transfer_box,
212 struct virtio_transfers_params *xfer_params)
213 {
214 uint32_t y_plane_height;
215 uint32_t c_plane_height;
216 struct bo_metadata emulated_metadata;
217
218 if (transfer_box->x == 0 && transfer_box->y == 0 && transfer_box->width == bo->meta.width &&
219 transfer_box->height == bo->meta.height) {
220 virgl_get_emulated_metadata(bo, &emulated_metadata);
221
222 xfer_params->xfers_needed = 1;
223 xfer_params->xfer_boxes[0].x = 0;
224 xfer_params->xfer_boxes[0].y = 0;
225 xfer_params->xfer_boxes[0].width = emulated_metadata.width;
226 xfer_params->xfer_boxes[0].height = emulated_metadata.height;
227
228 return;
229 }
230
231 switch (bo->meta.format) {
232 case DRM_FORMAT_NV12:
233 case DRM_FORMAT_NV21:
234 // Bi-planar
235 xfer_params->xfers_needed = 2;
236
237 y_plane_height = bo->meta.height;
238 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
239
240 // Y-plane (full resolution)
241 xfer_params->xfer_boxes[0].x = transfer_box->x;
242 xfer_params->xfer_boxes[0].y = transfer_box->y;
243 xfer_params->xfer_boxes[0].width = transfer_box->width;
244 xfer_params->xfer_boxes[0].height = transfer_box->height;
245
246 // CbCr-plane (half resolution, interleaved, placed below Y-plane)
247 xfer_params->xfer_boxes[1].x = transfer_box->x;
248 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
249 xfer_params->xfer_boxes[1].width = transfer_box->width;
250 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
251
252 break;
253 case DRM_FORMAT_YVU420:
254 case DRM_FORMAT_YVU420_ANDROID:
255 // Tri-planar
256 xfer_params->xfers_needed = 3;
257
258 y_plane_height = bo->meta.height;
259 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
260
261 // Y-plane (full resolution)
262 xfer_params->xfer_boxes[0].x = transfer_box->x;
263 xfer_params->xfer_boxes[0].y = transfer_box->y;
264 xfer_params->xfer_boxes[0].width = transfer_box->width;
265 xfer_params->xfer_boxes[0].height = transfer_box->height;
266
267 // Cb-plane (half resolution, placed below Y-plane)
268 xfer_params->xfer_boxes[1].x = transfer_box->x;
269 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
270 xfer_params->xfer_boxes[1].width = DIV_ROUND_UP(transfer_box->width, 2);
271 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
272
273 // Cr-plane (half resolution, placed below Cb-plane)
274 xfer_params->xfer_boxes[2].x = transfer_box->x;
275 xfer_params->xfer_boxes[2].y = transfer_box->y + y_plane_height + c_plane_height;
276 xfer_params->xfer_boxes[2].width = DIV_ROUND_UP(transfer_box->width, 2);
277 xfer_params->xfer_boxes[2].height = DIV_ROUND_UP(transfer_box->height, 2);
278
279 break;
280 }
281 }
282
virgl_supports_combination_natively(struct driver * drv,uint32_t drm_format,uint64_t use_flags)283 static bool virgl_supports_combination_natively(struct driver *drv, uint32_t drm_format,
284 uint64_t use_flags)
285 {
286 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
287
288 if (priv->caps.max_version == 0)
289 return true;
290
291 if ((use_flags & BO_USE_RENDERING) &&
292 !virgl_bitmask_supports_format(&priv->caps.v1.render, drm_format))
293 return false;
294
295 if ((use_flags & BO_USE_TEXTURE) &&
296 !virgl_bitmask_supports_format(&priv->caps.v1.sampler, drm_format))
297 return false;
298
299 if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
300 !virgl_bitmask_supports_format(&priv->caps.v2.scanout, drm_format))
301 return false;
302
303 return true;
304 }
305
306 // For virtio backends that do not support formats natively (e.g. multi-planar formats are not
307 // supported in virglrenderer when gbm is unavailable on the host machine), whether or not the
308 // format and usage combination can be handled as a blob (byte buffer).
virgl_supports_combination_through_emulation(struct driver * drv,uint32_t drm_format,uint64_t use_flags)309 static bool virgl_supports_combination_through_emulation(struct driver *drv, uint32_t drm_format,
310 uint64_t use_flags)
311 {
312 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
313
314 // Only enable emulation on non-gbm virtio backends.
315 if (priv->host_gbm_enabled)
316 return false;
317
318 if (use_flags & (BO_USE_RENDERING | BO_USE_SCANOUT))
319 return false;
320
321 if (!virgl_supports_combination_natively(drv, DRM_FORMAT_R8, use_flags))
322 return false;
323
324 return drm_format == DRM_FORMAT_NV12 || drm_format == DRM_FORMAT_NV21 ||
325 drm_format == DRM_FORMAT_YVU420 || drm_format == DRM_FORMAT_YVU420_ANDROID;
326 }
327
328 // Adds the given buffer combination to the list of supported buffer combinations if the
329 // combination is supported by the virtio backend.
virgl_add_combination(struct driver * drv,uint32_t drm_format,struct format_metadata * metadata,uint64_t use_flags)330 static void virgl_add_combination(struct driver *drv, uint32_t drm_format,
331 struct format_metadata *metadata, uint64_t use_flags)
332 {
333 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
334
335 if (params[param_3d].value && priv->caps.max_version >= 1) {
336 if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
337 !virgl_supports_combination_natively(drv, drm_format, use_flags)) {
338 drv_log("Scanout format: %d\n", drm_format);
339 use_flags &= ~BO_USE_SCANOUT;
340 }
341
342 if (!virgl_supports_combination_natively(drv, drm_format, use_flags) &&
343 !virgl_supports_combination_through_emulation(drv, drm_format, use_flags)) {
344 drv_log("Skipping unsupported combination format:%d\n", drm_format);
345 return;
346 }
347 }
348
349 drv_add_combination(drv, drm_format, metadata, use_flags);
350 }
351
352 // Adds each given buffer combination to the list of supported buffer combinations if the
353 // combination supported by the virtio backend.
virgl_add_combinations(struct driver * drv,const uint32_t * drm_formats,uint32_t num_formats,struct format_metadata * metadata,uint64_t use_flags)354 static void virgl_add_combinations(struct driver *drv, const uint32_t *drm_formats,
355 uint32_t num_formats, struct format_metadata *metadata,
356 uint64_t use_flags)
357 {
358 uint32_t i;
359
360 for (i = 0; i < num_formats; i++)
361 virgl_add_combination(drv, drm_formats[i], metadata, use_flags);
362 }
363
virtio_dumb_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)364 static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
365 uint64_t use_flags)
366 {
367 if (bo->meta.format != DRM_FORMAT_R8) {
368 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
369 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
370 }
371
372 return drv_dumb_bo_create_ex(bo, width, height, format, use_flags, BO_QUIRK_DUMB32BPP);
373 }
374
handle_flag(uint64_t * flag,uint64_t check_flag,uint32_t * bind,uint32_t virgl_bind)375 static inline void handle_flag(uint64_t *flag, uint64_t check_flag, uint32_t *bind,
376 uint32_t virgl_bind)
377 {
378 if ((*flag) & check_flag) {
379 (*flag) &= ~check_flag;
380 (*bind) |= virgl_bind;
381 }
382 }
383
compute_virgl_bind_flags(uint64_t use_flags,uint32_t format)384 static uint32_t compute_virgl_bind_flags(uint64_t use_flags, uint32_t format)
385 {
386 /* In crosvm, VIRGL_BIND_SHARED means minigbm will allocate, not virglrenderer. */
387 uint32_t bind = VIRGL_BIND_SHARED;
388
389 handle_flag(&use_flags, BO_USE_TEXTURE, &bind, VIRGL_BIND_SAMPLER_VIEW);
390 handle_flag(&use_flags, BO_USE_RENDERING, &bind, VIRGL_BIND_RENDER_TARGET);
391 handle_flag(&use_flags, BO_USE_SCANOUT, &bind, VIRGL_BIND_SCANOUT);
392 handle_flag(&use_flags, BO_USE_CURSOR, &bind, VIRGL_BIND_CURSOR);
393 handle_flag(&use_flags, BO_USE_LINEAR, &bind, VIRGL_BIND_LINEAR);
394
395 if (use_flags & BO_USE_PROTECTED) {
396 handle_flag(&use_flags, BO_USE_PROTECTED, &bind, VIRGL_BIND_MINIGBM_PROTECTED);
397 } else {
398 // Make sure we don't set both flags, since that could be mistaken for
399 // protected. Give OFTEN priority over RARELY.
400 if (use_flags & BO_USE_SW_READ_OFTEN) {
401 handle_flag(&use_flags, BO_USE_SW_READ_OFTEN, &bind,
402 VIRGL_BIND_MINIGBM_SW_READ_OFTEN);
403 } else {
404 handle_flag(&use_flags, BO_USE_SW_READ_RARELY, &bind,
405 VIRGL_BIND_MINIGBM_SW_READ_RARELY);
406 }
407 if (use_flags & BO_USE_SW_WRITE_OFTEN) {
408 handle_flag(&use_flags, BO_USE_SW_WRITE_OFTEN, &bind,
409 VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN);
410 } else {
411 handle_flag(&use_flags, BO_USE_SW_WRITE_RARELY, &bind,
412 VIRGL_BIND_MINIGBM_SW_WRITE_RARELY);
413 }
414 }
415
416 handle_flag(&use_flags, BO_USE_CAMERA_WRITE, &bind, VIRGL_BIND_MINIGBM_CAMERA_WRITE);
417 handle_flag(&use_flags, BO_USE_CAMERA_READ, &bind, VIRGL_BIND_MINIGBM_CAMERA_READ);
418 handle_flag(&use_flags, BO_USE_HW_VIDEO_DECODER, &bind,
419 VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER);
420 handle_flag(&use_flags, BO_USE_HW_VIDEO_ENCODER, &bind,
421 VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER);
422
423 /*
424 * HACK: This is for HAL_PIXEL_FORMAT_YV12 buffers allocated by arcvm. None of
425 * our platforms can display YV12, so we can treat as a SW buffer. Remove once
426 * this can be intelligently resolved in the guest. Also see gbm_bo_create.
427 */
428 if (format == DRM_FORMAT_YVU420_ANDROID)
429 bind |= VIRGL_BIND_LINEAR;
430
431 if (use_flags)
432 drv_log("Unhandled bo use flag: %llx\n", (unsigned long long)use_flags);
433
434 return bind;
435 }
436
virgl_3d_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)437 static int virgl_3d_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
438 uint64_t use_flags)
439 {
440 int ret;
441 size_t i;
442 uint32_t stride;
443 struct drm_virtgpu_resource_create res_create = { 0 };
444 struct bo_metadata emulated_metadata;
445
446 if (virgl_supports_combination_natively(bo->drv, format, use_flags)) {
447 stride = drv_stride_from_format(format, width, 0);
448 drv_bo_from_format(bo, stride, height, format);
449 } else {
450 assert(virgl_supports_combination_through_emulation(bo->drv, format, use_flags));
451
452 virgl_get_emulated_metadata(bo, &emulated_metadata);
453
454 format = emulated_metadata.format;
455 width = emulated_metadata.width;
456 height = emulated_metadata.height;
457 for (i = 0; i < emulated_metadata.num_planes; i++) {
458 bo->meta.strides[i] = emulated_metadata.strides[i];
459 bo->meta.offsets[i] = emulated_metadata.offsets[i];
460 bo->meta.sizes[i] = emulated_metadata.sizes[i];
461 }
462 bo->meta.total_size = emulated_metadata.total_size;
463 }
464
465 /*
466 * Setting the target is intended to ensure this resource gets bound as a 2D
467 * texture in the host renderer's GL state. All of these resource properties are
468 * sent unchanged by the kernel to the host, which in turn sends them unchanged to
469 * virglrenderer. When virglrenderer makes a resource, it will convert the target
470 * enum to the equivalent one in GL and then bind the resource to that target.
471 */
472
473 res_create.target = PIPE_TEXTURE_2D;
474 res_create.format = translate_format(format);
475 res_create.bind = compute_virgl_bind_flags(use_flags, format);
476 res_create.width = width;
477 res_create.height = height;
478
479 /* For virgl 3D */
480 res_create.depth = 1;
481 res_create.array_size = 1;
482 res_create.last_level = 0;
483 res_create.nr_samples = 0;
484
485 res_create.size = ALIGN(bo->meta.total_size, PAGE_SIZE); // PAGE_SIZE = 0x1000
486 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
487 if (ret) {
488 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n", strerror(errno));
489 return ret;
490 }
491
492 for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++)
493 bo->handles[plane].u32 = res_create.bo_handle;
494
495 return 0;
496 }
497
virgl_3d_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)498 static void *virgl_3d_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
499 {
500 int ret;
501 struct drm_virtgpu_map gem_map = { 0 };
502
503 gem_map.handle = bo->handles[0].u32;
504 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
505 if (ret) {
506 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
507 return MAP_FAILED;
508 }
509
510 vma->length = bo->meta.total_size;
511 return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
512 gem_map.offset);
513 }
514
virgl_get_caps(struct driver * drv,union virgl_caps * caps,int * caps_is_v2)515 static int virgl_get_caps(struct driver *drv, union virgl_caps *caps, int *caps_is_v2)
516 {
517 int ret;
518 struct drm_virtgpu_get_caps cap_args = { 0 };
519
520 *caps_is_v2 = 0;
521 cap_args.addr = (unsigned long long)caps;
522 if (params[param_capset_fix].value) {
523 *caps_is_v2 = 1;
524 cap_args.cap_set_id = 2;
525 cap_args.size = sizeof(union virgl_caps);
526 } else {
527 cap_args.cap_set_id = 1;
528 cap_args.size = sizeof(struct virgl_caps_v1);
529 }
530
531 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
532 if (ret) {
533 drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
534 *caps_is_v2 = 0;
535
536 // Fallback to v1
537 cap_args.cap_set_id = 1;
538 cap_args.size = sizeof(struct virgl_caps_v1);
539
540 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
541 if (ret)
542 drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
543 }
544
545 return ret;
546 }
547
virgl_init_params_and_caps(struct driver * drv)548 static void virgl_init_params_and_caps(struct driver *drv)
549 {
550 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
551 if (params[param_3d].value) {
552 virgl_get_caps(drv, &priv->caps, &priv->caps_is_v2);
553
554 // We use two criteria to determine whether host minigbm is used on the host for
555 // swapchain allocations.
556 //
557 // (1) Host minigbm is only available via virglrenderer, and only virglrenderer
558 // advertises capabilities.
559 // (2) Only host minigbm doesn't emulate YUV formats. Checking this is a bit of a
560 // proxy, but it works.
561 priv->host_gbm_enabled =
562 priv->caps.max_version > 0 &&
563 virgl_supports_combination_natively(drv, DRM_FORMAT_NV12, BO_USE_TEXTURE);
564 }
565 }
566
virgl_init(struct driver * drv)567 static int virgl_init(struct driver *drv)
568 {
569 struct virgl_priv *priv;
570
571 priv = calloc(1, sizeof(*priv));
572 drv->priv = priv;
573
574 virgl_init_params_and_caps(drv);
575
576 if (params[param_3d].value) {
577 /* This doesn't mean host can scanout everything, it just means host
578 * hypervisor can show it. */
579 virgl_add_combinations(drv, render_target_formats,
580 ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
581 BO_USE_RENDER_MASK | BO_USE_SCANOUT);
582 virgl_add_combinations(drv, texture_source_formats,
583 ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
584 BO_USE_TEXTURE_MASK);
585 } else {
586 /* Virtio primary plane only allows this format. */
587 virgl_add_combination(drv, DRM_FORMAT_XRGB8888, &LINEAR_METADATA,
588 BO_USE_RENDER_MASK | BO_USE_SCANOUT);
589 /* Virtio cursor plane only allows this format and Chrome cannot live without
590 * ARGB888 renderable format. */
591 virgl_add_combination(drv, DRM_FORMAT_ARGB8888, &LINEAR_METADATA,
592 BO_USE_RENDER_MASK | BO_USE_CURSOR);
593 /* Android needs more, but they cannot be bound as scanouts anymore after
594 * "drm/virtio: fix DRM_FORMAT_* handling" */
595 virgl_add_combinations(drv, render_target_formats,
596 ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
597 BO_USE_RENDER_MASK);
598 virgl_add_combinations(drv, dumb_texture_source_formats,
599 ARRAY_SIZE(dumb_texture_source_formats), &LINEAR_METADATA,
600 BO_USE_TEXTURE_MASK);
601 virgl_add_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
602 BO_USE_SW_MASK | BO_USE_LINEAR);
603 virgl_add_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
604 BO_USE_SW_MASK | BO_USE_LINEAR);
605 }
606
607 /* Android CTS tests require this. */
608 virgl_add_combination(drv, DRM_FORMAT_RGB888, &LINEAR_METADATA, BO_USE_SW_MASK);
609 virgl_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
610 virgl_add_combination(drv, DRM_FORMAT_ABGR16161616F, &LINEAR_METADATA,
611 BO_USE_SW_MASK | BO_USE_TEXTURE_MASK);
612 virgl_add_combination(drv, DRM_FORMAT_ABGR2101010, &LINEAR_METADATA,
613 BO_USE_SW_MASK | BO_USE_TEXTURE_MASK);
614 virgl_add_combination(drv, DRM_FORMAT_P010, &LINEAR_METADATA,
615 BO_USE_SW_MASK | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
616
617 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
618 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
619 BO_USE_HW_VIDEO_ENCODER);
620 drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
621 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
622 BO_USE_HW_VIDEO_ENCODER);
623
624 if (!priv->host_gbm_enabled) {
625 drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &LINEAR_METADATA,
626 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
627 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
628 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &LINEAR_METADATA,
629 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
630 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
631 drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
632 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
633 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
634 drv_modify_combination(drv, DRM_FORMAT_R16, &LINEAR_METADATA,
635 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
636 BO_USE_HW_VIDEO_DECODER);
637 drv_modify_combination(drv, DRM_FORMAT_YVU420, &LINEAR_METADATA,
638 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
639 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
640 drv_modify_combination(drv, DRM_FORMAT_YVU420_ANDROID, &LINEAR_METADATA,
641 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE |
642 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
643 }
644
645 return drv_modify_linear_combinations(drv);
646 }
647
virgl_close(struct driver * drv)648 static void virgl_close(struct driver *drv)
649 {
650 free(drv->priv);
651 drv->priv = NULL;
652 }
653
virgl_bo_create_blob(struct driver * drv,struct bo * bo)654 static int virgl_bo_create_blob(struct driver *drv, struct bo *bo)
655 {
656 int ret;
657 uint32_t stride;
658 uint32_t cur_blob_id;
659 uint32_t cmd[VIRGL_PIPE_RES_CREATE_SIZE + 1] = { 0 };
660 struct drm_virtgpu_resource_create_blob drm_rc_blob = { 0 };
661 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
662
663 uint32_t blob_flags = VIRTGPU_BLOB_FLAG_USE_SHAREABLE;
664 if (bo->meta.use_flags & BO_USE_SW_MASK)
665 blob_flags |= VIRTGPU_BLOB_FLAG_USE_MAPPABLE;
666 if (bo->meta.use_flags & BO_USE_NON_GPU_HW)
667 blob_flags |= VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE;
668
669 cur_blob_id = atomic_fetch_add(&priv->next_blob_id, 1);
670 stride = drv_stride_from_format(bo->meta.format, bo->meta.width, 0);
671 drv_bo_from_format(bo, stride, bo->meta.height, bo->meta.format);
672 bo->meta.total_size = ALIGN(bo->meta.total_size, PAGE_SIZE);
673 bo->meta.tiling = blob_flags;
674
675 cmd[0] = VIRGL_CMD0(VIRGL_CCMD_PIPE_RESOURCE_CREATE, 0, VIRGL_PIPE_RES_CREATE_SIZE);
676 cmd[VIRGL_PIPE_RES_CREATE_TARGET] = PIPE_TEXTURE_2D;
677 cmd[VIRGL_PIPE_RES_CREATE_WIDTH] = bo->meta.width;
678 cmd[VIRGL_PIPE_RES_CREATE_HEIGHT] = bo->meta.height;
679 cmd[VIRGL_PIPE_RES_CREATE_FORMAT] = translate_format(bo->meta.format);
680 cmd[VIRGL_PIPE_RES_CREATE_BIND] =
681 compute_virgl_bind_flags(bo->meta.use_flags, bo->meta.format);
682 cmd[VIRGL_PIPE_RES_CREATE_DEPTH] = 1;
683 cmd[VIRGL_PIPE_RES_CREATE_BLOB_ID] = cur_blob_id;
684
685 drm_rc_blob.cmd = (uint64_t)&cmd;
686 drm_rc_blob.cmd_size = 4 * (VIRGL_PIPE_RES_CREATE_SIZE + 1);
687 drm_rc_blob.size = bo->meta.total_size;
688 drm_rc_blob.blob_mem = VIRTGPU_BLOB_MEM_HOST3D;
689 drm_rc_blob.blob_flags = blob_flags;
690 drm_rc_blob.blob_id = cur_blob_id;
691
692 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB, &drm_rc_blob);
693 if (ret < 0) {
694 drv_log("DRM_VIRTGPU_RESOURCE_CREATE_BLOB failed with %s\n", strerror(errno));
695 return -errno;
696 }
697
698 for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++)
699 bo->handles[plane].u32 = drm_rc_blob.bo_handle;
700
701 return 0;
702 }
703
should_use_blob(struct driver * drv,uint32_t format,uint64_t use_flags)704 static bool should_use_blob(struct driver *drv, uint32_t format, uint64_t use_flags)
705 {
706 struct virgl_priv *priv = (struct virgl_priv *)drv->priv;
707
708 // TODO(gurchetansingh): remove once all minigbm users are blob-safe
709 #ifndef VIRTIO_GPU_NEXT
710 return false;
711 #endif
712
713 // Only use blob when host gbm is available
714 if (!priv->host_gbm_enabled)
715 return false;
716
717 // Use regular resources if only the GPU needs efficient access
718 if (!(use_flags &
719 (BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_LINEAR | BO_USE_NON_GPU_HW)))
720 return false;
721
722 switch (format) {
723 case DRM_FORMAT_YVU420_ANDROID:
724 case DRM_FORMAT_R8:
725 // Formats with strictly defined strides are supported
726 return true;
727 case DRM_FORMAT_NV12:
728 // Knowing buffer metadata at buffer creation isn't yet supported, so buffers
729 // can't be properly mapped into the guest.
730 return (use_flags & BO_USE_SW_MASK) == 0;
731 default:
732 return false;
733 }
734 }
735
virgl_bo_create(struct bo * bo,uint32_t width,uint32_t height,uint32_t format,uint64_t use_flags)736 static int virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
737 uint64_t use_flags)
738 {
739 if (params[param_resource_blob].value && params[param_host_visible].value &&
740 should_use_blob(bo->drv, format, use_flags))
741 return virgl_bo_create_blob(bo->drv, bo);
742
743 if (params[param_3d].value)
744 return virgl_3d_bo_create(bo, width, height, format, use_flags);
745 else
746 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
747 }
748
virgl_bo_destroy(struct bo * bo)749 static int virgl_bo_destroy(struct bo *bo)
750 {
751 if (params[param_3d].value)
752 return drv_gem_bo_destroy(bo);
753 else
754 return drv_dumb_bo_destroy(bo);
755 }
756
virgl_bo_map(struct bo * bo,struct vma * vma,size_t plane,uint32_t map_flags)757 static void *virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
758 {
759 if (params[param_3d].value)
760 return virgl_3d_bo_map(bo, vma, plane, map_flags);
761 else
762 return drv_dumb_bo_map(bo, vma, plane, map_flags);
763 }
764
virgl_bo_invalidate(struct bo * bo,struct mapping * mapping)765 static int virgl_bo_invalidate(struct bo *bo, struct mapping *mapping)
766 {
767 int ret;
768 size_t i;
769 struct drm_virtgpu_3d_transfer_from_host xfer = { 0 };
770 struct drm_virtgpu_3d_wait waitcmd = { 0 };
771 struct virtio_transfers_params xfer_params;
772 struct virgl_priv *priv = (struct virgl_priv *)bo->drv->priv;
773 uint64_t host_write_flags;
774
775 if (!params[param_3d].value)
776 return 0;
777
778 // Invalidate is only necessary if the host writes to the buffer. The encoder and
779 // decoder flags don't differentiate between input and output buffers, but we can
780 // use the format to determine whether this buffer could be encoder/decoder output.
781 host_write_flags = BO_USE_RENDERING | BO_USE_CAMERA_WRITE;
782 if (bo->meta.format == DRM_FORMAT_R8)
783 host_write_flags |= BO_USE_HW_VIDEO_ENCODER;
784 else
785 host_write_flags |= BO_USE_HW_VIDEO_DECODER;
786
787 if ((bo->meta.use_flags & host_write_flags) == 0)
788 return 0;
789
790 if (params[param_resource_blob].value && (bo->meta.tiling & VIRTGPU_BLOB_FLAG_USE_MAPPABLE))
791 return 0;
792
793 xfer.bo_handle = mapping->vma->handle;
794
795 if (mapping->rect.x || mapping->rect.y) {
796 /*
797 * virglrenderer uses the box parameters and assumes that offset == 0 for planar
798 * images
799 */
800 if (bo->meta.num_planes == 1) {
801 xfer.offset =
802 (bo->meta.strides[0] * mapping->rect.y) +
803 drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
804 }
805 }
806
807 if ((bo->meta.use_flags & BO_USE_RENDERING) == 0) {
808 // Unfortunately, the kernel doesn't actually pass the guest layer_stride
809 // and guest stride to the host (compare virgl.h and virtgpu_drm.h).
810 // For gbm based resources, we can work around this by using the level field
811 // to pass the stride to virglrenderer's gbm transfer code. However, we need
812 // to avoid doing this for resources which don't rely on that transfer code,
813 // which is resources with the BO_USE_RENDERING flag set.
814 // TODO(b/145993887): Send also stride when the patches are landed
815 if (priv->host_gbm_enabled)
816 xfer.level = bo->meta.strides[0];
817 }
818
819 if (virgl_supports_combination_natively(bo->drv, bo->meta.format, bo->meta.use_flags)) {
820 xfer_params.xfers_needed = 1;
821 xfer_params.xfer_boxes[0] = mapping->rect;
822 } else {
823 assert(virgl_supports_combination_through_emulation(bo->drv, bo->meta.format,
824 bo->meta.use_flags));
825
826 virgl_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
827 }
828
829 for (i = 0; i < xfer_params.xfers_needed; i++) {
830 xfer.box.x = xfer_params.xfer_boxes[i].x;
831 xfer.box.y = xfer_params.xfer_boxes[i].y;
832 xfer.box.w = xfer_params.xfer_boxes[i].width;
833 xfer.box.h = xfer_params.xfer_boxes[i].height;
834 xfer.box.d = 1;
835
836 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
837 if (ret) {
838 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n",
839 strerror(errno));
840 return -errno;
841 }
842 }
843
844 // The transfer needs to complete before invalidate returns so that any host changes
845 // are visible and to ensure the host doesn't overwrite subsequent guest changes.
846 // TODO(b/136733358): Support returning fences from transfers
847 waitcmd.handle = mapping->vma->handle;
848 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
849 if (ret) {
850 drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
851 return -errno;
852 }
853
854 return 0;
855 }
856
virgl_bo_flush(struct bo * bo,struct mapping * mapping)857 static int virgl_bo_flush(struct bo *bo, struct mapping *mapping)
858 {
859 int ret;
860 size_t i;
861 struct drm_virtgpu_3d_transfer_to_host xfer = { 0 };
862 struct drm_virtgpu_3d_wait waitcmd = { 0 };
863 struct virtio_transfers_params xfer_params;
864 struct virgl_priv *priv = (struct virgl_priv *)bo->drv->priv;
865
866 if (!params[param_3d].value)
867 return 0;
868
869 if (!(mapping->vma->map_flags & BO_MAP_WRITE))
870 return 0;
871
872 if (params[param_resource_blob].value && (bo->meta.tiling & VIRTGPU_BLOB_FLAG_USE_MAPPABLE))
873 return 0;
874
875 xfer.bo_handle = mapping->vma->handle;
876
877 if (mapping->rect.x || mapping->rect.y) {
878 /*
879 * virglrenderer uses the box parameters and assumes that offset == 0 for planar
880 * images
881 */
882 if (bo->meta.num_planes == 1) {
883 xfer.offset =
884 (bo->meta.strides[0] * mapping->rect.y) +
885 drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
886 }
887 }
888
889 // Unfortunately, the kernel doesn't actually pass the guest layer_stride and
890 // guest stride to the host (compare virgl.h and virtgpu_drm.h). We can use
891 // the level to work around this.
892 if (priv->host_gbm_enabled)
893 xfer.level = bo->meta.strides[0];
894
895 if (virgl_supports_combination_natively(bo->drv, bo->meta.format, bo->meta.use_flags)) {
896 xfer_params.xfers_needed = 1;
897 xfer_params.xfer_boxes[0] = mapping->rect;
898 } else {
899 assert(virgl_supports_combination_through_emulation(bo->drv, bo->meta.format,
900 bo->meta.use_flags));
901
902 virgl_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
903 }
904
905 for (i = 0; i < xfer_params.xfers_needed; i++) {
906 xfer.box.x = xfer_params.xfer_boxes[i].x;
907 xfer.box.y = xfer_params.xfer_boxes[i].y;
908 xfer.box.w = xfer_params.xfer_boxes[i].width;
909 xfer.box.h = xfer_params.xfer_boxes[i].height;
910 xfer.box.d = 1;
911
912 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
913 if (ret) {
914 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n",
915 strerror(errno));
916 return -errno;
917 }
918 }
919
920 // If the buffer is only accessed by the host GPU, then the flush is ordered
921 // with subsequent commands. However, if other host hardware can access the
922 // buffer, we need to wait for the transfer to complete for consistency.
923 // TODO(b/136733358): Support returning fences from transfers
924 if (bo->meta.use_flags & BO_USE_NON_GPU_HW) {
925 waitcmd.handle = mapping->vma->handle;
926
927 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
928 if (ret) {
929 drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
930 return -errno;
931 }
932 }
933
934 return 0;
935 }
936
virgl_resolve_format(struct driver * drv,uint32_t format,uint64_t use_flags)937 static uint32_t virgl_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
938 {
939 switch (format) {
940 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
941 /* Camera subsystem requires NV12. */
942 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
943 return DRM_FORMAT_NV12;
944 /*HACK: See b/28671744 */
945 return DRM_FORMAT_XBGR8888;
946 case DRM_FORMAT_FLEX_YCbCr_420_888:
947 /*
948 * All of our host drivers prefer NV12 as their flexible media format.
949 * If that changes, this will need to be modified.
950 */
951 if (params[param_3d].value)
952 return DRM_FORMAT_NV12;
953 else
954 return DRM_FORMAT_YVU420_ANDROID;
955 default:
956 return format;
957 }
958 }
virgl_resource_info(struct bo * bo,uint32_t strides[DRV_MAX_PLANES],uint32_t offsets[DRV_MAX_PLANES],uint64_t * format_modifier)959 static int virgl_resource_info(struct bo *bo, uint32_t strides[DRV_MAX_PLANES],
960 uint32_t offsets[DRV_MAX_PLANES], uint64_t *format_modifier)
961 {
962 int ret;
963 struct drm_virtgpu_resource_info_cros res_info = { 0 };
964
965 if (!params[param_3d].value)
966 return 0;
967
968 res_info.bo_handle = bo->handles[0].u32;
969 res_info.type = VIRTGPU_RESOURCE_INFO_TYPE_EXTENDED;
970 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_INFO_CROS, &res_info);
971 if (ret) {
972 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_INFO failed with %s\n", strerror(errno));
973 return ret;
974 }
975
976 for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++) {
977 /*
978 * Currently, kernel v4.14 (Betty) doesn't have the extended resource info
979 * ioctl.
980 */
981 if (res_info.strides[plane]) {
982 strides[plane] = res_info.strides[plane];
983 offsets[plane] = res_info.offsets[plane];
984 }
985 }
986 *format_modifier = res_info.format_modifier;
987
988 return 0;
989 }
990
991 const struct backend virtgpu_virgl = { .name = "virtgpu_virgl",
992 .init = virgl_init,
993 .close = virgl_close,
994 .bo_create = virgl_bo_create,
995 .bo_destroy = virgl_bo_destroy,
996 .bo_import = drv_prime_bo_import,
997 .bo_map = virgl_bo_map,
998 .bo_unmap = drv_bo_munmap,
999 .bo_invalidate = virgl_bo_invalidate,
1000 .bo_flush = virgl_bo_flush,
1001 .resolve_format = virgl_resolve_format,
1002 .resource_info = virgl_resource_info };
1003