cpu-specific-build-macros.rst - OpenGrok cross reference for /external/arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst

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1 Arm CPU Specific Build Macros
4 This document describes the various build options present in the CPU specific
6 for a specific CPU on a platform.
29    platform contains at least 1 CPU that requires dynamic mitigation.
34 CPU Errata Workarounds
38 are applied to each CPU by the reset handler. The errata details can be found
39 in the CPU specific errata documents published by Arm:
50 is for example ``A57`` for the ``Cortex_A57`` CPU.
58 these workarounds are enabled for the wrong CPU revision then the errata
72    CPU. This needs to be enabled for all revisions of the CPU.
77    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
80    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
85    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
88    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
104    CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
110    link time to Cortex-A53 CPU. This needs to be enabled for some variants of
115    CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
119    to Cortex-A53 CPU.  This needs to be enabled for some variants of revision
124    CPUs. Though the erratum is present in every revision of the CPU,
127    Earlier revisions of the CPU have other errata which require the same
131    revisions of Cortex-A53 CPU.
136    CPU. This needs to be enabled only for revision r0p0 of the CPU.
139    CPU. This needs to be enabled only for revision r0p0 of the CPU.
142    CPU. This needs to be enabled only for revision r0p0 of the CPU.
145    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
148    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
151    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
154    revisions of Cortex-A55 CPU.
159    CPU. This needs to be enabled only for revision r0p0 of the CPU.
162    CPU. This needs to be enabled only for revision r0p0 of the CPU.
165    CPU. This needs to be enabled only for revision r0p0 of the CPU.
168    CPU. This needs to be enabled only for revision r0p0 of the CPU.
171    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
174    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
177    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
180    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
183    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
186    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
189    CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
192    revisions of Cortex-A57 CPU.
197    CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
200    revisions of Cortex-A72 CPU.
205    CPU. This needs to be enabled only for revision r0p0 of the CPU.
208    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
213    CPU. This needs to be enabled only for revision r0p0 of the CPU.
216     CPU. This needs to be enabled only for revision r0p0 of the CPU.
221    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
224    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
227    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
230    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
233    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
236    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
239    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
242    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
245    revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
247    of Cortex-A76 CPU.
250    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
253    CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
258    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
261    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
264    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
267    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
272    CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
275    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
278    CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
282    CPU. This needs to be enabled for revisions r0p0 and r1p0.
285    CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
290    AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
294   AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
300    CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
303    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
306    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
309    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
312    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
315    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
318    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
321    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
324    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
327    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
330    CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
333    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
336    CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
342    CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
347    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
351    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
355    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
359    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
362    CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
363    CPU.
366    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
371    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
372    CPU.  It is still open.
377    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
378    r2p0 of the CPU. It is still open.
381    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
382    r2p0 of the CPU. It is still open.
385    Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
389    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
390    of the CPU and is still open.
395    CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
398    CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
401    CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
404    CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
409 Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
418 of DSU errata workarounds are similar to `CPU errata workarounds`_.
433 CPU Specific optimizations
436 This section describes some of the optimizations allowed by the CPU micro
454    <= r0p3 of the CPU and is enabled by default.
458    enabled only for revisions <= r1p2 of the CPU and is enabled by default,