Lines Matching +full:multi +full:- +full:cores

4 -  .. rubric:: T194
7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
9 executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
10 processors are organized as four dual-core clusters, where each cluster has
11 a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
12 these processor complexes and allows heterogeneous multi-processing with all
13 eight cores if required.
15 -  .. rubric:: T186
18 The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
19 multi-processing (HMP) solution designed to optimize performance and
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
24 support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
30 heterogeneous multi-processing with all six cores if required.
32 Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
33 fully Armv8-A architecture compatible. Each of the two Denver cores
34 implements a 7-way superscalar microarchitecture (up to 7 concurrent
35 micro-ops can be executed per clock), and includes a 128KB 4-way L1
36 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
37 cache, which services both cores.
41 highly tuned microcode-equivalent routines. These are stored in a
42 dedicated, 128MB main-memory-based optimization cache. After being read
43 into the instruction cache, the optimized micro-ops are executed,
44 re-fetched and executed from the instruction cache as long as needed and
47 Effectively, this reduces the need to re-optimize the software routines.
48 Instead of using hardware to extract the instruction-level parallelism
53 Denver also features new low latency power-state transitions, in addition
54 to extensive power-gating and dynamic voltage and clock scaling based on
57 -  .. rubric:: T210
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
62 support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
69 -------------------
71 -  plat/nvidia/tegra/common - Common code for all Tegra SoCs
72 -  plat/nvidia/tegra/soc/txxx - Chip specific code
75 ---------------------
79 - Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in
81 - Trusty: In order to include the 'trusty' dispatcher in the image, pass
89 - Tegra210: TLK and Trusty
90 - Tegra186: Trusty
91 - Tegra194: Trusty
94 -------------
104 ---------------------------------------------
108     CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
109     TARGET_SOC=<target-soc e.g. t194|t186|t210> SPD=<dispatcher e.g. trusty|tlkd>
136 ----------------
139 parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field
144 -------------
146 -  'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
147    Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will