Lines Matching full:priv
289 static uintptr_t get_base_addr(const struct ddr_info *priv, enum base_type base) in get_base_addr() argument
292 return (uintptr_t)priv->phy; in get_base_addr()
294 return (uintptr_t)priv->ctl; in get_base_addr()
298 static void set_reg(const struct ddr_info *priv, in set_reg() argument
305 uintptr_t base_addr = get_base_addr(priv, base); in set_reg()
417 static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode) in stm32mp1_wait_operating_mode() argument
428 stat = mmio_read_32((uintptr_t)&priv->ctl->stat); in stm32mp1_wait_operating_mode()
432 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
462 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
466 static void stm32mp1_mode_register_write(struct ddr_info *priv, uint8_t addr, in stm32mp1_mode_register_write() argument
479 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
492 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
494 (uintptr_t)&priv->ctl->mrctrl0, in stm32mp1_mode_register_write()
495 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0); in stm32mp1_mode_register_write()
496 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data); in stm32mp1_mode_register_write()
498 (uintptr_t)&priv->ctl->mrctrl1, in stm32mp1_mode_register_write()
499 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1)); in stm32mp1_mode_register_write()
509 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
511 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
517 (uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
521 static void stm32mp1_ddr3_dll_off(struct ddr_info *priv) in stm32mp1_ddr3_dll_off() argument
523 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1); in stm32mp1_ddr3_dll_off()
524 uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2); in stm32mp1_ddr3_dll_off()
534 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
536 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
537 mmio_read_32((uintptr_t)&priv->ctl->dbg1)); in stm32mp1_ddr3_dll_off()
548 dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam); in stm32mp1_ddr3_dll_off()
550 (uintptr_t)&priv->ctl->dbgcam, dbgcam); in stm32mp1_ddr3_dll_off()
562 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
577 stm32mp1_mode_register_write(priv, 2, mr2); in stm32mp1_ddr3_dll_off()
587 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
594 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
597 (uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
598 mmio_read_32((uintptr_t)&priv->ctl->pwrctl)); in stm32mp1_ddr3_dll_off()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
612 stm32mp1_start_sw_done(priv->ctl); in stm32mp1_ddr3_dll_off()
614 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); in stm32mp1_ddr3_dll_off()
616 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr3_dll_off()
617 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr3_dll_off()
619 stm32mp1_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr3_dll_off()
631 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
634 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
638 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS); in stm32mp1_ddr3_dll_off()
640 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
642 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
644 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
646 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, in stm32mp1_ddr3_dll_off()
650 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
652 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr3_dll_off()
666 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
668 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
669 mmio_read_32((uintptr_t)&priv->ctl->dbg1)); in stm32mp1_ddr3_dll_off()
710 void stm32mp1_ddr_init(struct ddr_info *priv, in stm32mp1_ddr_init() argument
742 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
743 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
744 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
745 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
746 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
747 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
750 if (stm32mp1_ddr_clk_enable(priv, config->info.speed) != 0) { in stm32mp1_ddr_init()
756 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
757 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
762 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
770 mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
773 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
774 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
776 set_reg(priv, REG_REG, &config->c_reg); in stm32mp1_ddr_init()
783 mmio_clrbits_32((uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
786 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
787 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr_init()
790 set_reg(priv, REG_TIMING, &config->c_timing); in stm32mp1_ddr_init()
791 set_reg(priv, REG_MAP, &config->c_map); in stm32mp1_ddr_init()
794 mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
798 (uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
799 mmio_read_32((uintptr_t)&priv->ctl->init0)); in stm32mp1_ddr_init()
801 set_reg(priv, REG_PERF, &config->c_perf); in stm32mp1_ddr_init()
804 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
805 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
806 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
812 set_reg(priv, REGPHY_REG, &config->p_reg); in stm32mp1_ddr_init()
813 set_reg(priv, REGPHY_TIMING, &config->p_timing); in stm32mp1_ddr_init()
814 set_reg(priv, REGPHY_CAL, &config->p_cal); in stm32mp1_ddr_init()
821 mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0)); in stm32mp1_ddr_init()
823 (uintptr_t)&priv->phy->mr1, in stm32mp1_ddr_init()
824 mmio_read_32((uintptr_t)&priv->phy->mr1)); in stm32mp1_ddr_init()
831 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
846 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
852 stm32mp1_start_sw_done(priv->ctl); in stm32mp1_ddr_init()
854 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
857 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
858 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
860 stm32mp1_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr_init()
868 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr_init()
872 stm32mp1_ddr3_dll_off(priv); in stm32mp1_ddr_init()
883 stm32mp1_refresh_disable(priv->ctl); in stm32mp1_ddr_init()
896 stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); in stm32mp1_ddr_init()
899 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
904 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, in stm32mp1_ddr_init()
908 mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_0, in stm32mp1_ddr_init()
911 (uintptr_t)&priv->ctl->pctrl_0, in stm32mp1_ddr_init()
912 mmio_read_32((uintptr_t)&priv->ctl->pctrl_0)); in stm32mp1_ddr_init()
915 mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_1, in stm32mp1_ddr_init()
918 (uintptr_t)&priv->ctl->pctrl_1, in stm32mp1_ddr_init()
919 mmio_read_32((uintptr_t)&priv->ctl->pctrl_1)); in stm32mp1_ddr_init()