460                                         unsigned PredReg) {  in UpdateBaseRegUses()
596     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()
793     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()
860   unsigned PredReg = 0;  in MergeOpsUpdate()  local
1127                                   ARMCC::CondCodes Pred, unsigned PredReg) {  in isIncrementOrDecrement()
1157                  ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {  in findIncDecBefore()
1177                 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {  in findIncDecAfter()
1211   unsigned PredReg = 0;  in MergeBaseUpdateLSMultiple()  local
1353   unsigned PredReg = 0;  in MergeBaseUpdateLoadStore()  local
1450   unsigned PredReg;  in MergeBaseUpdateLSDouble()  local
1555                           unsigned PredReg, const TargetInstrInfo *TII,  in InsertLDR_STR()
1610   unsigned PredReg = 0;  in FixInvalidRegPairOp()  local
1716       unsigned PredReg = 0;  in LoadStoreMultipleOpti()  local
2060                                           unsigned &PredReg,  in CanFormLdStDWord()
2218         unsigned BaseReg = 0, PredReg = 0;  in RescheduleOps()  local
2317       unsigned PredReg = 0;  in RescheduleLoadStoreInstrs()  local