Lines Matching full:decoder
74 const void *Decoder);
79 const void *Decoder);
84 const void *Decoder);
89 const void *Decoder);
94 const void *Decoder);
99 const void *Decoder);
104 const void *Decoder);
109 const void *Decoder);
114 const void *Decoder);
119 const void *Decoder);
124 const void *Decoder);
129 const void *Decoder);
133 const void *Decoder);
138 const void *Decoder);
143 const void *Decoder);
148 const void *Decoder);
153 const void *Decoder);
158 const void *Decoder);
163 const void *Decoder);
168 const void *Decoder);
173 const void *Decoder);
178 const void *Decoder);
183 const void *Decoder);
188 const void *Decoder);
193 const void *Decoder);
198 const void *Decoder);
203 const void *Decoder);
208 const void *Decoder);
213 const void *Decoder);
218 const void *Decoder);
223 const void *Decoder);
230 const void *Decoder);
237 const void *Decoder);
244 const void *Decoder);
251 const void *Decoder);
258 const void *Decoder);
263 const void *Decoder);
268 const void *Decoder);
273 const void *Decoder);
278 const void *Decoder);
283 const void *Decoder);
288 const void *Decoder);
293 const void *Decoder);
298 const void *Decoder);
303 const void *Decoder);
308 const void *Decoder);
313 const void *Decoder);
316 uint64_t Address, const void *Decoder);
321 const void *Decoder);
326 const void *Decoder);
331 const void *Decoder);
336 const void *Decoder);
341 const void *Decoder);
346 const void *Decoder);
351 const void *Decoder);
355 const void *Decoder);
359 const void *Decoder);
363 const void *Decoder);
367 const void *Decoder);
371 const void *Decoder);
375 const void *Decoder);
380 const void *Decoder);
385 const void *Decoder);
390 const void *Decoder);
395 const void *Decoder);
400 const void *Decoder);
405 const void *Decoder) { in DecodeUImmWithOffset() argument
407 Decoder); in DecodeUImmWithOffset()
413 const void *Decoder);
418 const void *Decoder);
421 uint64_t Address, const void *Decoder);
424 uint64_t Address, const void *Decoder);
427 uint64_t Address, const void *Decoder);
430 uint64_t Address, const void *Decoder);
433 uint64_t Address, const void *Decoder);
435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
439 const void *Decoder);
444 const void *Decoder);
449 const void *Decoder);
454 const void *Decoder);
459 const void *Decoder);
464 const void *Decoder);
469 const void *Decoder);
474 const void *Decoder);
479 const void *Decoder);
484 const void *Decoder);
489 const void *Decoder);
493 const void *Decoder);
497 const void *Decoder);
501 const void *Decoder);
544 const void *Decoder) { in DecodeINSVE_DF() argument
570 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
573 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
580 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
591 const void *Decoder) { in DecodeAddiGroupBranch() argument
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
630 const void *Decoder) { in DecodePOP35GroupBranchMMR6() argument
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
661 const void *Decoder) { in DecodeDaddiGroupBranch() argument
687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
700 const void *Decoder) { in DecodePOP37GroupBranchMMR6() argument
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
731 const void *Decoder) { in DecodeBlezlGroupBranch() argument
760 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
763 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
774 const void *Decoder) { in DecodeBgtzlGroupBranch() argument
804 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
807 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
818 const void *Decoder) { in DecodeBgtzGroupBranch() argument
852 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
856 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
867 const void *Decoder) { in DecodeBlezGroupBranch() argument
896 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
898 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
977 // Calling the auto-generated decoder function for microMIPS32R6 in getInstruction()
988 // Calling the auto-generated decoder function for microMIPS 16-bit in getInstruction()
1003 // Calling the auto-generated decoder function. in getInstruction()
1013 // Calling the auto-generated decoder function. in getInstruction()
1114 // Calling the auto-generated decoder function. in getInstruction()
1129 const void *Decoder) { in DecodeCPU16RegsRegisterClass() argument
1138 const void *Decoder) { in DecodeGPR64RegisterClass() argument
1143 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
1151 const void *Decoder) { in DecodeGPRMM16RegisterClass() argument
1154 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass()
1162 const void *Decoder) { in DecodeGPRMM16ZeroRegisterClass() argument
1165 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass()
1173 const void *Decoder) { in DecodeGPRMM16MovePRegisterClass() argument
1176 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass()
1184 const void *Decoder) { in DecodeGPR32RegisterClass() argument
1187 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
1195 const void *Decoder) { in DecodePtrRegisterClass() argument
1196 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) in DecodePtrRegisterClass()
1197 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1199 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1205 const void *Decoder) { in DecodeDSPRRegisterClass() argument
1206 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodeDSPRRegisterClass()
1212 const void *Decoder) { in DecodeFGR64RegisterClass() argument
1216 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
1224 const void *Decoder) { in DecodeFGR32RegisterClass() argument
1228 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass()
1236 const void *Decoder) { in DecodeCCRRegisterClass() argument
1239 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass()
1247 const void *Decoder) { in DecodeFCCRegisterClass() argument
1250 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass()
1257 const void *Decoder) { in DecodeFGRCCRegisterClass() argument
1261 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass()
1269 const void *Decoder) { in DecodeMem() argument
1274 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
1275 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMem()
1291 const void *Decoder) { in DecodeMemEVA() argument
1296 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemEVA()
1297 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemEVA()
1312 const void *Decoder) { in DecodeLoadByte9() argument
1317 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeLoadByte9()
1318 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte9()
1330 const void *Decoder) { in DecodeLoadByte15() argument
1335 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeLoadByte15()
1336 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte15()
1348 const void *Decoder) { in DecodeCacheOp() argument
1353 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOp()
1365 const void *Decoder) { in DecodeCacheOpMM() argument
1370 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOpMM()
1382 const void *Decoder) { in DecodePrefeOpMM() argument
1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodePrefeOpMM()
1399 const void *Decoder) { in DecodeCacheeOp_CacheOpR6() argument
1404 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheeOp_CacheOpR6()
1416 const void *Decoder) { in DecodeStoreEvaOpMM() argument
1421 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeStoreEvaOpMM()
1422 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeStoreEvaOpMM()
1434 const void *Decoder) { in DecodeSyncI() argument
1438 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI()
1449 const void *Decoder) { in DecodeSynciR6() argument
1453 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSynciR6()
1462 uint64_t Address, const void *Decoder) { in DecodeMSA128Mem() argument
1467 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); in DecodeMSA128Mem()
1468 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMSA128Mem()
1510 const void *Decoder) { in DecodeMemMMImm4() argument
1519 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1529 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1535 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) in DecodeMemMMImm4()
1568 const void *Decoder) { in DecodeMemMMSPImm5Lsl2() argument
1572 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMSPImm5Lsl2()
1584 const void *Decoder) { in DecodeMemMMGPImm7Lsl2() argument
1588 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMGPImm7Lsl2()
1600 const void *Decoder) { in DecodeMemMMReglistImm4Lsl2() argument
1612 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) in DecodeMemMMReglistImm4Lsl2()
1625 const void *Decoder) { in DecodeMemMMImm9() argument
1630 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm9()
1631 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm9()
1646 const void *Decoder) { in DecodeMemMMImm12() argument
1651 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm12()
1652 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm12()
1657 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) in DecodeMemMMImm12()
1682 const void *Decoder) { in DecodeMemMMImm16() argument
1687 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm16()
1688 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm16()
1700 const void *Decoder) { in DecodeFMem() argument
1705 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMem()
1706 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem()
1716 uint64_t Address, const void *Decoder) { in DecodeFMemMMR2() argument
1723 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMemMMR2()
1724 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemMMR2()
1736 const void *Decoder) { in DecodeFMem2() argument
1741 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMem2()
1742 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem2()
1754 const void *Decoder) { in DecodeFMem3() argument
1759 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); in DecodeFMem3()
1760 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem3()
1772 const void *Decoder) { in DecodeFMemCop2R6() argument
1777 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2R6()
1778 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2R6()
1788 uint64_t Address, const void *Decoder) { in DecodeFMemCop2MMR6() argument
1793 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2MMR6()
1794 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2MMR6()
1806 const void *Decoder) { in DecodeSpecial3LlSc() argument
1811 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); in DecodeSpecial3LlSc()
1812 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSpecial3LlSc()
1828 const void *Decoder) { in DecodeHWRegsRegisterClass() argument
1839 const void *Decoder) { in DecodeAFGR64RegisterClass() argument
1844 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); in DecodeAFGR64RegisterClass()
1852 const void *Decoder) { in DecodeACC64DSPRegisterClass() argument
1856 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); in DecodeACC64DSPRegisterClass()
1864 const void *Decoder) { in DecodeHI32DSPRegisterClass() argument
1868 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); in DecodeHI32DSPRegisterClass()
1876 const void *Decoder) { in DecodeLO32DSPRegisterClass() argument
1880 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); in DecodeLO32DSPRegisterClass()
1888 const void *Decoder) { in DecodeMSA128BRegisterClass() argument
1892 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); in DecodeMSA128BRegisterClass()
1900 const void *Decoder) { in DecodeMSA128HRegisterClass() argument
1904 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); in DecodeMSA128HRegisterClass()
1912 const void *Decoder) { in DecodeMSA128WRegisterClass() argument
1916 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); in DecodeMSA128WRegisterClass()
1924 const void *Decoder) { in DecodeMSA128DRegisterClass() argument
1928 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); in DecodeMSA128DRegisterClass()
1936 const void *Decoder) { in DecodeMSACtrlRegisterClass() argument
1940 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); in DecodeMSACtrlRegisterClass()
1948 const void *Decoder) { in DecodeCOP0RegisterClass() argument
1952 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); in DecodeCOP0RegisterClass()
1960 const void *Decoder) { in DecodeCOP2RegisterClass() argument
1964 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); in DecodeCOP2RegisterClass()
1972 const void *Decoder) { in DecodeBranchTarget() argument
1981 const void *Decoder) { in DecodeBranchTarget1SImm16() argument
1990 const void *Decoder) { in DecodeJumpTarget() argument
2000 const void *Decoder) { in DecodeBranchTarget21() argument
2010 const void *Decoder) { in DecodeBranchTarget21MM() argument
2020 const void *Decoder) { in DecodeBranchTarget26() argument
2030 const void *Decoder) { in DecodeBranchTarget7MM() argument
2039 const void *Decoder) { in DecodeBranchTarget10MM() argument
2048 const void *Decoder) { in DecodeBranchTargetMM() argument
2057 const void *Decoder) { in DecodeBranchTarget26MM() argument
2067 const void *Decoder) { in DecodeJumpTargetMM() argument
2076 const void *Decoder) { in DecodeAddiur2Simm7() argument
2089 const void *Decoder) { in DecodeLi16Imm() argument
2100 const void *Decoder) { in DecodePOOL16BEncodedField() argument
2108 const void *Decoder) { in DecodeUImmWithOffsetAndScale() argument
2118 const void *Decoder) { in DecodeSImmWithOffsetAndScale() argument
2127 const void *Decoder) { in DecodeInsSize() argument
2136 uint64_t Address, const void *Decoder) { in DecodeSimm19Lsl2() argument
2142 uint64_t Address, const void *Decoder) { in DecodeSimm18Lsl3() argument
2148 uint64_t Address, const void *Decoder) { in DecodeSimm9SP() argument
2162 uint64_t Address, const void *Decoder) { in DecodeANDI16Imm() argument
2174 const void *Decoder) { in DecodeRegListOperand() argument
2202 const void *Decoder) { in DecodeRegListOperand16() argument
2225 uint64_t Address, const void *Decoder) { in DecodeMovePRegPair() argument
2270 uint64_t Address, const void *Decoder) { in DecodeSimm23Lsl2() argument
2278 const void *Decoder) { in DecodeBgtzGroupBranchMMR6() argument
2310 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBgtzGroupBranchMMR6()
2314 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBgtzGroupBranchMMR6()
2324 const void *Decoder) { in DecodeBlezGroupBranchMMR6() argument
2350 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBlezGroupBranchMMR6()
2352 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBlezGroupBranchMMR6()