Lines Matching +full:- +full:encoding
21 asm_context(Program* program) : program(program), chip_class(program->chip_class) { in asm_context()
30 int subvector_begin_pos = -1;
47 /* lower remaining pseudo-instructions */ in emit_instruction()
48 if (instr->opcode == aco_opcode::p_constaddr) { in emit_instruction()
49 unsigned dest = instr->definitions[0].physReg(); in emit_instruction()
50 unsigned offset = instr->operands[0].constantValue(); in emit_instruction()
53 uint32_t encoding = (0b101111101 << 23); in emit_instruction() local
57 opcode = opcode - 4; in emit_instruction()
59 encoding |= dest << 16; in emit_instruction()
60 encoding |= opcode << 8; in emit_instruction()
61 out.push_back(encoding); in emit_instruction()
64 encoding = (0b10 << 30); in emit_instruction()
65 encoding |= ctx.opcode[(int)aco_opcode::s_add_u32] << 23; in emit_instruction()
66 encoding |= dest << 16; in emit_instruction()
67 encoding |= dest; in emit_instruction()
68 encoding |= 255 << 8; in emit_instruction()
69 out.push_back(encoding); in emit_instruction()
74 encoding = (0b10 << 30); in emit_instruction()
75 encoding |= ctx.opcode[(int)aco_opcode::s_addc_u32] << 23; in emit_instruction()
76 encoding |= (dest + 1) << 16; in emit_instruction()
77 encoding |= dest + 1; in emit_instruction()
78 encoding |= 128 << 8; in emit_instruction()
79 out.push_back(encoding); in emit_instruction()
83 uint32_t opcode = ctx.opcode[(int)instr->opcode]; in emit_instruction()
84 if (opcode == (uint32_t)-1) { in emit_instruction()
101 switch (instr->format) { in emit_instruction()
103 uint32_t encoding = (0b10 << 30); in emit_instruction() local
104 encoding |= opcode << 23; in emit_instruction()
105 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0; in emit_instruction()
106 encoding |= instr->operands.size() >= 2 ? instr->operands[1].physReg() << 8 : 0; in emit_instruction()
107 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0; in emit_instruction()
108 out.push_back(encoding); in emit_instruction()
114 if (instr->opcode == aco_opcode::s_subvector_loop_begin) { in emit_instruction()
116 assert(ctx.subvector_begin_pos == -1); in emit_instruction()
118 } else if (instr->opcode == aco_opcode::s_subvector_loop_end) { in emit_instruction()
120 assert(ctx.subvector_begin_pos != -1); in emit_instruction()
122 out[ctx.subvector_begin_pos] |= (out.size() - ctx.subvector_begin_pos); in emit_instruction()
124 sopk->imm = (uint16_t)(ctx.subvector_begin_pos - (int)out.size()); in emit_instruction()
125 ctx.subvector_begin_pos = -1; in emit_instruction()
128 uint32_t encoding = (0b1011 << 28); in emit_instruction() local
129 encoding |= opcode << 23; in emit_instruction()
130 encoding |= in emit_instruction()
131 !instr->definitions.empty() && !(instr->definitions[0].physReg() == scc) ? in emit_instruction()
132 instr->definitions[0].physReg() << 16 : in emit_instruction()
133 !instr->operands.empty() && instr->operands[0].physReg() <= 127 ? in emit_instruction()
134 instr->operands[0].physReg() << 16 : 0; in emit_instruction()
135 encoding |= sopk->imm; in emit_instruction()
136 out.push_back(encoding); in emit_instruction()
140 uint32_t encoding = (0b101111101 << 23); in emit_instruction() local
143 opcode = opcode - 4; in emit_instruction()
145 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0; in emit_instruction()
146 encoding |= opcode << 8; in emit_instruction()
147 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0; in emit_instruction()
148 out.push_back(encoding); in emit_instruction()
152 uint32_t encoding = (0b101111110 << 23); in emit_instruction() local
153 encoding |= opcode << 16; in emit_instruction()
154 encoding |= instr->operands.size() == 2 ? instr->operands[1].physReg() << 8 : 0; in emit_instruction()
155 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0; in emit_instruction()
156 out.push_back(encoding); in emit_instruction()
161 uint32_t encoding = (0b101111111 << 23); in emit_instruction() local
162 encoding |= opcode << 16; in emit_instruction()
163 encoding |= (uint16_t) sopp->imm; in emit_instruction()
164 if (sopp->block != -1) { in emit_instruction()
165 sopp->pass_flags = 0; in emit_instruction()
168 out.push_back(encoding); in emit_instruction()
173 bool soe = instr->operands.size() >= (!instr->definitions.empty() ? 3 : 4); in emit_instruction()
174 bool is_load = !instr->definitions.empty(); in emit_instruction()
175 uint32_t encoding = 0; in emit_instruction() local
178 encoding = (0b11000 << 27); in emit_instruction()
179 encoding |= opcode << 22; in emit_instruction()
180 encoding |= instr->definitions.size() ? instr->definitions[0].physReg() << 15 : 0; in emit_instruction()
181 encoding |= instr->operands.size() ? (instr->operands[0].physReg() >> 1) << 9 : 0; in emit_instruction()
182 if (instr->operands.size() >= 2) { in emit_instruction()
183 if (!instr->operands[1].isConstant() || instr->operands[1].constantValue() >= 1024) { in emit_instruction()
184 encoding |= instr->operands[1].physReg().reg(); in emit_instruction()
186 encoding |= instr->operands[1].constantValue() >> 2; in emit_instruction()
187 encoding |= 1 << 8; in emit_instruction()
190 out.push_back(encoding); in emit_instruction()
192 …if (instr->operands.size() >= 2 && instr->operands[1].isConstant() && instr->operands[1].constantV… in emit_instruction()
193 out.push_back(instr->operands[1].constantValue() >> 2); in emit_instruction()
198 encoding = (0b110000 << 26); in emit_instruction()
199 assert(!smem->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
200 encoding |= smem->nv ? 1 << 15 : 0; in emit_instruction()
202 encoding = (0b111101 << 26); in emit_instruction()
203 assert(!smem->nv); /* Non-volatile is not supported on GFX10 */ in emit_instruction()
204 encoding |= smem->dlc ? 1 << 14 : 0; in emit_instruction()
207 encoding |= opcode << 18; in emit_instruction()
208 encoding |= smem->glc ? 1 << 16 : 0; in emit_instruction()
211 if (instr->operands.size() >= 2) in emit_instruction()
212 encoding |= instr->operands[1].isConstant() ? 1 << 17 : 0; /* IMM - immediate enable */ in emit_instruction()
215 encoding |= soe ? 1 << 14 : 0; in emit_instruction()
218 if (is_load || instr->operands.size() >= 3) { /* SDATA */ in emit_instruction()
219 … encoding |= (is_load ? instr->definitions[0].physReg() : instr->operands[2].physReg()) << 6; in emit_instruction()
221 if (instr->operands.size() >= 1) { /* SBASE */ in emit_instruction()
222 encoding |= instr->operands[0].physReg() >> 1; in emit_instruction()
225 out.push_back(encoding); in emit_instruction()
226 encoding = 0; in emit_instruction()
232 if (instr->operands.size() >= 2) { in emit_instruction()
233 const Operand &op_off1 = instr->operands[1]; in emit_instruction()
247 const Operand &op_off2 = instr->operands.back(); in emit_instruction()
253 encoding |= offset; in emit_instruction()
254 encoding |= soffset << 25; in emit_instruction()
256 out.push_back(encoding); in emit_instruction()
260 uint32_t encoding = 0; in emit_instruction() local
261 encoding |= opcode << 25; in emit_instruction()
262 encoding |= (0xFF & instr->definitions[0].physReg()) << 17; in emit_instruction()
263 encoding |= (0xFF & instr->operands[1].physReg()) << 9; in emit_instruction()
264 encoding |= instr->operands[0].physReg(); in emit_instruction()
265 out.push_back(encoding); in emit_instruction()
269 uint32_t encoding = (0b0111111 << 25); in emit_instruction() local
270 if (!instr->definitions.empty()) in emit_instruction()
271 encoding |= (0xFF & instr->definitions[0].physReg()) << 17; in emit_instruction()
272 encoding |= opcode << 9; in emit_instruction()
273 if (!instr->operands.empty()) in emit_instruction()
274 encoding |= instr->operands[0].physReg(); in emit_instruction()
275 out.push_back(encoding); in emit_instruction()
279 uint32_t encoding = (0b0111110 << 25); in emit_instruction() local
280 encoding |= opcode << 17; in emit_instruction()
281 encoding |= (0xFF & instr->operands[1].physReg()) << 9; in emit_instruction()
282 encoding |= instr->operands[0].physReg(); in emit_instruction()
283 out.push_back(encoding); in emit_instruction()
288 uint32_t encoding = 0; in emit_instruction() local
290 if (instr->opcode == aco_opcode::v_interp_p1ll_f16 || in emit_instruction()
291 instr->opcode == aco_opcode::v_interp_p1lv_f16 || in emit_instruction()
292 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 || in emit_instruction()
293 instr->opcode == aco_opcode::v_interp_p2_f16) { in emit_instruction()
295 encoding = (0b110100 << 26); in emit_instruction()
297 encoding = (0b110101 << 26); in emit_instruction()
302 encoding |= opcode << 16; in emit_instruction()
303 encoding |= (0xFF & instr->definitions[0].physReg()); in emit_instruction()
304 out.push_back(encoding); in emit_instruction()
306 encoding = 0; in emit_instruction()
307 encoding |= interp->attribute; in emit_instruction()
308 encoding |= interp->component << 6; in emit_instruction()
309 encoding |= instr->operands[0].physReg() << 9; in emit_instruction()
310 if (instr->opcode == aco_opcode::v_interp_p2_f16 || in emit_instruction()
311 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 || in emit_instruction()
312 instr->opcode == aco_opcode::v_interp_p1lv_f16) { in emit_instruction()
313 encoding |= instr->operands[2].physReg() << 18; in emit_instruction()
315 out.push_back(encoding); in emit_instruction()
318 encoding = (0b110101 << 26); /* Vega ISA doc says 110010 but it's wrong */ in emit_instruction()
320 encoding = (0b110010 << 26); in emit_instruction()
323 assert(encoding); in emit_instruction()
324 encoding |= (0xFF & instr->definitions[0].physReg()) << 18; in emit_instruction()
325 encoding |= opcode << 16; in emit_instruction()
326 encoding |= interp->attribute << 10; in emit_instruction()
327 encoding |= interp->component << 8; in emit_instruction()
328 if (instr->opcode == aco_opcode::v_interp_mov_f32) in emit_instruction()
329 encoding |= (0x3 & instr->operands[0].constantValue()); in emit_instruction()
331 encoding |= (0xFF & instr->operands[0].physReg()); in emit_instruction()
332 out.push_back(encoding); in emit_instruction()
338 uint32_t encoding = (0b110110 << 26); in emit_instruction() local
340 encoding |= opcode << 17; in emit_instruction()
341 encoding |= (ds->gds ? 1 : 0) << 16; in emit_instruction()
343 encoding |= opcode << 18; in emit_instruction()
344 encoding |= (ds->gds ? 1 : 0) << 17; in emit_instruction()
346 encoding |= ((0xFF & ds->offset1) << 8); in emit_instruction()
347 encoding |= (0xFFFF & ds->offset0); in emit_instruction()
348 out.push_back(encoding); in emit_instruction()
349 encoding = 0; in emit_instruction()
350 unsigned reg = !instr->definitions.empty() ? instr->definitions[0].physReg() : 0; in emit_instruction()
351 encoding |= (0xFF & reg) << 24; in emit_instruction()
352 …reg = instr->operands.size() >= 3 && !(instr->operands[2].physReg() == m0) ? instr->operands[2].p… in emit_instruction()
353 encoding |= (0xFF & reg) << 16; in emit_instruction()
354 …reg = instr->operands.size() >= 2 && !(instr->operands[1].physReg() == m0) ? instr->operands[1].ph… in emit_instruction()
355 encoding |= (0xFF & reg) << 8; in emit_instruction()
356 encoding |= (0xFF & instr->operands[0].physReg()); in emit_instruction()
357 out.push_back(encoding); in emit_instruction()
362 uint32_t encoding = (0b111000 << 26); in emit_instruction() local
363 encoding |= opcode << 18; in emit_instruction()
364 encoding |= (mubuf->lds ? 1 : 0) << 16; in emit_instruction()
365 encoding |= (mubuf->glc ? 1 : 0) << 14; in emit_instruction()
366 encoding |= (mubuf->idxen ? 1 : 0) << 13; in emit_instruction()
367 assert(!mubuf->addr64 || ctx.chip_class <= GFX7); in emit_instruction()
369 encoding |= (mubuf->addr64 ? 1 : 0) << 15; in emit_instruction()
370 encoding |= (mubuf->offen ? 1 : 0) << 12; in emit_instruction()
372 assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
373 encoding |= (mubuf->slc ? 1 : 0) << 17; in emit_instruction()
375 encoding |= (mubuf->dlc ? 1 : 0) << 15; in emit_instruction()
377 encoding |= 0x0FFF & mubuf->offset; in emit_instruction()
378 out.push_back(encoding); in emit_instruction()
379 encoding = 0; in emit_instruction()
381 encoding |= (mubuf->slc ? 1 : 0) << 22; in emit_instruction()
383 encoding |= instr->operands[2].physReg() << 24; in emit_instruction()
384 encoding |= (mubuf->tfe ? 1 : 0) << 23; in emit_instruction()
385 encoding |= (instr->operands[0].physReg() >> 2) << 16; in emit_instruction()
386 …unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg() : instr->definitions[0].p… in emit_instruction()
387 encoding |= (0xFF & reg) << 8; in emit_instruction()
388 encoding |= (0xFF & instr->operands[1].physReg()); in emit_instruction()
389 out.push_back(encoding); in emit_instruction()
395 uint32_t img_format = ac_get_tbuffer_format(ctx.chip_class, mtbuf->dfmt, mtbuf->nfmt); in emit_instruction()
396 uint32_t encoding = (0b111010 << 26); in emit_instruction() local
398 assert(!mtbuf->dlc || ctx.chip_class >= GFX10); in emit_instruction()
399 encoding |= (mtbuf->dlc ? 1 : 0) << 15; /* DLC bit replaces one bit of the OPCODE on GFX10 */ in emit_instruction()
400 encoding |= (mtbuf->glc ? 1 : 0) << 14; in emit_instruction()
401 encoding |= (mtbuf->idxen ? 1 : 0) << 13; in emit_instruction()
402 encoding |= (mtbuf->offen ? 1 : 0) << 12; in emit_instruction()
403 encoding |= 0x0FFF & mtbuf->offset; in emit_instruction()
404 encoding |= (img_format << 19); /* Handles both the GFX10 FORMAT and the old NFMT+DFMT */ in emit_instruction()
407 encoding |= opcode << 15; in emit_instruction()
409 encoding |= (opcode & 0x07) << 16; /* 3 LSBs of 4-bit OPCODE */ in emit_instruction()
412 out.push_back(encoding); in emit_instruction()
413 encoding = 0; in emit_instruction()
415 encoding |= instr->operands[2].physReg() << 24; in emit_instruction()
416 encoding |= (mtbuf->tfe ? 1 : 0) << 23; in emit_instruction()
417 encoding |= (mtbuf->slc ? 1 : 0) << 22; in emit_instruction()
418 encoding |= (instr->operands[0].physReg() >> 2) << 16; in emit_instruction()
419 …unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg() : instr->definitions[0].p… in emit_instruction()
420 encoding |= (0xFF & reg) << 8; in emit_instruction()
421 encoding |= (0xFF & instr->operands[1].physReg()); in emit_instruction()
424 encoding |= (((opcode & 0x08) >> 3) << 21); /* MSB of 4-bit OPCODE */ in emit_instruction()
427 out.push_back(encoding); in emit_instruction()
432 uint32_t encoding = (0b111100 << 26); in emit_instruction() local
433 encoding |= mimg->slc ? 1 << 25 : 0; in emit_instruction()
434 encoding |= opcode << 18; in emit_instruction()
435 encoding |= mimg->lwe ? 1 << 17 : 0; in emit_instruction()
436 encoding |= mimg->tfe ? 1 << 16 : 0; in emit_instruction()
437 encoding |= mimg->glc ? 1 << 13 : 0; in emit_instruction()
438 encoding |= mimg->unrm ? 1 << 12 : 0; in emit_instruction()
440 assert(!mimg->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
441 assert(!mimg->r128); in emit_instruction()
442 encoding |= mimg->a16 ? 1 << 15 : 0; in emit_instruction()
443 encoding |= mimg->da ? 1 << 14 : 0; in emit_instruction()
445 …encoding |= mimg->r128 ? 1 << 15 : 0; /* GFX10: A16 moved to 2nd word, R128 replaces it in 1st wor… in emit_instruction()
446 encoding |= mimg->dim << 3; /* GFX10: dimensionality instead of declare array */ in emit_instruction()
447 encoding |= mimg->dlc ? 1 << 7 : 0; in emit_instruction()
449 encoding |= (0xF & mimg->dmask) << 8; in emit_instruction()
450 out.push_back(encoding); in emit_instruction()
451 encoding = (0xFF & instr->operands[2].physReg()); /* VADDR */ in emit_instruction()
452 if (!instr->definitions.empty()) { in emit_instruction()
453 encoding |= (0xFF & instr->definitions[0].physReg()) << 8; /* VDATA */ in emit_instruction()
454 } else if (instr->operands[1].regClass().type() == RegType::vgpr) { in emit_instruction()
455 encoding |= (0xFF & instr->operands[1].physReg()) << 8; /* VDATA */ in emit_instruction()
457 encoding |= (0x1F & (instr->operands[0].physReg() >> 2)) << 16; /* T# (resource) */ in emit_instruction()
458 if (instr->operands[1].regClass().type() == RegType::sgpr) in emit_instruction()
459 encoding |= (0x1F & (instr->operands[1].physReg() >> 2)) << 21; /* sampler */ in emit_instruction()
461 assert(!mimg->d16 || ctx.chip_class >= GFX9); in emit_instruction()
462 encoding |= mimg->d16 ? 1 << 15 : 0; in emit_instruction()
464 … encoding |= mimg->a16 ? 1 << 14 : 0; /* GFX10: A16 still exists, but is in a different place */ in emit_instruction()
467 out.push_back(encoding); in emit_instruction()
474 uint32_t encoding = (0b110111 << 26); in emit_instruction() local
475 encoding |= opcode << 18; in emit_instruction()
477 assert(flat->offset <= 0x1fff); in emit_instruction()
478 encoding |= flat->offset & 0x1fff; in emit_instruction()
479 } else if (instr->format == Format::FLAT) { in emit_instruction()
480 /* GFX10 has a 12-bit immediate OFFSET field, in emit_instruction()
483 assert(flat->offset == 0); in emit_instruction()
485 assert(flat->offset <= 0xfff); in emit_instruction()
486 encoding |= flat->offset & 0xfff; in emit_instruction()
488 if (instr->format == Format::SCRATCH) in emit_instruction()
489 encoding |= 1 << 14; in emit_instruction()
490 else if (instr->format == Format::GLOBAL) in emit_instruction()
491 encoding |= 2 << 14; in emit_instruction()
492 encoding |= flat->lds ? 1 << 13 : 0; in emit_instruction()
493 encoding |= flat->glc ? 1 << 16 : 0; in emit_instruction()
494 encoding |= flat->slc ? 1 << 17 : 0; in emit_instruction()
496 assert(!flat->nv); in emit_instruction()
497 encoding |= flat->dlc ? 1 << 12 : 0; in emit_instruction()
499 assert(!flat->dlc); in emit_instruction()
501 out.push_back(encoding); in emit_instruction()
502 encoding = (0xFF & instr->operands[0].physReg()); in emit_instruction()
503 if (!instr->definitions.empty()) in emit_instruction()
504 encoding |= (0xFF & instr->definitions[0].physReg()) << 24; in emit_instruction()
505 if (instr->operands.size() >= 3) in emit_instruction()
506 encoding |= (0xFF & instr->operands[2].physReg()) << 8; in emit_instruction()
507 if (!instr->operands[1].isUndefined()) { in emit_instruction()
508 assert(ctx.chip_class >= GFX10 || instr->operands[1].physReg() != 0x7F); in emit_instruction()
509 assert(instr->format != Format::FLAT); in emit_instruction()
510 encoding |= instr->operands[1].physReg() << 16; in emit_instruction()
511 …} else if (instr->format != Format::FLAT || ctx.chip_class >= GFX10) { /* SADDR is actually used w… in emit_instruction()
513 encoding |= 0x7F << 16; in emit_instruction()
515 encoding |= sgpr_null << 16; in emit_instruction()
517 encoding |= flat->nv ? 1 << 23 : 0; in emit_instruction()
518 out.push_back(encoding); in emit_instruction()
523 uint32_t encoding; in emit_instruction() local
525 encoding = (0b110001 << 26); in emit_instruction()
527 encoding = (0b111110 << 26); in emit_instruction()
530 encoding |= exp->valid_mask ? 0b1 << 12 : 0; in emit_instruction()
531 encoding |= exp->done ? 0b1 << 11 : 0; in emit_instruction()
532 encoding |= exp->compressed ? 0b1 << 10 : 0; in emit_instruction()
533 encoding |= exp->dest << 4; in emit_instruction()
534 encoding |= exp->enabled_mask; in emit_instruction()
535 out.push_back(encoding); in emit_instruction()
536 encoding = 0xFF & exp->operands[0].physReg(); in emit_instruction()
537 encoding |= (0xFF & exp->operands[1].physReg()) << 8; in emit_instruction()
538 encoding |= (0xFF & exp->operands[2].physReg()) << 16; in emit_instruction()
539 encoding |= (0xFF & exp->operands[3].physReg()) << 24; in emit_instruction()
540 out.push_back(encoding); in emit_instruction()
545 if (instr->opcode != aco_opcode::p_unit_test) in emit_instruction()
549 if ((uint16_t) instr->format & (uint16_t) Format::VOP3A) { in emit_instruction()
552 if ((uint16_t) instr->format & (uint16_t) Format::VOP2) { in emit_instruction()
554 } else if ((uint16_t) instr->format & (uint16_t) Format::VOP1) { in emit_instruction()
559 } else if ((uint16_t) instr->format & (uint16_t) Format::VOPC) { in emit_instruction()
561 } else if ((uint16_t) instr->format & (uint16_t) Format::VINTRP) { in emit_instruction()
565 uint32_t encoding; in emit_instruction() local
567 encoding = (0b110100 << 26); in emit_instruction()
569 encoding = (0b110101 << 26); in emit_instruction()
575 encoding |= opcode << 17; in emit_instruction()
576 encoding |= (vop3->clamp ? 1 : 0) << 11; in emit_instruction()
578 encoding |= opcode << 16; in emit_instruction()
579 encoding |= (vop3->clamp ? 1 : 0) << 15; in emit_instruction()
581 encoding |= vop3->opsel << 11; in emit_instruction()
583 encoding |= vop3->abs[i] << (8+i); in emit_instruction()
584 if (instr->definitions.size() == 2) in emit_instruction()
585 encoding |= instr->definitions[1].physReg() << 8; in emit_instruction()
586 encoding |= (0xFF & instr->definitions[0].physReg()); in emit_instruction()
587 out.push_back(encoding); in emit_instruction()
588 encoding = 0; in emit_instruction()
589 if (instr->opcode == aco_opcode::v_interp_mov_f32) { in emit_instruction()
590 encoding = 0x3 & instr->operands[0].constantValue(); in emit_instruction()
592 for (unsigned i = 0; i < instr->operands.size(); i++) in emit_instruction()
593 encoding |= instr->operands[i].physReg() << (i * 9); in emit_instruction()
595 encoding |= vop3->omod << 27; in emit_instruction()
597 encoding |= vop3->neg[i] << (29+i); in emit_instruction()
598 out.push_back(encoding); in emit_instruction()
600 } else if (instr->format == Format::VOP3P) { in emit_instruction()
603 uint32_t encoding; in emit_instruction() local
605 encoding = (0b110100111 << 23); in emit_instruction()
607 encoding = (0b110011 << 26); in emit_instruction()
612 encoding |= opcode << 16; in emit_instruction()
613 encoding |= (vop3->clamp ? 1 : 0) << 15; in emit_instruction()
614 encoding |= vop3->opsel_lo << 11; in emit_instruction()
615 encoding |= (vop3->opsel_hi & 0x4) ? 1 : 0 << 14; in emit_instruction()
617 encoding |= vop3->neg_hi[i] << (8+i); in emit_instruction()
618 encoding |= (0xFF & instr->definitions[0].physReg()); in emit_instruction()
619 out.push_back(encoding); in emit_instruction()
620 encoding = 0; in emit_instruction()
621 for (unsigned i = 0; i < instr->operands.size(); i++) in emit_instruction()
622 encoding |= instr->operands[i].physReg() << (i * 9); in emit_instruction()
623 encoding |= vop3->opsel_hi & 0x3 << 27; in emit_instruction()
625 encoding |= vop3->neg_lo[i] << (29+i); in emit_instruction()
626 out.push_back(encoding); in emit_instruction()
628 } else if (instr->isDPP()){ in emit_instruction()
631 Operand dpp_op = instr->operands[0]; in emit_instruction()
632 instr->operands[0] = Operand(PhysReg{250}, v1); in emit_instruction()
633 instr->format = (Format) ((uint16_t) instr->format & ~(uint16_t)Format::DPP); in emit_instruction()
636 uint32_t encoding = (0xF & dpp->row_mask) << 28; in emit_instruction() local
637 encoding |= (0xF & dpp->bank_mask) << 24; in emit_instruction()
638 encoding |= dpp->abs[1] << 23; in emit_instruction()
639 encoding |= dpp->neg[1] << 22; in emit_instruction()
640 encoding |= dpp->abs[0] << 21; in emit_instruction()
641 encoding |= dpp->neg[0] << 20; in emit_instruction()
643 encoding |= 1 << 18; /* set Fetch Inactive to match GFX9 behaviour */ in emit_instruction()
644 encoding |= dpp->bound_ctrl << 19; in emit_instruction()
645 encoding |= dpp->dpp_ctrl << 8; in emit_instruction()
646 encoding |= (0xFF) & dpp_op.physReg(); in emit_instruction()
647 out.push_back(encoding); in emit_instruction()
649 } else if (instr->isSDWA()) { in emit_instruction()
651 Operand sdwa_op = instr->operands[0]; in emit_instruction()
652 instr->operands[0] = Operand(PhysReg{249}, v1); in emit_instruction()
653 instr->format = (Format) ((uint16_t) instr->format & ~(uint16_t)Format::SDWA); in emit_instruction()
657 uint32_t encoding = 0; in emit_instruction() local
659 if ((uint16_t)instr->format & (uint16_t)Format::VOPC) { in emit_instruction()
660 if (instr->definitions[0].physReg() != vcc) { in emit_instruction()
661 encoding |= instr->definitions[0].physReg() << 8; in emit_instruction()
662 encoding |= 1 << 15; in emit_instruction()
664 encoding |= (sdwa->clamp ? 1 : 0) << 13; in emit_instruction()
666 encoding |= get_sdwa_sel(sdwa->dst_sel, instr->definitions[0].physReg()) << 8; in emit_instruction()
667 uint32_t dst_u = sdwa->dst_sel & sdwa_sext ? 1 : 0; in emit_instruction()
668 if (sdwa->dst_preserve || (sdwa->dst_sel & sdwa_isra)) in emit_instruction()
670 encoding |= dst_u << 11; in emit_instruction()
671 encoding |= (sdwa->clamp ? 1 : 0) << 13; in emit_instruction()
672 encoding |= sdwa->omod << 14; in emit_instruction()
675 encoding |= get_sdwa_sel(sdwa->sel[0], sdwa_op.physReg()) << 16; in emit_instruction()
676 encoding |= sdwa->sel[0] & sdwa_sext ? 1 << 19 : 0; in emit_instruction()
677 encoding |= sdwa->abs[0] << 21; in emit_instruction()
678 encoding |= sdwa->neg[0] << 20; in emit_instruction()
680 if (instr->operands.size() >= 2) { in emit_instruction()
681 encoding |= get_sdwa_sel(sdwa->sel[1], instr->operands[1].physReg()) << 24; in emit_instruction()
682 encoding |= sdwa->sel[1] & sdwa_sext ? 1 << 27 : 0; in emit_instruction()
683 encoding |= sdwa->abs[1] << 29; in emit_instruction()
684 encoding |= sdwa->neg[1] << 28; in emit_instruction()
687 encoding |= 0xFF & sdwa_op.physReg(); in emit_instruction()
688 encoding |= (sdwa_op.physReg() < 256) << 23; in emit_instruction()
689 if (instr->operands.size() >= 2) in emit_instruction()
690 encoding |= (instr->operands[1].physReg() < 256) << 31; in emit_instruction()
691 out.push_back(encoding); in emit_instruction()
699 for (const Operand& op : instr->operands) { in emit_instruction()
712 std::cerr << "Encoding:\t" << std::endl; in emit_block()
719 …std::cerr << "encoding: " << "0x" << std::setfill('0') << std::setw(8) << std::hex << out[i] << st… in emit_block()
727 for (Block& block : program->blocks) { in fix_exports()
733 if ((*it)->format == Format::EXP) { in fix_exports()
735 if (program->stage.hw == HWStage::VS || program->stage.hw == HWStage::NGG) { in fix_exports()
736 if (exp->dest >= V_008DFC_SQ_EXP_POS && exp->dest <= (V_008DFC_SQ_EXP_POS + 3)) { in fix_exports()
737 exp->done = true; in fix_exports()
742 exp->done = true; in fix_exports()
743 exp->valid_mask = true; in fix_exports()
747 } else if ((*it)->definitions.size() && (*it)->definitions[0].physReg() == exec) in fix_exports()
755 … bool is_vertex_or_ngg = (program->stage.hw == HWStage::VS || program->stage.hw == HWStage::NGG); in fix_exports()
768 for (Block& block : ctx.program->blocks) { in insert_code()
774 …td::find_if(ctx.branches.begin(), ctx.branches.end(), [insert_before](const auto &branch) -> bool { in insert_code()
780 branch_it->first += insert_count; in insert_code()
783 …nd_if(ctx.constaddrs.begin(), ctx.constaddrs.end(), [insert_before](const int &caddr_pos) -> bool { in insert_code()
798 …ch_it = std::find_if(ctx.branches.begin(), ctx.branches.end(), [&ctx](const auto &branch) -> bool { in fix_branches_gfx10()
799 return ((int)ctx.program->blocks[branch.second->block].offset - branch.first - 1) == 0x3f; in fix_branches_gfx10()
807 insert_code(ctx, out, buggy_branch_it->first + 1, 1, &s_nop_0); in fix_branches_gfx10()
816 Definition def_tmp_lo(branch->definitions[0].physReg(), s1); in emit_long_jump()
817 Operand op_tmp_lo(branch->definitions[0].physReg(), s1); in emit_long_jump()
818 Definition def_tmp_hi(branch->definitions[0].physReg().advance(4), s1); in emit_long_jump()
819 Operand op_tmp_hi(branch->definitions[0].physReg().advance(4), s1); in emit_long_jump()
823 if (branch->opcode != aco_opcode::s_branch) { in emit_long_jump()
826 switch (branch->opcode) { in emit_long_jump()
848 instr.reset(bld.sopp(inv, -1, 7)); in emit_long_jump()
853 instr.reset(bld.sop1(aco_opcode::s_getpc_b64, branch->definitions[0]).instr); in emit_long_jump()
857 instr->operands[1].setFixed(PhysReg{255}); /* this operand has to be a literal */ in emit_long_jump()
859 branch->pass_flags = out.size(); in emit_long_jump()
871 …instr.reset(bld.sop1(aco_opcode::s_setpc_b64, Operand(branch->definitions[0].physReg(), s2)).instr… in emit_long_jump()
885 int offset = (int)ctx.program->blocks[branch.second->block].offset - branch.first - 1; in fix_branches()
886 if ((offset < INT16_MIN || offset > INT16_MAX) && !branch.second->pass_flags) { in fix_branches()
888 … bool backwards = ctx.program->blocks[branch.second->block].offset < (unsigned)branch.first; in fix_branches()
892 insert_code(ctx, out, branch.first + 1, long_jump.size() - 1, long_jump.data() + 1); in fix_branches()
898 if (branch.second->pass_flags) { in fix_branches()
899 int after_getpc = branch.first + branch.second->pass_flags - 2; in fix_branches()
900 offset = (int)ctx.program->blocks[branch.second->block].offset - after_getpc; in fix_branches()
901 out[branch.first + branch.second->pass_flags - 1] = offset * 4; in fix_branches()
913 out[addr] += (out.size() - addr + 1u) * 4u; in fix_constaddrs()
921 if (program->stage.hw == HWStage::VS || in emit_program()
922 program->stage.hw == HWStage::FS || in emit_program()
923 program->stage.hw == HWStage::NGG) in emit_program()
926 for (Block& block : program->blocks) { in emit_program()
935 if (program->chip_class >= GFX10) { in emit_program()
945 while (program->constant_data.size() % 4u) in emit_program()
946 program->constant_data.push_back(0); in emit_program()
948 code.insert(code.end(), (uint32_t*)program->constant_data.data(), in emit_program()
949 (uint32_t*)(program->constant_data.data() + program->constant_data.size())); in emit_program()