| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/MCTargetDesc/ |
| D | ARCInfo.h | 24 enum CondCode { enum
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiCondCode.h | 10 enum CondCode { enum
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| D | LanaiInstrInfo.cpp | 525 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiCondCode.h | 10 enum CondCode { enum
|
| D | LanaiInstrInfo.cpp | 522 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SpeculationHardening.cpp | 226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode()
247 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
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| D | AArch64InstructionSelector.cpp | 927 AArch64CC::CondCode &CondCode, in changeFCMPPredToAArch64CC()
3525 AArch64CC::CondCode CondCode; in tryOptSelect() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.h | 32 enum CondCode { enum
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.h | 33 enum CondCode { enum
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 33 enum CondCode { enum
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 38 enum CondCode { enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 37 enum CondCode { enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 1053 LPCC::CondCode CondCode = in splitMnemonic() local
1073 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
|
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 1030 LPCC::CondCode CondCode = in splitMnemonic() local
1050 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 235 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/AsmParser/ |
| D | MSP430AsmParser.cpp | 318 unsigned CondCode; in parseJccInstruction() local
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 850 enum CondCode { enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 75 enum CondCode { enum
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 537 static unsigned getPTXCmpMode(const CondCodeSDNode &CondCode, bool FTZ) { in getPTXCmpMode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1047 enum CondCode { enum
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1346 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
3462 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
3648 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in checkVSELConstraints()
3892 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in LowerSELECT_CC() local
3906 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
4050 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
4097 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1849 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
4323 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
4647 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in checkVSELConstraints()
5037 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in LowerSELECT_CC() local
5054 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
5199 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
5233 ARMCC::CondCodes CondCode = in LowerBRCOND() local
5286 ARMCC::CondCodes CondCode = in LowerBR_CC() local
5312 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
9264 ARMCC::CondCodes CondCode, CondCode2; in LowerFSETCC() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 986 unsigned CondCode = MI.getOperand(3).getImm(); in EmitF128CSEL() local
1079 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC()
1142 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC()
1172 AArch64CC::CondCode &CondCode, in changeVectorFPCCToAArch64CC()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1005 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); in performVSELECTCombine() local
|