1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef SOC_DEFAULT_HELPER_MACROS_H 9 #define SOC_DEFAULT_HELPER_MACROS_H 10 11 #ifdef NXP_OCRAM_TZPC_ADDR 12 13 /* 0x1: means 4 KB 14 * 0x2: means 8 KB 15 */ 16 #define TZPC_BLOCK_SIZE 0x1000 17 #endif 18 19 /* DDR controller offsets and defines */ 20 #ifdef NXP_DDR_ADDR 21 22 #define DDR_CFG_2_OFFSET 0x114 23 #define CFG_2_FORCE_REFRESH 0x80000000 24 25 #endif /* NXP_DDR_ADDR */ 26 27 /* Reset block register offsets */ 28 #ifdef NXP_RESET_ADDR 29 30 /* Register Offset */ 31 #define RST_RSTCR_OFFSET 0x0 32 #define RST_RSTRQMR1_OFFSET 0x10 33 #define RST_RSTRQSR1_OFFSET 0x18 34 #define BRR_OFFSET 0x60 35 36 /* helper macros */ 37 #define RSTRQSR1_SWRR 0x800 38 #define RSTRQMR_RPTOE_MASK (1 << 19) 39 40 #endif /* NXP_RESET_ADDR */ 41 42 /* Secure-Register-File register offsets and bit masks */ 43 #ifdef NXP_RST_ADDR 44 /* Register Offset */ 45 #define CORE_HOLD_OFFSET 0x140 46 #define RSTCNTL_OFFSET 0x180 47 48 /* Helper macros */ 49 #define SW_RST_REQ_INIT 0x1 50 #endif 51 52 #ifdef NXP_CCN_ADDR 53 #define NXP_CCN_HN_F_1_ADDR 0x04210000 54 55 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 56 #define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200 57 #define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210 58 #define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220 59 #define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00 60 #define CCN_HNF_NODE_COUNT 8 61 #define CCN_HNF_OFFSET 0x10000 62 63 #define SA_AUX_CTRL_REG_OFFSET 0x500 64 #define NUM_HNI_NODE 2 65 #define CCN_HNI_MEMORY_MAP_SIZE 0x10000 66 67 #define PCIeRC_RN_I_NODE_ID_OFFSET 0x8 68 #define PoS_CONTROL_REG_OFFSET 0x0 69 #define POS_EARLY_WR_COMP_EN 0x20 70 #define HNI_POS_EN 0x01 71 #define POS_TERMINATE_BARRIERS 0x10 72 #define SERIALIZE_DEV_nGnRnE_WRITES 0x200 73 #define ENABLE_ERR_SIGNAL_TO_MN 0x4 74 #define ENABLE_RESERVE_BIT53 0x400 75 #define ENABLE_WUO 0x10 76 #endif /* NXP_CCN_ADDR */ 77 78 #endif /* SOC_DEFAULT_HELPER_MACROS_H */ 79