1 /*
2 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
3 *
4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10 */
11
12 #ifndef AOM_AOM_PORTS_X86_H_
13 #define AOM_AOM_PORTS_X86_H_
14 #include <stdlib.h>
15
16 #if defined(_MSC_VER)
17 #include <intrin.h> /* For __cpuidex, __rdtsc */
18 #endif
19
20 #include "aom/aom_integer.h"
21 #include "config/aom_config.h"
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 typedef enum {
28 AOM_CPU_UNKNOWN = -1,
29 AOM_CPU_AMD,
30 AOM_CPU_AMD_OLD,
31 AOM_CPU_CENTAUR,
32 AOM_CPU_CYRIX,
33 AOM_CPU_INTEL,
34 AOM_CPU_NEXGEN,
35 AOM_CPU_NSC,
36 AOM_CPU_RISE,
37 AOM_CPU_SIS,
38 AOM_CPU_TRANSMETA,
39 AOM_CPU_TRANSMETA_OLD,
40 AOM_CPU_UMC,
41 AOM_CPU_VIA,
42
43 AOM_CPU_LAST
44 } aom_cpu_t;
45
46 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
47 #if ARCH_X86_64
48 #define cpuid(func, func2, ax, bx, cx, dx) \
49 __asm__ __volatile__("cpuid \n\t" \
50 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
51 : "a"(func), "c"(func2));
52 #else
53 #define cpuid(func, func2, ax, bx, cx, dx) \
54 __asm__ __volatile__( \
55 "mov %%ebx, %%edi \n\t" \
56 "cpuid \n\t" \
57 "xchg %%edi, %%ebx \n\t" \
58 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
59 : "a"(func), "c"(func2));
60 #endif
61 #elif defined(__SUNPRO_C) || \
62 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
63 #if ARCH_X86_64
64 #define cpuid(func, func2, ax, bx, cx, dx) \
65 asm volatile( \
66 "xchg %rsi, %rbx \n\t" \
67 "cpuid \n\t" \
68 "movl %ebx, %edi \n\t" \
69 "xchg %rsi, %rbx \n\t" \
70 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
71 : "a"(func), "c"(func2));
72 #else
73 #define cpuid(func, func2, ax, bx, cx, dx) \
74 asm volatile( \
75 "pushl %ebx \n\t" \
76 "cpuid \n\t" \
77 "movl %ebx, %edi \n\t" \
78 "popl %ebx \n\t" \
79 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
80 : "a"(func), "c"(func2));
81 #endif
82 #else /* end __SUNPRO__ */
83 #if ARCH_X86_64
84 #if defined(_MSC_VER) && _MSC_VER > 1500
85 #define cpuid(func, func2, a, b, c, d) \
86 do { \
87 int regs[4]; \
88 __cpuidex(regs, func, func2); \
89 a = regs[0]; \
90 b = regs[1]; \
91 c = regs[2]; \
92 d = regs[3]; \
93 } while (0)
94 #else
95 #define cpuid(func, func2, a, b, c, d) \
96 do { \
97 int regs[4]; \
98 __cpuid(regs, func); \
99 a = regs[0]; \
100 b = regs[1]; \
101 c = regs[2]; \
102 d = regs[3]; \
103 } while (0)
104 #endif
105 #else
106 /* clang-format off */
107 #define cpuid(func, func2, a, b, c, d) \
108 __asm mov eax, func \
109 __asm mov ecx, func2 \
110 __asm cpuid \
111 __asm mov a, eax \
112 __asm mov b, ebx \
113 __asm mov c, ecx \
114 __asm mov d, edx
115 #endif
116 /* clang-format on */
117 #endif /* end others */
118
119 // NaCl has no support for xgetbv or the raw opcode.
120 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
xgetbv(void)121 static INLINE uint64_t xgetbv(void) {
122 const uint32_t ecx = 0;
123 uint32_t eax, edx;
124 // Use the raw opcode for xgetbv for compatibility with older toolchains.
125 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
126 : "=a"(eax), "=d"(edx)
127 : "c"(ecx));
128 return ((uint64_t)edx << 32) | eax;
129 }
130 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
131 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
132 #include <immintrin.h>
133 #define xgetbv() _xgetbv(0)
134 #elif defined(_MSC_VER) && defined(_M_IX86)
xgetbv(void)135 static INLINE uint64_t xgetbv(void) {
136 uint32_t eax_, edx_;
137 __asm {
138 xor ecx, ecx // ecx = 0
139 // Use the raw opcode for xgetbv for compatibility with older toolchains.
140 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
141 mov eax_, eax
142 mov edx_, edx
143 }
144 return ((uint64_t)edx_ << 32) | eax_;
145 }
146 #else
147 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
148 #endif
149
150 #if defined(_MSC_VER) && _MSC_VER >= 1700
151 #include <windows.h>
152 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
153 #define getenv(x) NULL
154 #endif
155 #endif
156
157 #define HAS_MMX 0x01
158 #define HAS_SSE 0x02
159 #define HAS_SSE2 0x04
160 #define HAS_SSE3 0x08
161 #define HAS_SSSE3 0x10
162 #define HAS_SSE4_1 0x20
163 #define HAS_AVX 0x40
164 #define HAS_AVX2 0x80
165 #define HAS_SSE4_2 0x100
166 #ifndef BIT
167 #define BIT(n) (1u << (n))
168 #endif
169
x86_simd_caps(void)170 static INLINE int x86_simd_caps(void) {
171 unsigned int flags = 0;
172 unsigned int mask = ~0u;
173 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
174 char *env;
175
176 /* See if the CPU capabilities are being overridden by the environment */
177 env = getenv("AOM_SIMD_CAPS");
178
179 if (env && *env) return (int)strtol(env, NULL, 0);
180
181 env = getenv("AOM_SIMD_CAPS_MASK");
182
183 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
184
185 /* Ensure that the CPUID instruction supports extended features */
186 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
187
188 if (max_cpuid_val < 1) return 0;
189
190 /* Get the standard feature flags */
191 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
192
193 if (reg_edx & BIT(23)) flags |= HAS_MMX;
194
195 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
196
197 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
198
199 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
200
201 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
202
203 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
204
205 if (reg_ecx & BIT(20)) flags |= HAS_SSE4_2;
206
207 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
208 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
209 // Check for OS-support of YMM state. Necessary for AVX and AVX2.
210 if ((xgetbv() & 0x6) == 0x6) {
211 flags |= HAS_AVX;
212
213 if (max_cpuid_val >= 7) {
214 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
215 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
216
217 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
218 }
219 }
220 }
221
222 (void)reg_eax; // Avoid compiler warning on unused-but-set variable.
223
224 return flags & mask;
225 }
226
227 // Fine-Grain Measurement Functions
228 //
229 // If you are timing a small region of code, access the timestamp counter
230 // (TSC) via:
231 //
232 // unsigned int start = x86_tsc_start();
233 // ...
234 // unsigned int end = x86_tsc_end();
235 // unsigned int diff = end - start;
236 //
237 // The start/end functions introduce a few more instructions than using
238 // x86_readtsc directly, but prevent the CPU's out-of-order execution from
239 // affecting the measurement (by having earlier/later instructions be evaluated
240 // in the time interval). See the white paper, "How to Benchmark Code
241 // Execution Times on Intel(R) IA-32 and IA-64 Instruction Set Architectures" by
242 // Gabriele Paoloni for more information.
243 //
244 // If you are timing a large function (CPU time > a couple of seconds), use
245 // x86_readtsc64 to read the timestamp counter in a 64-bit integer. The
246 // out-of-order leakage that can occur is minimal compared to total runtime.
x86_readtsc(void)247 static INLINE unsigned int x86_readtsc(void) {
248 #if defined(__GNUC__) && __GNUC__
249 unsigned int tsc;
250 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
251 return tsc;
252 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
253 unsigned int tsc;
254 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
255 return tsc;
256 #else
257 #if ARCH_X86_64
258 return (unsigned int)__rdtsc();
259 #else
260 __asm rdtsc;
261 #endif
262 #endif
263 }
264 // 64-bit CPU cycle counter
x86_readtsc64(void)265 static INLINE uint64_t x86_readtsc64(void) {
266 #if defined(__GNUC__) && __GNUC__
267 uint32_t hi, lo;
268 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
269 return ((uint64_t)hi << 32) | lo;
270 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
271 uint_t hi, lo;
272 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
273 return ((uint64_t)hi << 32) | lo;
274 #else
275 #if ARCH_X86_64
276 return (uint64_t)__rdtsc();
277 #else
278 __asm rdtsc;
279 #endif
280 #endif
281 }
282
283 // 32-bit CPU cycle counter with a partial fence against out-of-order execution.
x86_readtscp(void)284 static INLINE unsigned int x86_readtscp(void) {
285 #if defined(__GNUC__) && __GNUC__
286 unsigned int tscp;
287 __asm__ __volatile__("rdtscp\n\t" : "=a"(tscp) :);
288 return tscp;
289 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
290 unsigned int tscp;
291 asm volatile("rdtscp\n\t" : "=a"(tscp) :);
292 return tscp;
293 #elif defined(_MSC_VER)
294 unsigned int ui;
295 return (unsigned int)__rdtscp(&ui);
296 #else
297 #if ARCH_X86_64
298 return (unsigned int)__rdtscp();
299 #else
300 __asm rdtscp;
301 #endif
302 #endif
303 }
304
x86_tsc_start(void)305 static INLINE unsigned int x86_tsc_start(void) {
306 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
307 // This call should not be removed. See function notes above.
308 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
309 // Avoid compiler warnings on unused-but-set variables.
310 (void)reg_eax;
311 (void)reg_ebx;
312 (void)reg_ecx;
313 (void)reg_edx;
314 return x86_readtsc();
315 }
316
x86_tsc_end(void)317 static INLINE unsigned int x86_tsc_end(void) {
318 uint32_t v = x86_readtscp();
319 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
320 // This call should not be removed. See function notes above.
321 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
322 // Avoid compiler warnings on unused-but-set variables.
323 (void)reg_eax;
324 (void)reg_ebx;
325 (void)reg_ecx;
326 (void)reg_edx;
327 return v;
328 }
329
330 #if defined(__GNUC__) && __GNUC__
331 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
332 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
333 #define x86_pause_hint() asm volatile("pause \n\t")
334 #else
335 #if ARCH_X86_64
336 #define x86_pause_hint() _mm_pause();
337 #else
338 #define x86_pause_hint() __asm pause
339 #endif
340 #endif
341
342 #if defined(__GNUC__) && __GNUC__
x87_set_control_word(unsigned short mode)343 static void x87_set_control_word(unsigned short mode) {
344 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
345 }
x87_get_control_word(void)346 static unsigned short x87_get_control_word(void) {
347 unsigned short mode;
348 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
349 return mode;
350 }
351 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
x87_set_control_word(unsigned short mode)352 static void x87_set_control_word(unsigned short mode) {
353 asm volatile("fldcw %0" : : "m"(*&mode));
354 }
x87_get_control_word(void)355 static unsigned short x87_get_control_word(void) {
356 unsigned short mode;
357 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
358 return mode;
359 }
360 #elif ARCH_X86_64
361 /* No fldcw intrinsics on Windows x64, punt to external asm */
362 extern void aom_winx64_fldcw(unsigned short mode);
363 extern unsigned short aom_winx64_fstcw(void);
364 #define x87_set_control_word aom_winx64_fldcw
365 #define x87_get_control_word aom_winx64_fstcw
366 #else
x87_set_control_word(unsigned short mode)367 static void x87_set_control_word(unsigned short mode) {
368 __asm { fldcw mode }
369 }
x87_get_control_word(void)370 static unsigned short x87_get_control_word(void) {
371 unsigned short mode;
372 __asm { fstcw mode }
373 return mode;
374 }
375 #endif
376
x87_set_double_precision(void)377 static INLINE unsigned int x87_set_double_precision(void) {
378 unsigned int mode = x87_get_control_word();
379 // Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1
380 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
381 // 8.1.5.2 Precision Control Field
382 // Bits 8 and 9 (0x300) of the x87 FPU Control Word ("Precision Control")
383 // determine the number of bits used in floating point calculations. To match
384 // later SSE instructions restrict x87 operations to Double Precision (0x200).
385 // Precision PC Field
386 // Single Precision (24-Bits) 00B
387 // Reserved 01B
388 // Double Precision (53-Bits) 10B
389 // Extended Precision (64-Bits) 11B
390 x87_set_control_word((mode & ~0x300) | 0x200);
391 return mode;
392 }
393
394 #ifdef __cplusplus
395 } // extern "C"
396 #endif
397
398 #endif // AOM_AOM_PORTS_X86_H_
399