/external/vixl/test/aarch32/ |
D | test-simulator-cond-rd-rn-rm-q-a32.cc | 141 struct Inputs { struct 142 uint32_t apsr; 143 uint32_t qbit; 144 uint32_t ge; 145 uint32_t rd; 146 uint32_t rn; 147 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 137 struct Inputs { struct 138 uint32_t apsr; 139 uint32_t qbit; 140 uint32_t ge; 141 uint32_t rd; 142 uint32_t rn; 143 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 149 struct Inputs { struct 150 uint32_t apsr; 151 uint32_t qbit; 152 uint32_t ge; 153 uint32_t rd; 154 uint32_t rn; 155 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-a32.cc | 195 struct Inputs { struct 196 uint32_t apsr; 197 uint32_t qbit; 198 uint32_t ge; 199 uint32_t rd; 200 uint32_t rn; 201 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 149 struct Inputs { struct 150 uint32_t apsr; 151 uint32_t qbit; 152 uint32_t ge; 153 uint32_t rd; 154 uint32_t rn; 155 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-q-t32.cc | 141 struct Inputs { struct 142 uint32_t apsr; 143 uint32_t qbit; 144 uint32_t ge; 145 uint32_t rd; 146 uint32_t rn; 147 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-t32.cc | 194 struct Inputs { struct 195 uint32_t apsr; 196 uint32_t qbit; 197 uint32_t ge; 198 uint32_t rd; 199 uint32_t rn; 200 uint32_t rm;
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D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 137 struct Inputs { struct 138 uint32_t apsr; 139 uint32_t qbit; 140 uint32_t ge; 141 uint32_t rd; 142 uint32_t rn; 143 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 159 struct Inputs { struct 160 uint32_t apsr; 161 uint32_t rd; 162 uint32_t rn; 163 uint32_t rm; 164 uint32_t rs;
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D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 139 struct Inputs { struct 140 uint32_t fpscr; 141 uint64_t rd; 142 uint64_t rn; 143 uint64_t rm;
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D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 139 struct Inputs { struct 140 uint32_t fpscr; 141 uint64_t rd; 142 uint64_t rn; 143 uint64_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 171 struct Inputs { struct 172 uint32_t apsr; 173 uint32_t rd; 174 uint32_t rn; 175 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 171 struct Inputs { struct 172 uint32_t apsr; 173 uint32_t rd; 174 uint32_t rn; 175 uint32_t rm;
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D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 139 struct Inputs { struct 140 uint32_t apsr; 141 uint32_t rd; 142 uint32_t rn; 143 uint32_t rm;
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D | test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 140 struct Inputs { struct 141 uint32_t apsr; 142 uint32_t rd; 143 uint32_t rn; 144 uint32_t rs;
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 159 struct Inputs { struct 160 uint32_t apsr; 161 uint32_t rd; 162 uint32_t rn; 163 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 159 struct Inputs { struct 160 uint32_t apsr; 161 uint32_t rd; 162 uint32_t rn; 163 uint32_t rm;
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D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 146 struct Inputs { struct 147 uint32_t apsr; 148 uint32_t rd; 149 uint32_t rn; 150 uint32_t rs;
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 159 struct Inputs { struct 160 uint32_t apsr; 161 uint32_t rd; 162 uint32_t rn; 163 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 145 struct Inputs { struct 146 uint32_t apsr; 147 uint32_t rd; 148 uint32_t rn; 149 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 145 struct Inputs { struct 146 uint32_t apsr; 147 uint32_t rd; 148 uint32_t rn; 149 uint32_t rm;
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 159 struct Inputs { struct 160 uint32_t apsr; 161 uint32_t rd; 162 uint32_t rn; 163 uint32_t rm;
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/external/clang/lib/Driver/ |
D | Action.cpp | 70 JobAction::JobAction(ActionClass Kind, const ActionList &Inputs, types::ID Type) in JobAction() 111 LinkJobAction::LinkJobAction(ActionList &Inputs, types::ID Type) in LinkJobAction() 117 LipoJobAction::LipoJobAction(ActionList &Inputs, types::ID Type) in LipoJobAction() 123 DsymutilJobAction::DsymutilJobAction(ActionList &Inputs, types::ID Type) in DsymutilJobAction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonConstPropagation.cpp | 1081 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, in getCell() 1108 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { in evaluateCMPrr() 1147 const APInt &A2, const CellMap &Inputs, bool &Result) { in evaluateCMPri() 1174 uint64_t Props2, const CellMap &Inputs, bool &Result) { in evaluateCMPrp() 1367 const CellMap &Inputs, LatticeCell &Result) { in evaluateCOPY() 1372 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDrr() 1403 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDri() 1439 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORrr() 1470 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORri() 1506 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORrr() [all …]
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/external/swiftshader/src/Device/ |
D | Context.hpp | 65 struct Inputs struct 72 inline const DescriptorSet::Array &getDescriptorSetObjects() const { return descriptorSetObjects; } in getDescriptorSetObjects() 73 inline const DescriptorSet::Bindings &getDescriptorSets() const { return descriptorSets; } in getDescriptorSets() 74 …riptorSet::DynamicOffsets &getDescriptorDynamicOffsets() const { return descriptorDynamicOffsets; } in getDescriptorDynamicOffsets() 75 inline const sw::Stream &getStream(uint32_t i) const { return stream[i]; } in getStream() 83 VertexInputBinding vertexInputBindings[MAX_VERTEX_INPUT_BINDINGS] = {}; 84 DescriptorSet::Array descriptorSetObjects = {}; 85 DescriptorSet::Bindings descriptorSets = {}; 86 DescriptorSet::DynamicOffsets descriptorDynamicOffsets = {}; 87 sw::Stream stream[sw::MAX_INTERFACE_COMPONENTS / 4];
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