1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef SOC_DEFAULT_BASE_ADDR_H 9 #define SOC_DEFAULT_BASE_ADDR_H 10 11 /* CCSR mmu_def.h */ 12 #define NXP_CCSR_ADDR 0x1000000 13 #define NXP_CCSR_SIZE 0xF000000 14 15 #define NXP_DCSR_ADDR 0x700000000 16 #define NXP_DCSR_SIZE 0x40000000 17 18 /* Flex-SPI controller address */ 19 #define NXP_FLEXSPI_ADDR 0x020C0000 20 /* Flex-SPI Flash Start address */ 21 #define NXP_FLEXSPI_FLASH_ADDR 0x20000000 22 23 /* MMU 500 soc.c*/ 24 #define NXP_SMMU_ADDR 0x05000000 25 26 #define NXP_SNVS_ADDR 0x01E90000 27 28 #define NXP_DCFG_ADDR 0x01E00000 29 #define NXP_PMU_CCSR_ADDR 0x01E30000 30 #define NXP_PMU_DCSR_ADDR 0x700123000 31 #define NXP_PMU_ADDR NXP_PMU_CCSR_ADDR 32 #define NXP_SFP_ADDR 0x01E80000 33 #define NXP_SCFG_ADDR 0x01FC0000 34 #define NXP_I2C_ADDR 0x02000000 35 #define NXP_ESDHC_ADDR 0x02140000 36 #define NXP_ESDHC2_ADDR 0x02150000 37 #define NXP_UART_ADDR 0x021C0000 38 #define NXP_UART1_ADDR 0x021D0000 39 40 #define NXP_GPIO1_ADDR 0x02300000 41 #define NXP_GPIO2_ADDR 0x02310000 42 #define NXP_GPIO3_ADDR 0x02320000 43 #define NXP_GPIO4_ADDR 0x02330000 44 45 #define NXP_WDOG1_NS_ADDR 0x02390000 46 #define NXP_WDOG2_NS_ADDR 0x023A0000 47 #define NXP_WDOG1_TZ_ADDR 0x023B0000 48 #define NXP_WDOG2_TZ_ADDR 0x023C0000 49 50 #define NXP_TIMER_STATUS_ADDR 0x023F0000 51 52 #define NXP_GICD_ADDR 0x06000000 53 #define NXP_GICR_ADDR 0x06200000 54 #define NXP_GICR_SGI_ADDR 0x06210000 55 56 #define NXP_CAAM_ADDR 0x08000000 57 58 #define NXP_TZC_ADDR 0x01100000 59 #define NXP_TZC2_ADDR 0x01110000 60 #define NXP_TZC3_ADDR 0x01120000 61 62 #define NXP_TIMER_ADDR 0x023E0000 63 64 #define NXP_RESET_ADDR 0x01E60000 65 #define NXP_SEC_REGFILE_ADDR 0x01E88000 66 #define NXP_RST_ADDR 0x01E88000 67 68 #define TPMWAKEMR0_ADDR 0x700123c50 69 #define TZPC_BLOCK_SIZE 0x1000 70 71 #define NXP_TZC_ADDR 0x01100000 72 #define NXP_TZC2_ADDR 0x01110000 73 #define NXP_TZC3_ADDR 0x01120000 74 #define NXP_TZC4_ADDR 0x01130000 75 #define NXP_DDR_ADDR 0x01080000 76 #define NXP_DDR2_ADDR 0x01090000 77 78 #define NXP_OCRAM_TZPC_ADDR 0x02200000 79 80 #define NXP_CCN_ADDR 0x04000000 81 #define NXP_CCN_HNI_ADDR 0x04080000 82 #define NXP_CCN_HN_F_0_ADDR 0x04200000 83 84 #endif /* SOC_DEFAULT_BASE_ADDR_H */ 85