Searched defs:Offset0 (Results 1 – 11 of 11) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
D | SILoadStoreOptimizer.cpp | 130 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0, in offsetsCanBeCombined() 181 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local 205 unsigned Offset0 in mergeRead2Pair() local 301 unsigned Offset0 in mergeWrite2Pair() local
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D | AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
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D | SIInstrInfo.cpp | 94 int64_t &Offset0, in areLoadsFromSameBasePtr() 231 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOpBaseRegImmOfs() local 1344 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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D | AMDGPUISelDAGToDAG.cpp | 719 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonSubtarget.cpp | 277 int64_t Offset0; in apply() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 147 int64_t &Offset0, in areLoadsFromSameBasePtr() 294 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOperandWithOffset() local 505 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() 2531 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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D | AMDGPUInstructionSelector.cpp | 1080 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
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D | AMDGPUISelDAGToDAG.cpp | 1259 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
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D | SIISelLowering.cpp | 6199 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 9847 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 13961 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
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