| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 556 __ Orn(x2, x0, Operand(x1)); in TEST() local
557 __ Orn(w3, w0, Operand(w1, LSL, 4)); in TEST() local
558 __ Orn(x4, x0, Operand(x1, LSL, 4)); in TEST() local
559 __ Orn(x5, x0, Operand(x1, LSR, 1)); in TEST() local
560 __ Orn(w6, w0, Operand(w1, ASR, 1)); in TEST() local
561 __ Orn(x7, x0, Operand(x1, ASR, 1)); in TEST() local
562 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST() local
563 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST() local
564 __ Orn(w10, w0, 0x0000ffff); in TEST() local
565 __ Orn(x11, x0, 0x0000ffff0000ffff); in TEST() local
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| D | test-assembler-neon-aarch64.cc | 6064 __ Orn(v16.V16B(), v0.V16B(), v0.V16B()); // self test in TEST() local
6065 __ Orn(v17.V16B(), v0.V16B(), v1.V16B()); // all combinations in TEST() local
6066 __ Orn(v24.V8B(), v0.V8B(), v0.V8B()); // self test in TEST() local
6067 __ Orn(v25.V8B(), v0.V8B(), v1.V8B()); // all combinations in TEST() local
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| D | test-assembler-sve-aarch64.cc | 1157 __ Orn(p5.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB()); in TEST_SVE() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 794 void MacroAssembler::Orn(const Register& rd, in Orn() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 5407 void Orn(const PRegisterWithLaneSize& pd, in Orn() function
5415 void Orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in Orn() function
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 3269 __ Orn(r0, r0, 0xffffffff); in TEST() local
3313 __ Orn(r4, r0, 0); in TEST() local
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2693 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { in Orn() function
2713 void Orn(Register rd, Register rn, const Operand& operand) { in Orn() function
2716 void Orn(FlagsUpdate flags, in Orn() function
2733 void Orn(FlagsUpdate flags, in Orn() function
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