1 // Copyright 2021 The Chromium OS Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 mod pci_bridge; 6 mod pcie_device; 7 mod pcie_host; 8 mod pcie_rp; 9 10 pub use pci_bridge::PciBridge; 11 pub use pcie_host::PcieHostRootPort; 12 pub use pcie_rp::PcieRootPort; 13 14 #[allow(dead_code)] 15 #[derive(Clone, Copy)] 16 pub enum PcieDevicePortType { 17 PcieEndpoint = 0, 18 PcieLegacyEndpoint = 1, 19 RootPort = 4, 20 UpstreamPort = 5, 21 DownstreamPort = 6, 22 Pcie2PciBridge = 7, 23 Pci2PcieBridge = 8, 24 RCIntegratedEndpoint = 9, 25 RCEventCollector = 0xa, 26 } 27 28 const PCIE_CAP_LEN: usize = 0x3C; 29 30 const PCIE_CAP_VERSION: u16 = 0x2; 31 const PCIE_TYPE_SHIFT: u16 = 0x4; 32 const PCIE_CAP_SLOT_SHIFT: u16 = 0x8; 33 const PCIE_CAP_IRQ_NUM_SHIFT: u16 = 0x9; 34 35 const PCIE_DEVCAP_RBER: u32 = 0x0000_8000; 36 const PCIE_LINK_X1: u16 = 0x10; 37 const PCIE_LINK_2_5GT: u16 = 0x01; 38 39 const PCIE_SLTCAP_ABP: u32 = 0x01; // Attention Button Present 40 const PCIE_SLTCAP_AIP: u32 = 0x08; // Attention Indicator Present 41 const PCIE_SLTCAP_PIP: u32 = 0x10; // Power Indicator Present 42 const PCIE_SLTCAP_HPS: u32 = 0x20; // Hot-Plug Surprise 43 const PCIE_SLTCAP_HPC: u32 = 0x40; // Hot-Plug Capable 44 45 const PCIE_SLTCTL_OFFSET: usize = 0x18; 46 const PCIE_SLTCTL_PIC_OFF: u16 = 0x300; 47 const PCIE_SLTCTL_AIC_OFF: u16 = 0xC0; 48 const PCIE_SLTCTL_ABPE: u16 = 0x01; 49 const PCIE_SLTCTL_PDCE: u16 = 0x08; 50 const PCIE_SLTCTL_CCIE: u16 = 0x10; 51 const PCIE_SLTCTL_HPIE: u16 = 0x20; 52 53 const PCIE_SLTSTA_OFFSET: usize = 0x1A; 54 const PCIE_SLTSTA_ABP: u16 = 0x0001; 55 const PCIE_SLTSTA_PFD: u16 = 0x0002; 56 const PCIE_SLTSTA_PDC: u16 = 0x0008; 57 const PCIE_SLTSTA_CC: u16 = 0x0010; 58 const PCIE_SLTSTA_PDS: u16 = 0x0040; 59 const PCIE_SLTSTA_DLLSC: u16 = 0x0100; 60 61 const PCIE_ROOTCTL_OFFSET: usize = 0x1C; 62 const PCIE_ROOTCTL_PME_ENABLE: u16 = 0x08; 63 64 const PCIE_ROOTSTA_OFFSET: usize = 0x20; 65 const PCIE_ROOTSTA_PME_REQ_ID_MASK: u32 = 0xFFFF; 66 const PCIE_ROOTSTA_PME_STATUS: u32 = 0x10000; 67 const PCIE_ROOTSTA_PME_PENDING: u32 = 0x20000; 68 69 const PMC_CAP_CONTROL_STATE_OFFSET: usize = 1; 70 const PMC_CAP_PME_SUPPORT_D0: u16 = 0x800; 71 const PMC_CAP_PME_SUPPORT_D3_HOT: u16 = 0x4000; 72 const PMC_CAP_PME_SUPPORT_D3_COLD: u16 = 0x8000; 73 const PMC_CAP_VERSION: u16 = 0x2; 74 const PMC_PME_STATUS: u16 = 0x8000; 75 const PMC_PME_ENABLE: u16 = 0x100; 76 const PMC_POWER_STATE_MASK: u16 = 0x3; 77 const PMC_POWER_STATE_D0: u16 = 0; 78 const PMC_POWER_STATE_D3: u16 = 0x3; 79 80 #[derive(PartialEq)] 81 pub enum PciDevicePower { 82 D0 = 0, 83 D3 = 3, 84 Unsupported = 0xFF, 85 } 86