Searched defs:ROR (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 41 ROR, ///< Bit rotate right. enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 41 ROR, ///< Bit rotate right. enumerator
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 357 ROR, enumerator
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| /external/python/cpython2/Modules/ |
| D | sha256module.c | 113 #define ROR(x, y)\ macro
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| /external/python/cpython3/Modules/ |
| D | sha256module.c | 116 #define ROR(x, y)\ macro
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 455 ROR, enumerator
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 37 ROR, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 37 ROR, enumerator
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 1051 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enumerator
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| /external/skia/src/core/ |
| D | SkVM.h | 334 enum Shift { LSL,LSR,ASR,ROR }; enumerator
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2273 ### ROR ### subsection
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3835 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1)) in visitOR() local
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 353 ROR = 0x3, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5913 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags())) in visitOR() local
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