1 /*
2 * Copyright (c) 2016, Alliance for Open Media. All rights reserved
3 *
4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10 */
11
12 #include <arm_neon.h>
13
14 #include "config/aom_config.h"
15
16 #include "aom_dsp/txfm_common.h"
17 #include "aom_dsp/arm/mem_neon.h"
18 #include "aom_dsp/arm/transpose_neon.h"
19
aom_fdct4x4_helper(const int16_t * input,int stride,int16x4_t * input_0,int16x4_t * input_1,int16x4_t * input_2,int16x4_t * input_3)20 static void aom_fdct4x4_helper(const int16_t *input, int stride,
21 int16x4_t *input_0, int16x4_t *input_1,
22 int16x4_t *input_2, int16x4_t *input_3) {
23 *input_0 = vshl_n_s16(vld1_s16(input + 0 * stride), 4);
24 *input_1 = vshl_n_s16(vld1_s16(input + 1 * stride), 4);
25 *input_2 = vshl_n_s16(vld1_s16(input + 2 * stride), 4);
26 *input_3 = vshl_n_s16(vld1_s16(input + 3 * stride), 4);
27 // If the very first value != 0, then add 1.
28 if (input[0] != 0) {
29 const int16x4_t one = vreinterpret_s16_s64(vdup_n_s64(1));
30 *input_0 = vadd_s16(*input_0, one);
31 }
32
33 for (int i = 0; i < 2; ++i) {
34 const int16x8_t input_01 = vcombine_s16(*input_0, *input_1);
35 const int16x8_t input_32 = vcombine_s16(*input_3, *input_2);
36
37 // in_0 +/- in_3, in_1 +/- in_2
38 const int16x8_t s_01 = vaddq_s16(input_01, input_32);
39 const int16x8_t s_32 = vsubq_s16(input_01, input_32);
40
41 // step_0 +/- step_1, step_2 +/- step_3
42 const int16x4_t s_0 = vget_low_s16(s_01);
43 const int16x4_t s_1 = vget_high_s16(s_01);
44 const int16x4_t s_2 = vget_high_s16(s_32);
45 const int16x4_t s_3 = vget_low_s16(s_32);
46
47 // (s_0 +/- s_1) * cospi_16_64
48 // Must expand all elements to s32. See 'needs32' comment in fwd_txfm.c.
49 const int32x4_t s_0_p_s_1 = vaddl_s16(s_0, s_1);
50 const int32x4_t s_0_m_s_1 = vsubl_s16(s_0, s_1);
51 const int32x4_t temp1 = vmulq_n_s32(s_0_p_s_1, cospi_16_64);
52 const int32x4_t temp2 = vmulq_n_s32(s_0_m_s_1, cospi_16_64);
53
54 // fdct_round_shift
55 int16x4_t out_0 = vrshrn_n_s32(temp1, DCT_CONST_BITS);
56 int16x4_t out_2 = vrshrn_n_s32(temp2, DCT_CONST_BITS);
57
58 // s_3 * cospi_8_64 + s_2 * cospi_24_64
59 // s_3 * cospi_24_64 - s_2 * cospi_8_64
60 const int32x4_t s_3_cospi_8_64 = vmull_n_s16(s_3, cospi_8_64);
61 const int32x4_t s_3_cospi_24_64 = vmull_n_s16(s_3, cospi_24_64);
62
63 const int32x4_t temp3 = vmlal_n_s16(s_3_cospi_8_64, s_2, cospi_24_64);
64 const int32x4_t temp4 = vmlsl_n_s16(s_3_cospi_24_64, s_2, cospi_8_64);
65
66 // fdct_round_shift
67 int16x4_t out_1 = vrshrn_n_s32(temp3, DCT_CONST_BITS);
68 int16x4_t out_3 = vrshrn_n_s32(temp4, DCT_CONST_BITS);
69
70 transpose_s16_4x4d(&out_0, &out_1, &out_2, &out_3);
71
72 *input_0 = out_0;
73 *input_1 = out_1;
74 *input_2 = out_2;
75 *input_3 = out_3;
76 }
77 }
78
aom_fdct4x4_neon(const int16_t * input,tran_low_t * final_output,int stride)79 void aom_fdct4x4_neon(const int16_t *input, tran_low_t *final_output,
80 int stride) {
81 // input[M * stride] * 16
82 int16x4_t input_0, input_1, input_2, input_3;
83
84 aom_fdct4x4_helper(input, stride, &input_0, &input_1, &input_2, &input_3);
85
86 // Not quite a rounding shift. Only add 1 despite shifting by 2.
87 const int16x8_t one = vdupq_n_s16(1);
88 int16x8_t out_01 = vcombine_s16(input_0, input_1);
89 int16x8_t out_23 = vcombine_s16(input_2, input_3);
90 out_01 = vshrq_n_s16(vaddq_s16(out_01, one), 2);
91 out_23 = vshrq_n_s16(vaddq_s16(out_23, one), 2);
92 store_s16q_to_tran_low(final_output + 0 * 8, out_01);
93 store_s16q_to_tran_low(final_output + 1 * 8, out_23);
94 }
95
aom_fdct4x4_lp_neon(const int16_t * input,int16_t * final_output,int stride)96 void aom_fdct4x4_lp_neon(const int16_t *input, int16_t *final_output,
97 int stride) {
98 // input[M * stride] * 16
99 int16x4_t input_0, input_1, input_2, input_3;
100
101 aom_fdct4x4_helper(input, stride, &input_0, &input_1, &input_2, &input_3);
102
103 // Not quite a rounding shift. Only add 1 despite shifting by 2.
104 const int16x8_t one = vdupq_n_s16(1);
105 int16x8_t out_01 = vcombine_s16(input_0, input_1);
106 int16x8_t out_23 = vcombine_s16(input_2, input_3);
107 out_01 = vshrq_n_s16(vaddq_s16(out_01, one), 2);
108 out_23 = vshrq_n_s16(vaddq_s16(out_23, one), 2);
109 vst1q_s16(final_output + 0 * 8, out_01);
110 vst1q_s16(final_output + 1 * 8, out_23);
111 }
112
aom_fdct8x8_neon(const int16_t * input,int16_t * final_output,int stride)113 void aom_fdct8x8_neon(const int16_t *input, int16_t *final_output, int stride) {
114 // stage 1
115 int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2);
116 int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2);
117 int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2);
118 int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2);
119 int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2);
120 int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2);
121 int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2);
122 int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2);
123 for (int i = 0; i < 2; ++i) {
124 int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
125 const int16x8_t v_s0 = vaddq_s16(input_0, input_7);
126 const int16x8_t v_s1 = vaddq_s16(input_1, input_6);
127 const int16x8_t v_s2 = vaddq_s16(input_2, input_5);
128 const int16x8_t v_s3 = vaddq_s16(input_3, input_4);
129 const int16x8_t v_s4 = vsubq_s16(input_3, input_4);
130 const int16x8_t v_s5 = vsubq_s16(input_2, input_5);
131 const int16x8_t v_s6 = vsubq_s16(input_1, input_6);
132 const int16x8_t v_s7 = vsubq_s16(input_0, input_7);
133 // fdct4(step, step);
134 int16x8_t v_x0 = vaddq_s16(v_s0, v_s3);
135 int16x8_t v_x1 = vaddq_s16(v_s1, v_s2);
136 int16x8_t v_x2 = vsubq_s16(v_s1, v_s2);
137 int16x8_t v_x3 = vsubq_s16(v_s0, v_s3);
138 // fdct4(step, step);
139 int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
140 int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
141 int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1));
142 int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1));
143 int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_24_64);
144 int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_24_64);
145 int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_24_64);
146 int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_24_64);
147 v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), (int16_t)cospi_8_64);
148 v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), (int16_t)cospi_8_64);
149 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), (int16_t)cospi_8_64);
150 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), (int16_t)cospi_8_64);
151 v_t0_lo = vmulq_n_s32(v_t0_lo, (int32_t)cospi_16_64);
152 v_t0_hi = vmulq_n_s32(v_t0_hi, (int32_t)cospi_16_64);
153 v_t1_lo = vmulq_n_s32(v_t1_lo, (int32_t)cospi_16_64);
154 v_t1_hi = vmulq_n_s32(v_t1_hi, (int32_t)cospi_16_64);
155 {
156 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
157 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
158 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
159 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
160 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
161 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
162 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
163 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
164 out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43
165 out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63
166 out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47
167 out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67
168 }
169 // Stage 2
170 v_x0 = vsubq_s16(v_s6, v_s5);
171 v_x1 = vaddq_s16(v_s6, v_s5);
172 v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), (int16_t)cospi_16_64);
173 v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), (int16_t)cospi_16_64);
174 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_16_64);
175 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_16_64);
176 {
177 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
178 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
179 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
180 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
181 const int16x8_t ab = vcombine_s16(a, b);
182 const int16x8_t cd = vcombine_s16(c, d);
183 // Stage 3
184 v_x0 = vaddq_s16(v_s4, ab);
185 v_x1 = vsubq_s16(v_s4, ab);
186 v_x2 = vsubq_s16(v_s7, cd);
187 v_x3 = vaddq_s16(v_s7, cd);
188 }
189 // Stage 4
190 v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_4_64);
191 v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_4_64);
192 v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), (int16_t)cospi_28_64);
193 v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), (int16_t)cospi_28_64);
194 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_12_64);
195 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_12_64);
196 v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), (int16_t)cospi_20_64);
197 v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), (int16_t)cospi_20_64);
198 v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_12_64);
199 v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_12_64);
200 v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), (int16_t)cospi_20_64);
201 v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), (int16_t)cospi_20_64);
202 v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_28_64);
203 v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_28_64);
204 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), (int16_t)cospi_4_64);
205 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), (int16_t)cospi_4_64);
206 {
207 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS);
208 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS);
209 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS);
210 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS);
211 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS);
212 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS);
213 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS);
214 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS);
215 out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53
216 out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73
217 out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57
218 out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77
219 }
220 // transpose 8x8
221 {
222 // 00 01 02 03 40 41 42 43
223 // 10 11 12 13 50 51 52 53
224 // 20 21 22 23 60 61 62 63
225 // 30 31 32 33 70 71 72 73
226 // 04 05 06 07 44 45 46 47
227 // 14 15 16 17 54 55 56 57
228 // 24 25 26 27 64 65 66 67
229 // 34 35 36 37 74 75 76 77
230 const int32x4x2_t r02_s32 =
231 vtrnq_s32(vreinterpretq_s32_s16(out_0), vreinterpretq_s32_s16(out_2));
232 const int32x4x2_t r13_s32 =
233 vtrnq_s32(vreinterpretq_s32_s16(out_1), vreinterpretq_s32_s16(out_3));
234 const int32x4x2_t r46_s32 =
235 vtrnq_s32(vreinterpretq_s32_s16(out_4), vreinterpretq_s32_s16(out_6));
236 const int32x4x2_t r57_s32 =
237 vtrnq_s32(vreinterpretq_s32_s16(out_5), vreinterpretq_s32_s16(out_7));
238 const int16x8x2_t r01_s16 =
239 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]),
240 vreinterpretq_s16_s32(r13_s32.val[0]));
241 const int16x8x2_t r23_s16 =
242 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]),
243 vreinterpretq_s16_s32(r13_s32.val[1]));
244 const int16x8x2_t r45_s16 =
245 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]),
246 vreinterpretq_s16_s32(r57_s32.val[0]));
247 const int16x8x2_t r67_s16 =
248 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]),
249 vreinterpretq_s16_s32(r57_s32.val[1]));
250 input_0 = r01_s16.val[0];
251 input_1 = r01_s16.val[1];
252 input_2 = r23_s16.val[0];
253 input_3 = r23_s16.val[1];
254 input_4 = r45_s16.val[0];
255 input_5 = r45_s16.val[1];
256 input_6 = r67_s16.val[0];
257 input_7 = r67_s16.val[1];
258 // 00 10 20 30 40 50 60 70
259 // 01 11 21 31 41 51 61 71
260 // 02 12 22 32 42 52 62 72
261 // 03 13 23 33 43 53 63 73
262 // 04 14 24 34 44 54 64 74
263 // 05 15 25 35 45 55 65 75
264 // 06 16 26 36 46 56 66 76
265 // 07 17 27 37 47 57 67 77
266 }
267 } // for
268 {
269 // from aom_dct_sse2.c
270 // Post-condition (division by two)
271 // division of two 16 bits signed numbers using shifts
272 // n / 2 = (n - (n >> 15)) >> 1
273 const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15);
274 const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15);
275 const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15);
276 const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15);
277 const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15);
278 const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15);
279 const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15);
280 const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15);
281 input_0 = vhsubq_s16(input_0, sign_in0);
282 input_1 = vhsubq_s16(input_1, sign_in1);
283 input_2 = vhsubq_s16(input_2, sign_in2);
284 input_3 = vhsubq_s16(input_3, sign_in3);
285 input_4 = vhsubq_s16(input_4, sign_in4);
286 input_5 = vhsubq_s16(input_5, sign_in5);
287 input_6 = vhsubq_s16(input_6, sign_in6);
288 input_7 = vhsubq_s16(input_7, sign_in7);
289 // store results
290 vst1q_s16(&final_output[0 * 8], input_0);
291 vst1q_s16(&final_output[1 * 8], input_1);
292 vst1q_s16(&final_output[2 * 8], input_2);
293 vst1q_s16(&final_output[3 * 8], input_3);
294 vst1q_s16(&final_output[4 * 8], input_4);
295 vst1q_s16(&final_output[5 * 8], input_5);
296 vst1q_s16(&final_output[6 * 8], input_6);
297 vst1q_s16(&final_output[7 * 8], input_7);
298 }
299 }
300
aom_fdct8x8_1_neon(const int16_t * input,int16_t * output,int stride)301 void aom_fdct8x8_1_neon(const int16_t *input, int16_t *output, int stride) {
302 int r;
303 int16x8_t sum = vld1q_s16(&input[0]);
304 for (r = 1; r < 8; ++r) {
305 const int16x8_t input_00 = vld1q_s16(&input[r * stride]);
306 sum = vaddq_s16(sum, input_00);
307 }
308 {
309 const int32x4_t a = vpaddlq_s16(sum);
310 const int64x2_t b = vpaddlq_s32(a);
311 const int32x2_t c = vadd_s32(vreinterpret_s32_s64(vget_low_s64(b)),
312 vreinterpret_s32_s64(vget_high_s64(b)));
313 output[0] = vget_lane_s16(vreinterpret_s16_s32(c), 0);
314 output[1] = 0;
315 }
316 }
317