1 /* 2 * Copyright (C) 2019 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _EXYNOSDEVICEINTERFACE_H 18 #define _EXYNOSDEVICEINTERFACE_H 19 20 #include "ExynosHWCHelper.h" 21 #include "ExynosDisplayInterface.h" 22 23 struct hwc_dpp_size_range { 24 uint32_t min; 25 uint32_t max; 26 uint32_t align; 27 }; 28 29 struct hwc_dpp_restriction { 30 struct hwc_dpp_size_range src_f_w; 31 struct hwc_dpp_size_range src_f_h; 32 struct hwc_dpp_size_range src_w; 33 struct hwc_dpp_size_range src_h; 34 uint32_t src_x_align; 35 uint32_t src_y_align; 36 struct hwc_dpp_size_range dst_f_w; 37 struct hwc_dpp_size_range dst_f_h; 38 struct hwc_dpp_size_range dst_w; 39 struct hwc_dpp_size_range dst_h; 40 uint32_t dst_x_align; 41 uint32_t dst_y_align; 42 struct hwc_dpp_size_range blk_w; 43 struct hwc_dpp_size_range blk_h; 44 uint32_t blk_x_align; 45 uint32_t blk_y_align; 46 uint32_t src_h_rot_max; 47 std::vector<uint32_t> formats; 48 uint32_t scale_down; 49 uint32_t scale_up; 50 }; 51 52 struct hwc_dpp_ch_restriction { 53 int id; 54 unsigned long attr; 55 struct hwc_dpp_restriction restriction; 56 }; 57 58 struct hwc_dpp_restrictions_info { 59 uint32_t ver; 60 /* dpp_chs : Normal DPP DMA Channels for window composition */ 61 std::vector<hwc_dpp_ch_restriction> dpp_chs; 62 /* spp_chs : Special DPP DMA Channels for SPP (Speicial Purpose Plane) */ 63 std::vector<hwc_dpp_ch_restriction> spp_chs; 64 uint32_t ppc = 0; 65 uint32_t max_disp_freq = 0; 66 }; 67 68 /* for restriction query */ 69 typedef struct dpu_dpp_info { 70 struct hwc_dpp_restrictions_info dpuInfo; 71 bool overlap[16] = {false, }; 72 } dpu_dpp_info_t; 73 74 class ExynosDevice; 75 class ExynosDeviceInterface { 76 protected: 77 ExynosDevice *mExynosDevice = NULL; 78 bool mUseQuery = false; 79 // Gathered DPU resctrictions 80 dpu_dpp_info_t mDPUInfo; 81 public: ~ExynosDeviceInterface()82 virtual ~ExynosDeviceInterface(){}; 83 virtual void init(ExynosDevice *exynosDevice) = 0; initDisplayInterface(std::unique_ptr<ExynosDisplayInterface> & dispInterface)84 virtual int32_t initDisplayInterface( 85 std::unique_ptr<ExynosDisplayInterface> &dispInterface) 86 { return 0;}; 87 /* Fill mDPUInfo according to interface type */ 88 virtual void updateRestrictions() = 0; getUseQuery()89 virtual bool getUseQuery() { return mUseQuery; }; 90 getNumDPPChs()91 uint32_t getNumDPPChs() { return mDPUInfo.dpuInfo.dpp_chs.size(); }; getNumSPPChs()92 uint32_t getNumSPPChs() { return mDPUInfo.dpuInfo.spp_chs.size(); }; getSPPChId(uint32_t index)93 uint32_t getSPPChId(uint32_t index) { return mDPUInfo.dpuInfo.spp_chs.at(index).id; }; getSPPChAttr(uint32_t index)94 uint64_t getSPPChAttr(uint32_t index) { return mDPUInfo.dpuInfo.spp_chs.at(index).attr; }; 95 getExynosDevice()96 ExynosDevice* getExynosDevice() {return mExynosDevice;}; 97 protected: 98 /* Make dpu restrictions using mDPUInfo */ 99 int32_t makeDPURestrictions(); 100 /* Update feature table using mDPUInfo */ 101 int32_t updateFeatureTable(); 102 /* Print restriction */ 103 void printDppRestriction(struct hwc_dpp_ch_restriction res); 104 public: 105 uint32_t mType = INTERFACE_TYPE_NONE; 106 }; 107 #endif //_EXYNOSDEVICEINTERFACE_H 108