1 /*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <drivers/arm/cci.h>
11 #include <drivers/arm/ccn.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/arm/sp804_delay_timer.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <lib/mmio.h>
16 #include <lib/smccc.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <platform_def.h>
19 #include <services/arm_arch_svc.h>
20 #if SPM_MM
21 #include <services/spm_mm_partition.h>
22 #endif
23
24 #include <plat/arm/common/arm_config.h>
25 #include <plat/arm/common/plat_arm.h>
26 #include <plat/common/platform.h>
27
28 #include "fvp_private.h"
29
30 /* Defines for GIC Driver build time selection */
31 #define FVP_GICV2 1
32 #define FVP_GICV3 2
33
34 /*******************************************************************************
35 * arm_config holds the characteristics of the differences between the three FVP
36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
37 * at each boot stage by the primary before enabling the MMU (to allow
38 * interconnect configuration) & used thereafter. Each BL will have its own copy
39 * to allow independent operation.
40 ******************************************************************************/
41 arm_config_t arm_config;
42
43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
44 DEVICE0_SIZE, \
45 MT_DEVICE | MT_RW | MT_SECURE)
46
47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
48 DEVICE1_SIZE, \
49 MT_DEVICE | MT_RW | MT_SECURE)
50
51 #if FVP_GICR_REGION_PROTECTION
52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
53 BASE_GICD_SIZE, \
54 MT_DEVICE | MT_RW | MT_SECURE)
55
56 /* Map all core's redistributor memory as read-only. After boots up,
57 * per-core map its redistributor memory as read-write */
58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
60 MT_DEVICE | MT_RO | MT_SECURE)
61 #endif /* FVP_GICR_REGION_PROTECTION */
62
63 /*
64 * Need to be mapped with write permissions in order to set a new non-volatile
65 * counter value.
66 */
67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
68 DEVICE2_SIZE, \
69 MT_DEVICE | MT_RW | MT_SECURE)
70
71 /*
72 * Table of memory regions for various BL stages to map using the MMU.
73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
74 * of mapping it.
75 */
76 #ifdef IMAGE_BL1
77 const mmap_region_t plat_arm_mmap[] = {
78 ARM_MAP_SHARED_RAM,
79 V2M_MAP_FLASH0_RO,
80 V2M_MAP_IOFPGA,
81 MAP_DEVICE0,
82 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
83 MAP_DEVICE1,
84 #endif
85 #if TRUSTED_BOARD_BOOT
86 /* To access the Root of Trust Public Key registers. */
87 MAP_DEVICE2,
88 /* Map DRAM to authenticate NS_BL2U image. */
89 ARM_MAP_NS_DRAM1,
90 #endif
91 {0}
92 };
93 #endif
94 #ifdef IMAGE_BL2
95 const mmap_region_t plat_arm_mmap[] = {
96 ARM_MAP_SHARED_RAM,
97 V2M_MAP_FLASH0_RW,
98 V2M_MAP_IOFPGA,
99 MAP_DEVICE0,
100 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
101 MAP_DEVICE1,
102 #endif
103 ARM_MAP_NS_DRAM1,
104 #ifdef __aarch64__
105 ARM_MAP_DRAM2,
106 #endif
107 #if defined(SPD_spmd)
108 ARM_MAP_TRUSTED_DRAM,
109 #endif
110 #ifdef SPD_tspd
111 ARM_MAP_TSP_SEC_MEM,
112 #endif
113 #if TRUSTED_BOARD_BOOT
114 /* To access the Root of Trust Public Key registers. */
115 MAP_DEVICE2,
116 #if !BL2_AT_EL3
117 ARM_MAP_BL1_RW,
118 #endif
119 #endif /* TRUSTED_BOARD_BOOT */
120 #if SPM_MM
121 ARM_SP_IMAGE_MMAP,
122 #endif
123 #if ARM_BL31_IN_DRAM
124 ARM_MAP_BL31_SEC_DRAM,
125 #endif
126 #ifdef SPD_opteed
127 ARM_MAP_OPTEE_CORE_MEM,
128 ARM_OPTEE_PAGEABLE_LOAD_MEM,
129 #endif
130 {0}
131 };
132 #endif
133 #ifdef IMAGE_BL2U
134 const mmap_region_t plat_arm_mmap[] = {
135 MAP_DEVICE0,
136 V2M_MAP_IOFPGA,
137 {0}
138 };
139 #endif
140 #ifdef IMAGE_BL31
141 const mmap_region_t plat_arm_mmap[] = {
142 ARM_MAP_SHARED_RAM,
143 #if USE_DEBUGFS
144 /* Required by devfip, can be removed if devfip is not used */
145 V2M_MAP_FLASH0_RW,
146 #endif /* USE_DEBUGFS */
147 ARM_MAP_EL3_TZC_DRAM,
148 V2M_MAP_IOFPGA,
149 MAP_DEVICE0,
150 #if FVP_GICR_REGION_PROTECTION
151 MAP_GICD_MEM,
152 MAP_GICR_MEM,
153 #else
154 MAP_DEVICE1,
155 #endif /* FVP_GICR_REGION_PROTECTION */
156 ARM_V2M_MAP_MEM_PROTECT,
157 #if SPM_MM
158 ARM_SPM_BUF_EL3_MMAP,
159 #endif
160 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
161 ARM_DTB_DRAM_NS,
162 {0}
163 };
164
165 #if defined(IMAGE_BL31) && SPM_MM
166 const mmap_region_t plat_arm_secure_partition_mmap[] = {
167 V2M_MAP_IOFPGA_EL0, /* for the UART */
168 MAP_REGION_FLAT(DEVICE0_BASE, \
169 DEVICE0_SIZE, \
170 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
171 ARM_SP_IMAGE_MMAP,
172 ARM_SP_IMAGE_NS_BUF_MMAP,
173 ARM_SP_IMAGE_RW_MMAP,
174 ARM_SPM_BUF_EL0_MMAP,
175 {0}
176 };
177 #endif
178 #endif
179 #ifdef IMAGE_BL32
180 const mmap_region_t plat_arm_mmap[] = {
181 #ifndef __aarch64__
182 ARM_MAP_SHARED_RAM,
183 ARM_V2M_MAP_MEM_PROTECT,
184 #endif
185 V2M_MAP_IOFPGA,
186 MAP_DEVICE0,
187 MAP_DEVICE1,
188 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
189 ARM_DTB_DRAM_NS,
190 {0}
191 };
192 #endif
193
194 ARM_CASSERT_MMAP
195
196 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
197 static const int fvp_cci400_map[] = {
198 PLAT_FVP_CCI400_CLUS0_SL_PORT,
199 PLAT_FVP_CCI400_CLUS1_SL_PORT,
200 };
201
202 static const int fvp_cci5xx_map[] = {
203 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
204 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
205 };
206
get_interconnect_master(void)207 static unsigned int get_interconnect_master(void)
208 {
209 unsigned int master;
210 u_register_t mpidr;
211
212 mpidr = read_mpidr_el1();
213 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
214 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
215
216 assert(master < FVP_CLUSTER_COUNT);
217 return master;
218 }
219 #endif
220
221 #if defined(IMAGE_BL31) && SPM_MM
222 /*
223 * Boot information passed to a secure partition during initialisation. Linear
224 * indices in MP information will be filled at runtime.
225 */
226 static spm_mm_mp_info_t sp_mp_info[] = {
227 [0] = {0x80000000, 0},
228 [1] = {0x80000001, 0},
229 [2] = {0x80000002, 0},
230 [3] = {0x80000003, 0},
231 [4] = {0x80000100, 0},
232 [5] = {0x80000101, 0},
233 [6] = {0x80000102, 0},
234 [7] = {0x80000103, 0},
235 };
236
237 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
238 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
239 .h.version = VERSION_1,
240 .h.size = sizeof(spm_mm_boot_info_t),
241 .h.attr = 0,
242 .sp_mem_base = ARM_SP_IMAGE_BASE,
243 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
244 .sp_image_base = ARM_SP_IMAGE_BASE,
245 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
246 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
247 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
248 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
249 .sp_image_size = ARM_SP_IMAGE_SIZE,
250 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
251 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
252 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
253 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
254 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
255 .num_cpus = PLATFORM_CORE_COUNT,
256 .mp_info = &sp_mp_info[0],
257 };
258
plat_get_secure_partition_mmap(void * cookie)259 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
260 {
261 return plat_arm_secure_partition_mmap;
262 }
263
plat_get_secure_partition_boot_info(void * cookie)264 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
265 void *cookie)
266 {
267 return &plat_arm_secure_partition_boot_info;
268 }
269 #endif
270
271 /*******************************************************************************
272 * A single boot loader stack is expected to work on both the Foundation FVP
273 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
274 * SYS_ID register provides a mechanism for detecting the differences between
275 * these platforms. This information is stored in a per-BL array to allow the
276 * code to take the correct path.Per BL platform configuration.
277 ******************************************************************************/
fvp_config_setup(void)278 void __init fvp_config_setup(void)
279 {
280 unsigned int rev, hbi, bld, arch, sys_id;
281
282 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
283 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
284 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
285 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
286 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
287
288 if (arch != ARCH_MODEL) {
289 ERROR("This firmware is for FVP models\n");
290 panic();
291 }
292
293 /*
294 * The build field in the SYS_ID tells which variant of the GIC
295 * memory is implemented by the model.
296 */
297 switch (bld) {
298 case BLD_GIC_VE_MMAP:
299 ERROR("Legacy Versatile Express memory map for GIC peripheral"
300 " is not supported\n");
301 panic();
302 break;
303 case BLD_GIC_A53A57_MMAP:
304 break;
305 default:
306 ERROR("Unsupported board build %x\n", bld);
307 panic();
308 }
309
310 /*
311 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
312 * for the Foundation FVP.
313 */
314 switch (hbi) {
315 case HBI_FOUNDATION_FVP:
316 arm_config.flags = 0;
317
318 /*
319 * Check for supported revisions of Foundation FVP
320 * Allow future revisions to run but emit warning diagnostic
321 */
322 switch (rev) {
323 case REV_FOUNDATION_FVP_V2_0:
324 case REV_FOUNDATION_FVP_V2_1:
325 case REV_FOUNDATION_FVP_v9_1:
326 case REV_FOUNDATION_FVP_v9_6:
327 break;
328 default:
329 WARN("Unrecognized Foundation FVP revision %x\n", rev);
330 break;
331 }
332 break;
333 case HBI_BASE_FVP:
334 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
335
336 /*
337 * Check for supported revisions
338 * Allow future revisions to run but emit warning diagnostic
339 */
340 switch (rev) {
341 case REV_BASE_FVP_V0:
342 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
343 break;
344 case REV_BASE_FVP_REVC:
345 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
346 ARM_CONFIG_FVP_HAS_CCI5XX);
347 break;
348 default:
349 WARN("Unrecognized Base FVP revision %x\n", rev);
350 break;
351 }
352 break;
353 default:
354 ERROR("Unsupported board HBI number 0x%x\n", hbi);
355 panic();
356 }
357
358 /*
359 * We assume that the presence of MT bit, and therefore shifted
360 * affinities, is uniform across the platform: either all CPUs, or no
361 * CPUs implement it.
362 */
363 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
364 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
365 }
366
367
fvp_interconnect_init(void)368 void __init fvp_interconnect_init(void)
369 {
370 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
371 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
372 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
373 panic();
374 }
375
376 plat_arm_interconnect_init();
377 #else
378 uintptr_t cci_base = 0U;
379 const int *cci_map = NULL;
380 unsigned int map_size = 0U;
381
382 /* Initialize the right interconnect */
383 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
384 cci_base = PLAT_FVP_CCI5XX_BASE;
385 cci_map = fvp_cci5xx_map;
386 map_size = ARRAY_SIZE(fvp_cci5xx_map);
387 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
388 cci_base = PLAT_FVP_CCI400_BASE;
389 cci_map = fvp_cci400_map;
390 map_size = ARRAY_SIZE(fvp_cci400_map);
391 } else {
392 return;
393 }
394
395 assert(cci_base != 0U);
396 assert(cci_map != NULL);
397 cci_init(cci_base, cci_map, map_size);
398 #endif
399 }
400
fvp_interconnect_enable(void)401 void fvp_interconnect_enable(void)
402 {
403 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
404 plat_arm_interconnect_enter_coherency();
405 #else
406 unsigned int master;
407
408 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
409 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
410 master = get_interconnect_master();
411 cci_enable_snoop_dvm_reqs(master);
412 }
413 #endif
414 }
415
fvp_interconnect_disable(void)416 void fvp_interconnect_disable(void)
417 {
418 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
419 plat_arm_interconnect_exit_coherency();
420 #else
421 unsigned int master;
422
423 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
424 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
425 master = get_interconnect_master();
426 cci_disable_snoop_dvm_reqs(master);
427 }
428 #endif
429 }
430
431 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)432 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
433 {
434 assert(heap_addr != NULL);
435 assert(heap_size != NULL);
436
437 return arm_get_mbedtls_heap(heap_addr, heap_size);
438 }
439 #endif
440
fvp_timer_init(void)441 void fvp_timer_init(void)
442 {
443 #if USE_SP804_TIMER
444 /* Enable the clock override for SP804 timer 0, which means that no
445 * clock dividers are applied and the raw (35MHz) clock will be used.
446 */
447 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
448
449 /* Initialize delay timer driver using SP804 dual timer 0 */
450 sp804_timer_init(V2M_SP804_TIMER0_BASE,
451 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
452 #else
453 generic_delay_timer_init();
454
455 /* Enable System level generic timer */
456 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
457 CNTCR_FCREQ(0U) | CNTCR_EN);
458 #endif /* USE_SP804_TIMER */
459 }
460
461 /*****************************************************************************
462 * plat_is_smccc_feature_available() - This function checks whether SMCCC
463 * feature is availabile for platform.
464 * @fid: SMCCC function id
465 *
466 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
467 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
468 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)469 int32_t plat_is_smccc_feature_available(u_register_t fid)
470 {
471 switch (fid) {
472 case SMCCC_ARCH_SOC_ID:
473 return SMC_ARCH_CALL_SUCCESS;
474 default:
475 return SMC_ARCH_CALL_NOT_SUPPORTED;
476 }
477 }
478
479 /* Get SOC version */
plat_get_soc_version(void)480 int32_t plat_get_soc_version(void)
481 {
482 return (int32_t)
483 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
484 ARM_SOC_IDENTIFICATION_CODE) |
485 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
486 }
487
488 /* Get SOC revision */
plat_get_soc_revision(void)489 int32_t plat_get_soc_revision(void)
490 {
491 unsigned int sys_id;
492
493 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
494 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
495 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
496 }
497