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Searched defs:ldr (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/MC/AArch64/
Darm64-memory.s14 ldr d8, [sp, #8] define
216 ldr d8, [x0, #8]! define
259 ldr d8, [x0], #8 define
412 ldr d1, [x1, x2] define
413 ldr d1, [x1, x2, lsl #3] define
557 ldr d4, [x6, #4] define
558 ldr d4, [x7, #-8] define
Dbasic-a64-diagnostics.s2093 ldr d3, [x3], #256 define
2094 ldr d3, [x13], #-257 define
2268 ldr d3, [x3, #256]! define
2269 ldr d3, [x13, #-257]! define
2489 ldr d3, [x20, wzr, uxtw #4] define
Darm64-diags.s79 ldr w1, [x3, w3, sxtw #4] label
80 ldr x1, [x3, w3, sxtw #4] label
81 ldr b1, [x3, w3, sxtw #4] label
82 ldr h1, [x3, w3, sxtw #4] label
83 ldr s1, [x3, w3, sxtw #4] label
84 ldr d1, [x3, w3, sxtw #4] define
85 ldr q1, [x3, w3, sxtw #1] label
Dinline-asm-modifiers.s129 ldr d0, [sp] define
144 ldr d0, [sp] define
Dbasic-a64-instructions.s2230 ldr d0, i_dont define
2524 ldr d3, [x10, #32760] define
/external/vixl/benchmarks/aarch32/
Dasm-disasm-speed-test.cc204 __ ldr(Narrow, r6, MemOperand(r7)); in Generate_1() local
208 __ ldr(Narrow, r2, &l_00a8); in Generate_1() local
249 __ ldr(Narrow, r2, MemOperand(r1, 28)); in Generate_1() local
268 __ ldr(Narrow, r3, &l_00ac); in Generate_1() local
288 __ ldr(Narrow, r4, MemOperand(r0)); in Generate_1() local
291 __ ldr(Narrow, r1, MemOperand(r0, 4)); in Generate_1() local
295 __ ldr(Narrow, r3, MemOperand(sp, 40)); in Generate_1() local
298 __ ldr(Narrow, r3, MemOperand(r4, 4)); in Generate_1() local
303 __ ldr(Narrow, r3, MemOperand(r4)); in Generate_1() local
309 __ ldr(r2, MemOperand(r3, 24, PostIndex)); in Generate_1() local
[all …]
/external/libffi/src/aarch64/
Dwin64_armasm.S266 ldr d3, [x3, #24] /* D4 */ define
268 ldr d2, [x3, #16] /* D3 */ define
272 ldr d0, [x3] /* D1 */ define
/external/rust/crates/quiche/deps/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S54 ldr r4,=0 label
55 ldr r5,=254 label
73 ldr r7,=960 label
1569 ldr r2,[sp,#488] label
1570 ldr r4,[sp,#492] label
1581 ldr r1,=0 label
1584 ldr r4,=0 label
1585 ldr r5,=2 label
2033 ldr r2,[r1],#4 label
2034 ldr r3,[r1],#4 label
[all …]
/external/rust/crates/ring/crypto/curve25519/asm/
Dx25519-asm-arm.S56 ldr r4,=0 label
57 ldr r5,=254 label
75 ldr r7,=960 label
1571 ldr r2,[sp,#488] label
1572 ldr r4,[sp,#492] label
1583 ldr r1,=0 label
1586 ldr r4,=0 label
1587 ldr r5,=2 label
2035 ldr r2,[r1],#4 label
2036 ldr r3,[r1],#4 label
[all …]
/external/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S54 ldr r4,=0 label
55 ldr r5,=254 label
73 ldr r7,=960 label
1569 ldr r2,[sp,#488] label
1570 ldr r4,[sp,#492] label
1581 ldr r1,=0 label
1584 ldr r4,=0 label
1585 ldr r5,=2 label
2033 ldr r2,[r1],#4 label
2034 ldr r3,[r1],#4 label
[all …]
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_aarch64.S128 ldr d8, [x7, #MARL_REG_v8] define
129 ldr d9, [x7, #MARL_REG_v9] define
/external/XNNPACK/src/jit/
Daarch64-assembler.cc271 void Assembler::ldr(XRegister xt, MemOperand xn) { in ldr() function in xnnpack::aarch64::Assembler
281 void Assembler::ldr(XRegister xt, MemOperand xn, int32_t imm) { in ldr() function in xnnpack::aarch64::Assembler
462 void Assembler::ldr(DRegister dt, MemOperand xn, int32_t imm) { in ldr() function in xnnpack::aarch64::Assembler
466 void Assembler::ldr(QRegister qt, MemOperand xn, int32_t imm) { in ldr() function in xnnpack::aarch64::Assembler
470 void Assembler::ldr(SRegister st, MemOperand xn, int32_t imm) { in ldr() function in xnnpack::aarch64::Assembler
617 void Assembler::ldr(uint32_t size, uint32_t opc, MemOperand xn, int32_t imm, uint8_t rt_code) { in ldr() function in xnnpack::aarch64::Assembler
Daarch32-assembler.cc164 void Assembler::ldr(CoreRegister rt, MemOperand op, int32_t offset) { in ldr() function in xnnpack::aarch32::Assembler
168 void Assembler::ldr(CoreRegister rt, MemOperand op) { in ldr() function in xnnpack::aarch32::Assembler
/external/clang/test/CXX/expr/
Dp9.cpp7 long double &ldr = ld0; variable
/external/lmfit/lib/
Dlmmin.c553 void lm_lmpar(const int n, double* r, const int ldr, const int* Pivot, in lm_lmpar()
900 void lm_qrsolv(const int n, double* r, const int ldr, const int* Pivot, in lm_qrsolv()
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc3981 __ ldr(x2, &before_x); in TEST() local
3982 __ ldr(w3, &before_w); in TEST() local
3984 __ ldr(q11, &before_q); in TEST() local
3985 __ ldr(d13, &before_d); in TEST() local
3986 __ ldr(s25, &before_s); in TEST() local
3988 __ ldr(x6, &after_x); in TEST() local
3989 __ ldr(w7, &after_w); in TEST() local
3991 __ ldr(q18, &after_q); in TEST() local
3992 __ ldr(d14, &after_d); in TEST() local
3993 __ ldr(s26, &after_s); in TEST() local
[all …]
Dtest-trace-aarch64.cc179 __ ldr(w29, MemOperand(x0)); in GenerateTestSequenceBase() local
180 __ ldr(w29, MemOperand(x1, 4, PostIndex)); in GenerateTestSequenceBase() local
181 __ ldr(w29, MemOperand(x1, 4, PreIndex)); in GenerateTestSequenceBase() local
182 __ ldr(x2, MemOperand(x0)); in GenerateTestSequenceBase() local
183 __ ldr(x2, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase() local
184 __ ldr(x2, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase() local
2755 __ ldr(p8.VnD(), SVEMemOperand(x0, 11, SVE_MUL_VL)); in GenerateTestSequenceSVE() local
2756 __ ldr(p9.VnS(), SVEMemOperand(x0, 11, SVE_MUL_VL)); in GenerateTestSequenceSVE() local
2757 __ ldr(p10.VnH(), SVEMemOperand(x0, 11, SVE_MUL_VL)); in GenerateTestSequenceSVE() local
2758 __ ldr(p11.VnB(), SVEMemOperand(x0, 11, SVE_MUL_VL)); in GenerateTestSequenceSVE() local
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.h215 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, in ldr() function
DIceAssemblerARM32.cpp1547 void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress, in ldr() function in Ice::ARM32::AssemblerARM32
/external/vixl/src/aarch64/
Dassembler-aarch64.cc119 Instruction* ldr = GetBuffer()->GetOffsetAddress<Instruction*>(offset); in place() local
1242 void Assembler::ldr(const CPURegister& rt, in ldr() function in vixl::aarch64::Assembler
1371 void Assembler::ldr(const CPURegister& rt, RawLiteral* literal) { in ldr() function in vixl::aarch64::Assembler
1383 void Assembler::ldr(const CPURegister& rt, int64_t imm19) { in ldr() function in vixl::aarch64::Assembler
Dassembler-sve-aarch64.cc4206 void Assembler::ldr(const CPURegister& rt, const SVEMemOperand& addr) { in ldr() function in vixl::aarch64::Assembler
/external/vixl/src/aarch32/
Dassembler-aarch32.h2399 void ldr(Register rt, const MemOperand& operand) { in ldr() function
2402 void ldr(Condition cond, Register rt, const MemOperand& operand) { in ldr() function
2405 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { in ldr() function
2415 void ldr(Register rt, Location* location) { ldr(al, Best, rt, location); } in ldr() function
2416 void ldr(Condition cond, Register rt, Location* location) { in ldr() function
2419 void ldr(EncodingSize size, Register rt, Location* location) { in ldr() function
Dassembler-aarch32.cc4995 void Assembler::ldr(Condition cond, in ldr() function in vixl::aarch32::Assembler
5190 void Assembler::ldr(Condition cond, in ldr() function in vixl::aarch32::Assembler
Ddisasm-aarch32.cc1704 void Disassembler::ldr(Condition cond, in ldr() function in vixl::aarch32::Disassembler
1713 void Disassembler::ldr(Condition cond, in ldr() function in vixl::aarch32::Disassembler