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Searched defs:out_reg (Results 1 – 12 of 12) sorted by relevance

/art/tools/dexanalyze/
Ddexanalyze_bytecode.cc266 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
296 uint32_t out_reg = is_jumbo ? inst->VRegA_31c() : inst->VRegA_21c(); in ProcessCodeItem() local
324 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
440 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
454 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
469 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
/art/compiler/optimizing/
Dcode_generator_arm_vixl.cc4704 vixl32::Register out_reg = OutputRegister(rem); in VisitRem() local
5012 vixl32::Register out_reg = RegisterFrom(locations->Out()); in VisitAbs() local
5281 vixl32::Register out_reg = OutputRegister(op); in HandleShift() local
8485 vixl32::Register out_reg = RegisterFrom(out); in VisitBitwiseNegatedRight() local
8703 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
8737 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
8774 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadOneRegister() local
8808 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadTwoRegisters() local
Dcode_generator_arm64.cc6048 Register out_reg = OutputRegister(abs); in VisitAbs() local
6056 VRegister out_reg = OutputFPRegister(abs); in VisitAbs() local
6463 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadOneRegister() local
6503 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadTwoRegisters() local
Dcode_generator_x86_64.cc7427 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadOneRegister() local
7460 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
Dcode_generator_x86.cc8189 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
8222 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
Dintrinsics_arm_vixl.cc427 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat() local
Dintrinsics_arm64.cc565 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); in GenMathRound() local
/art/compiler/utils/x86_64/
Djni_macro_assembler_x86_64.cc590 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in CreateJObject() local
/art/compiler/utils/x86/
Djni_macro_assembler_x86.cc514 X86ManagedRegister out_reg = mout_reg.AsX86(); in CreateJObject() local
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc842 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in CreateJObject() local
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc933 vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm()); in CreateJObject() local
/art/oatdump/
Doatdump.cc1436 for (size_t out_reg = 0; out_reg < num_outs; out_reg++) { in DumpVregLocations() local