1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _USR_IDXD_H_ 4 #define _USR_IDXD_H_ 5 6 #ifdef __KERNEL__ 7 #include <linux/types.h> 8 #else 9 #include <stdint.h> 10 #endif 11 12 /* Driver command error status */ 13 enum idxd_scmd_stat { 14 IDXD_SCMD_DEV_ENABLED = 0x80000010, 15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16 IDXD_SCMD_WQ_ENABLED = 0x80000021, 17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24 IDXD_SCMD_PERCPU_ERR = 0x80090000, 25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26 IDXD_SCMD_CDEV_ERR = 0x800b0000, 27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 }; 33 34 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 35 #define IDXD_SCMD_SOFTERR_SHIFT 16 36 37 /* Descriptor flags */ 38 #define IDXD_OP_FLAG_FENCE 0x0001 39 #define IDXD_OP_FLAG_BOF 0x0002 40 #define IDXD_OP_FLAG_CRAV 0x0004 41 #define IDXD_OP_FLAG_RCR 0x0008 42 #define IDXD_OP_FLAG_RCI 0x0010 43 #define IDXD_OP_FLAG_CRSTS 0x0020 44 #define IDXD_OP_FLAG_CR 0x0080 45 #define IDXD_OP_FLAG_CC 0x0100 46 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 47 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 48 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 49 #define IDXD_OP_FLAG_CR_TCS 0x1000 50 #define IDXD_OP_FLAG_STORD 0x2000 51 #define IDXD_OP_FLAG_DRDBK 0x4000 52 #define IDXD_OP_FLAG_DSTS 0x8000 53 54 /* IAX */ 55 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 56 57 /* Opcode */ 58 enum dsa_opcode { 59 DSA_OPCODE_NOOP = 0, 60 DSA_OPCODE_BATCH, 61 DSA_OPCODE_DRAIN, 62 DSA_OPCODE_MEMMOVE, 63 DSA_OPCODE_MEMFILL, 64 DSA_OPCODE_COMPARE, 65 DSA_OPCODE_COMPVAL, 66 DSA_OPCODE_CR_DELTA, 67 DSA_OPCODE_AP_DELTA, 68 DSA_OPCODE_DUALCAST, 69 DSA_OPCODE_CRCGEN = 0x10, 70 DSA_OPCODE_COPY_CRC, 71 DSA_OPCODE_DIF_CHECK, 72 DSA_OPCODE_DIF_INS, 73 DSA_OPCODE_DIF_STRP, 74 DSA_OPCODE_DIF_UPDT, 75 DSA_OPCODE_CFLUSH = 0x20, 76 }; 77 78 enum iax_opcode { 79 IAX_OPCODE_NOOP = 0, 80 IAX_OPCODE_DRAIN = 2, 81 IAX_OPCODE_MEMMOVE, 82 IAX_OPCODE_DECOMPRESS = 0x42, 83 IAX_OPCODE_COMPRESS, 84 }; 85 86 /* Completion record status */ 87 enum dsa_completion_status { 88 DSA_COMP_NONE = 0, 89 DSA_COMP_SUCCESS, 90 DSA_COMP_SUCCESS_PRED, 91 DSA_COMP_PAGE_FAULT_NOBOF, 92 DSA_COMP_PAGE_FAULT_IR, 93 DSA_COMP_BATCH_FAIL, 94 DSA_COMP_BATCH_PAGE_FAULT, 95 DSA_COMP_DR_OFFSET_NOINC, 96 DSA_COMP_DR_OFFSET_ERANGE, 97 DSA_COMP_DIF_ERR, 98 DSA_COMP_BAD_OPCODE = 0x10, 99 DSA_COMP_INVALID_FLAGS, 100 DSA_COMP_NOZERO_RESERVE, 101 DSA_COMP_XFER_ERANGE, 102 DSA_COMP_DESC_CNT_ERANGE, 103 DSA_COMP_DR_ERANGE, 104 DSA_COMP_OVERLAP_BUFFERS, 105 DSA_COMP_DCAST_ERR, 106 DSA_COMP_DESCLIST_ALIGN, 107 DSA_COMP_INT_HANDLE_INVAL, 108 DSA_COMP_CRA_XLAT, 109 DSA_COMP_CRA_ALIGN, 110 DSA_COMP_ADDR_ALIGN, 111 DSA_COMP_PRIV_BAD, 112 DSA_COMP_TRAFFIC_CLASS_CONF, 113 DSA_COMP_PFAULT_RDBA, 114 DSA_COMP_HW_ERR1, 115 DSA_COMP_HW_ERR_DRB, 116 DSA_COMP_TRANSLATION_FAIL, 117 }; 118 119 enum iax_completion_status { 120 IAX_COMP_NONE = 0, 121 IAX_COMP_SUCCESS, 122 IAX_COMP_PAGE_FAULT_IR = 0x04, 123 IAX_COMP_OUTBUF_OVERFLOW, 124 IAX_COMP_BAD_OPCODE = 0x10, 125 IAX_COMP_INVALID_FLAGS, 126 IAX_COMP_NOZERO_RESERVE, 127 IAX_COMP_INVALID_SIZE, 128 IAX_COMP_OVERLAP_BUFFERS = 0x16, 129 IAX_COMP_INT_HANDLE_INVAL = 0x19, 130 IAX_COMP_CRA_XLAT, 131 IAX_COMP_CRA_ALIGN, 132 IAX_COMP_ADDR_ALIGN, 133 IAX_COMP_PRIV_BAD, 134 IAX_COMP_TRAFFIC_CLASS_CONF, 135 IAX_COMP_PFAULT_RDBA, 136 IAX_COMP_HW_ERR1, 137 IAX_COMP_HW_ERR_DRB, 138 IAX_COMP_TRANSLATION_FAIL, 139 IAX_COMP_PRS_TIMEOUT, 140 IAX_COMP_WATCHDOG, 141 IAX_COMP_INVALID_COMP_FLAG = 0x30, 142 IAX_COMP_INVALID_FILTER_FLAG, 143 IAX_COMP_INVALID_NUM_ELEMS = 0x33, 144 }; 145 146 #define DSA_COMP_STATUS_MASK 0x7f 147 #define DSA_COMP_STATUS_WRITE 0x80 148 149 struct dsa_hw_desc { 150 uint32_t pasid:20; 151 uint32_t rsvd:11; 152 uint32_t priv:1; 153 uint32_t flags:24; 154 uint32_t opcode:8; 155 uint64_t completion_addr; 156 union { 157 uint64_t src_addr; 158 uint64_t rdback_addr; 159 uint64_t pattern; 160 uint64_t desc_list_addr; 161 }; 162 union { 163 uint64_t dst_addr; 164 uint64_t rdback_addr2; 165 uint64_t src2_addr; 166 uint64_t comp_pattern; 167 }; 168 union { 169 uint32_t xfer_size; 170 uint32_t desc_count; 171 }; 172 uint16_t int_handle; 173 uint16_t rsvd1; 174 union { 175 uint8_t expected_res; 176 /* create delta record */ 177 struct { 178 uint64_t delta_addr; 179 uint32_t max_delta_size; 180 uint32_t delt_rsvd; 181 uint8_t expected_res_mask; 182 }; 183 uint32_t delta_rec_size; 184 uint64_t dest2; 185 /* CRC */ 186 struct { 187 uint32_t crc_seed; 188 uint32_t crc_rsvd; 189 uint64_t seed_addr; 190 }; 191 /* DIF check or strip */ 192 struct { 193 uint8_t src_dif_flags; 194 uint8_t dif_chk_res; 195 uint8_t dif_chk_flags; 196 uint8_t dif_chk_res2[5]; 197 uint32_t chk_ref_tag_seed; 198 uint16_t chk_app_tag_mask; 199 uint16_t chk_app_tag_seed; 200 }; 201 /* DIF insert */ 202 struct { 203 uint8_t dif_ins_res; 204 uint8_t dest_dif_flag; 205 uint8_t dif_ins_flags; 206 uint8_t dif_ins_res2[13]; 207 uint32_t ins_ref_tag_seed; 208 uint16_t ins_app_tag_mask; 209 uint16_t ins_app_tag_seed; 210 }; 211 /* DIF update */ 212 struct { 213 uint8_t src_upd_flags; 214 uint8_t upd_dest_flags; 215 uint8_t dif_upd_flags; 216 uint8_t dif_upd_res[5]; 217 uint32_t src_ref_tag_seed; 218 uint16_t src_app_tag_mask; 219 uint16_t src_app_tag_seed; 220 uint32_t dest_ref_tag_seed; 221 uint16_t dest_app_tag_mask; 222 uint16_t dest_app_tag_seed; 223 }; 224 225 uint8_t op_specific[24]; 226 }; 227 } __attribute__((packed)); 228 229 struct iax_hw_desc { 230 uint32_t pasid:20; 231 uint32_t rsvd:11; 232 uint32_t priv:1; 233 uint32_t flags:24; 234 uint32_t opcode:8; 235 uint64_t completion_addr; 236 uint64_t src1_addr; 237 uint64_t dst_addr; 238 uint32_t src1_size; 239 uint16_t int_handle; 240 union { 241 uint16_t compr_flags; 242 uint16_t decompr_flags; 243 }; 244 uint64_t src2_addr; 245 uint32_t max_dst_size; 246 uint32_t src2_size; 247 uint32_t filter_flags; 248 uint32_t num_inputs; 249 } __attribute__((packed)); 250 251 struct dsa_raw_desc { 252 uint64_t field[8]; 253 } __attribute__((packed)); 254 255 /* 256 * The status field will be modified by hardware, therefore it should be 257 * volatile and prevent the compiler from optimize the read. 258 */ 259 struct dsa_completion_record { 260 volatile uint8_t status; 261 union { 262 uint8_t result; 263 uint8_t dif_status; 264 }; 265 uint16_t rsvd; 266 uint32_t bytes_completed; 267 uint64_t fault_addr; 268 union { 269 /* common record */ 270 struct { 271 uint32_t invalid_flags:24; 272 uint32_t rsvd2:8; 273 }; 274 275 uint32_t delta_rec_size; 276 uint32_t crc_val; 277 278 /* DIF check & strip */ 279 struct { 280 uint32_t dif_chk_ref_tag; 281 uint16_t dif_chk_app_tag_mask; 282 uint16_t dif_chk_app_tag; 283 }; 284 285 /* DIF insert */ 286 struct { 287 uint64_t dif_ins_res; 288 uint32_t dif_ins_ref_tag; 289 uint16_t dif_ins_app_tag_mask; 290 uint16_t dif_ins_app_tag; 291 }; 292 293 /* DIF update */ 294 struct { 295 uint32_t dif_upd_src_ref_tag; 296 uint16_t dif_upd_src_app_tag_mask; 297 uint16_t dif_upd_src_app_tag; 298 uint32_t dif_upd_dest_ref_tag; 299 uint16_t dif_upd_dest_app_tag_mask; 300 uint16_t dif_upd_dest_app_tag; 301 }; 302 303 uint8_t op_specific[16]; 304 }; 305 } __attribute__((packed)); 306 307 struct dsa_raw_completion_record { 308 uint64_t field[4]; 309 } __attribute__((packed)); 310 311 struct iax_completion_record { 312 volatile uint8_t status; 313 uint8_t error_code; 314 uint16_t rsvd; 315 uint32_t bytes_completed; 316 uint64_t fault_addr; 317 uint32_t invalid_flags; 318 uint32_t rsvd2; 319 uint32_t output_size; 320 uint8_t output_bits; 321 uint8_t rsvd3; 322 uint16_t rsvd4; 323 uint64_t rsvd5[4]; 324 } __attribute__((packed)); 325 326 struct iax_raw_completion_record { 327 uint64_t field[8]; 328 } __attribute__((packed)); 329 330 #endif 331