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/external/llvm/lib/Target/X86/
D	X86Schedule.td	`1 //===-- X86Schedule.td - X86 Scheduling Definitions --------- tablegen --===// 8 //===----------------------------------------------------------------------===// 10 // InstrSchedModel annotations for out-of-order CPUs. 17 def ReadAfterLd : SchedRead; 21 def WriteRMW : SchedWrite; 34 // Register-Memory operation. 35 def Ld : SchedWrite; 36 // Register-Register operation. 37 def NAME : X86FoldableSchedWrite { 45 def WriteIMulH : SchedWrite; // Integer multiplication, high part. [all …]`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMSchedule.td	1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===// 9 // Instruction scheduling annotations for in-order and out-of-order CPUs. 11 // Here we define the subtarget independent read/write per-operand resources. 17 // Rd <- ADD Rn, Rm, <shift> Rs 18 // Uops \| Latency from register \| Uops - resource requirements - latency 19 // 2 \| Rn: 1 Rm: 4 Rs: 4 \| uop T0, Rm, Rs - P01 - 3 20 // \| \| uopc Rd, Rn, T0 - P01 - 1 [all …]
/external/llvm/lib/Target/ARM/
D	ARMSchedule.td	1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------- tablegen --===// 8 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 10 // Instruction scheduling annotations for out-of-order CPUs. 12 // Here we define the subtarget independent read/write per-operand resources. 18 // Rd <- ADD Rn, Rm, <shift> Rs 19 // Uops \| Latency from register \| Uops - resource requirements - latency 20 // 2 \| Rn: 1 Rm: 4 Rs: 4 \| uop T0, Rm, Rs - P01 - 3 21 // \| \| uopc Rd, Rn, T0 - P01 - 1 24 // and one cycle after the result in Rn is available. The micro-ops can execute [all …]
/external/clang/include/clang/Basic/
D	DiagnosticGroups.td	1 //==--- DiagnosticGroups.td - Diagnostic Group Definitions ----------------===// 8 //===----------------------------------------------------------------------===// 10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">; 11 def ImplicitInt : DiagGroup<"implicit-int">; 14 def Implicit : DiagGroup<"implicit", [ 20 def : DiagGroup<"abi">; 21 def AbsoluteValue : DiagGroup<"absolute-value">; 22 def AddressOfTemporary : DiagGroup<"address-of-temporary">; 23 def : DiagGroup<"aggregate-return">; 24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">; [all …]
D	DiagnosticLexKinds.td	1 //==--- DiagnosticLexKinds.td - liblex diagnostics ------------------------===// 8 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 16 def null_in_char_or_string : Warning< 19 def null_in_file : Warning<"null character ignored">, InGroup<NullCharacter>; 20 def warn_nested_block_comment : Warning<"'/*' within block comment">, 22 def escaped_newline_block_comment_end : Warning< 25 def backslash_newline_space : Warning< 27 InGroup<DiagGroup<"backslash-newline-escape">>; [all …]
D	DiagnosticParseKinds.td	1 //==--- DiagnosticParseKinds.td - libparse diagnostics --------------------===// 8 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 16 def w_asm_qualifier_ignored : Warning<"ignored %0 qualifier on asm">, 18 def warn_file_asm_volatile : Warning< 22 def err_asm_empty : Error<"__asm used with no assembly instructions">; 23 def err_inline_ms_asm_parsing : Error<"%0">; 24 def err_msasm_unsupported_arch : Error< 25 "Unsupported architecture '%0' for MS-style inline assembly">; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
D	PPCSchedule.td	1 //===-- PPCSchedule.td - PowerPC Scheduling Definitions ----- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 def IIC_IntSimple : InstrItinClass; 13 def IIC_IntGeneral : InstrItinClass; 14 def IIC_IntCompare : InstrItinClass; 15 def IIC_IntISEL : InstrItinClass; 16 def IIC_IntDivD : InstrItinClass; 17 def IIC_IntDivW : InstrItinClass; [all …]
/external/llvm/lib/Target/PowerPC/
D	PPCSchedule.td	1 //===-- PPCSchedule.td - PowerPC Scheduling Definitions ----- tablegen --===// 8 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===// 13 def IIC_IntSimple : InstrItinClass; 14 def IIC_IntGeneral : InstrItinClass; 15 def IIC_IntCompare : InstrItinClass; 16 def IIC_IntISEL : InstrItinClass; 17 def IIC_IntDivD : InstrItinClass; 18 def IIC_IntDivW : InstrItinClass; 19 def IIC_IntMFFS : InstrItinClass; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; [all …]
D	IntrinsicsHexagon.td	1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---- tablegen --===// 4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 //===----------------------------------------------------------------------===// 8 // This file defines all of the Hexagon-specific intrinsics. 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. 24 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon 71 def int_hexagon_circ_ldd : 76 def int_hexagon_circ_ldw : [all …]
D	IntrinsicsPowerPC.td	1 //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the PowerPC-specific intrinsics. 11 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 17 // Non-altivec intrinsics. 20 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>; 21 def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">, 23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
D	AVRDevices.td	1 //===---------------------------------------------------------------------===// 3 //===---------------------------------------------------------------------===// 5 // :TODO: Implement the skip errata, see `gcc/config/avr/avr-arch.h` for details 25 // SRAM-relevant instructions. 28 // LD - all 9 variants 29 // ST - all 9 variants 30 // LDD - two variants for Y and Z 31 // STD - two variants for Y and Z 35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true", 39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true", [all …]
/external/ply/ply/example/ansic/
D	cparse.py	`1 # ----------------------------------------------------------------------------- 5 # ----------------------------------------------------------------------------- 14 # translation-unit: 17 def p_translation_unit_1(t): 22 def p_translation_unit_2(t): 26 # external-declaration: 29 def p_external_declaration_1(t): 34 def p_external_declaration_2(t): 38 # function-definition: 41 def p_function_definition_1(t): [all …]`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
D	RISCVSchedule.td	1 //===-- RISCVSchedule.td - RISCV Scheduling Definitions -------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 /// Define scheduler resources associated with def operands. 10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations 11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I 12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix 13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations 14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder 15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I [all …]
D	RISCVSystemOperands.td	1 //===- RISCVSystemOperands.td ----------------------------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // RISC-V system instruction. 12 //===----------------------------------------------------------------------===// 16 //===----------------------------------------------------------------------===// 18 //===----------------------------------------------------------------------===// 24 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. 26 // bits<2> ReadWrite = op{11 - 10}; 27 // bits<2> XMode = op{9 - 8}; [all …]
/external/llvm/lib/Target/AVR/
D	AVR.td	1 //===-- AVR.td - Describe the AVR Target Machine ----------- tablegen --===// 8 //===---------------------------------------------------------------------===// 10 //===---------------------------------------------------------------------===// 12 //===---------------------------------------------------------------------===// 13 // Target-independent interfaces which we are implementing 14 //===---------------------------------------------------------------------===// 18 //===---------------------------------------------------------------------===// 20 //===---------------------------------------------------------------------===// 22 // :TODO: Implement the skip errata, see `gcc/config/avr/avr-arch.h` for details 43 // SRAM-relevant instructions. [all …]
/external/llvm/lib/Target/Hexagon/
D	HexagonIntrinsics.td	1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------- tablegen --===// 8 //===----------------------------------------------------------------------===// 11 // Application-Level Specification 12 // 80-V9418-8 Rev. B 14 //===----------------------------------------------------------------------===// 222 //===----------------------------------------------------------------------===// 225 //===----------------------------------------------------------------------===// 227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>; 228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>; 229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
D	SparcRegisterInfo.td	1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 24 def sub_even : SubRegIndex<32>; 25 def sub_odd : SubRegIndex<32, 32>; 26 def sub_even64 : SubRegIndex<64>; 27 def sub_odd64 : SubRegIndex<64, 64>; 30 // Registers are identified with 5-bit ID numbers. [all …]
/external/llvm/lib/Target/Sparc/
D	SparcRegisterInfo.td	1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------- tablegen --===// 8 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 25 def sub_even : SubRegIndex<32>; 26 def sub_odd : SubRegIndex<32, 32>; 27 def sub_even64 : SubRegIndex<64>; 28 def sub_odd64 : SubRegIndex<64, 64>; 31 // Registers are identified with 5-bit ID numbers. 32 // Ri - 32-bit integer registers [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64SchedExynosM4.td	1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16 // in-order stage for decode and dispatch and a wider issue stage. 17 // The execution units and loads and stores are out-of-order. 19 def ExynosM4Model : SchedMachineModel { 30 //===----------------------------------------------------------------------===// [all …]
D	AArch64SystemOperands.td	1 //===- AArch64SystemOperands.td ----------------------------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 16 //===----------------------------------------------------------------------===// 18 //===----------------------------------------------------------------------===// 20 def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 23 def HasPAN : Predicate<"Subtarget->hasPAN()">, 25 "ARM v8.1 Privileged Access-Never extension">; 27 def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, [all …]
D	AArch64SchedExynosM5.td	1 //=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide 16 // in-order stage for decode and dispatch and a wider issue stage. 17 // The execution units and loads and stores are out-of-order. 19 def ExynosM5Model : SchedMachineModel { 30 //===----------------------------------------------------------------------===// [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
D	HexagonIntrinsicsV5.td	1 //===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>; 10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>; 11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>; 14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>; 16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; 17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; 18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; [all …]
/external/llvm/include/llvm/IR/
D	IntrinsicsPowerPC.td	1 //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---- tablegen --===// 8 //===----------------------------------------------------------------------===// 10 // This file defines all of the PowerPC-specific intrinsics. 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 18 // Non-altivec intrinsics. 21 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>; 22 def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>; 23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>; 24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>; [all …]
/external/clang/include/clang/Driver/
D	Options.td	1 //===--- Options.td - Options for clang -----------------------------------===// 8 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 20 // DriverOption - The option is a "driver" option, and should not be forwarded 22 def DriverOption : OptionFlag; 24 // LinkerInput - The option is a linker input. 25 def LinkerInput : OptionFlag; 27 // NoArgumentUnused - Don't report argument unused warnings for this option; this 28 // is useful for options like -static or -dynamic which a user may always end up 30 def NoArgumentUnused : OptionFlag; [all …]

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