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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td71 def int_hexagon_circ_ldd :
76 def int_hexagon_circ_ldw :
81 def int_hexagon_circ_ldh :
86 def int_hexagon_circ_lduh :
91 def int_hexagon_circ_ldb :
96 def int_hexagon_circ_ldub :
102 def int_hexagon_circ_std :
107 def int_hexagon_circ_stw :
112 def int_hexagon_circ_sth :
117 def int_hexagon_circ_sthhi :
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DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
21 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
27 def int_aarch64_clrex : Intrinsic<[]>;
29 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def PragmaComment : Decl;
15 def PragmaDetectMismatch : Decl;
16 def ExternCContext : Decl, DeclContext;
17 def Named : Decl<1>;
18 def Namespace : DDecl<Named>, DeclContext;
19 def UsingDirective : DDecl<Named>;
20 def NamespaceAlias : DDecl<Named>;
21 def Label : DDecl<Named>;
22 def Type : DDecl<Named, 1>;
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DDiagnosticParseKinds.td16 def w_asm_qualifier_ignored : Warning<"ignored %0 qualifier on asm">,
18 def warn_file_asm_volatile : Warning<
22 def err_asm_empty : Error<"__asm used with no assembly instructions">;
23 def err_inline_ms_asm_parsing : Error<"%0">;
24 def err_msasm_unsupported_arch : Error<
26 def err_msasm_unable_to_create_target : Error<
28 def err_gnu_inline_asm_disabled : Error<
30 def err_asm_goto_not_supported_yet : Error<
36 def ext_empty_translation_unit : Extension<
39 def warn_cxx98_compat_top_level_semi : Warning<
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DDiagnosticLexKinds.td16 def null_in_char_or_string : Warning<
19 def null_in_file : Warning<"null character ignored">, InGroup<NullCharacter>;
20 def warn_nested_block_comment : Warning<"'/*' within block comment">,
22 def escaped_newline_block_comment_end : Warning<
25 def backslash_newline_space : Warning<
30 def warn_cxx98_compat_less_colon_colon : Warning<
35 def trigraph_ignored : Warning<"trigraph ignored">, InGroup<Trigraphs>;
36 def trigraph_ignored_block_comment : Warning<
38 def trigraph_ends_block_comment : Warning<"trigraph ends block comment">,
40 def trigraph_converted : Warning<"trigraph converted to '%0' character">,
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DDiagnosticSemaKinds.td17 def note_previous_decl : Note<"%0 declared here">;
18 def note_entity_declared_at : Note<"%0 declared here">;
19 def note_callee_decl : Note<"%0 declared here">;
20 def note_defined_here : Note<"%0 defined here">;
23 def warn_variables_not_in_loop_body : Warning<
27 def warn_redundant_loop_iteration : Warning<
31 def note_loop_iteration_here : Note<"%select{decremented|incremented}0 here">;
33 def warn_duplicate_enum_values : Warning<
36 def note_duplicate_element : Note<"element %0 also has value %1">;
39 def warn_unsigned_abs : Warning<
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/external/ply/ply/example/ansic/
Dcparse.py17 def p_translation_unit_1(t):
22 def p_translation_unit_2(t):
29 def p_external_declaration_1(t):
34 def p_external_declaration_2(t):
41 def p_function_definition_1(t):
46 def p_function_definition_2(t):
51 def p_function_definition_3(t):
56 def p_function_definition_4(t):
63 def p_declaration_1(t):
68 def p_declaration_2(t):
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
17 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
18 def WriteJmp : SchedWrite; // Jump
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DRISCVSystemOperands.td36 def SysRegsList : GenericTable {
45 def lookupSysRegByName : SearchIndex {
57 def : SysReg<"ustatus", 0x000>;
58 def : SysReg<"uie", 0x004>;
59 def : SysReg<"utvec", 0x005>;
64 def : SysReg<"uscratch", 0x040>;
65 def : SysReg<"uepc", 0x041>;
66 def : SysReg<"ucause", 0x042>;
67 def : SysReg<"utval", 0x043>;
68 def : SysReg<"uip", 0x044>;
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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td24 def sub_even : SubRegIndex<32>;
25 def sub_odd : SubRegIndex<32, 32>;
26 def sub_even64 : SubRegIndex<64>;
27 def sub_odd64 : SubRegIndex<64, 64>;
58 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
60 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
62 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
64 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
68 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
65 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
67 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
69 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/external/llvm/lib/Target/AVR/
DAVR.td53 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
57 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
63 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
69 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
74 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
79 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
84 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
89 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
93 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
98 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedExynosM4.td19 def ExynosM4Model : SchedMachineModel {
35 def M4UnitA : ProcResource<2>; // Simple integer
36 def M4UnitC : ProcResource<2>; // Simple and complex integer
38 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M4UnitE : ProcResource<1>; // CRC (inside C0)
41 def M4UnitB : ProcResource<2>; // Branch
42 def M4UnitL0 : ProcResource<1>; // Load
43 def M4UnitS0 : ProcResource<1>; // Store
44 def M4PipeLS : ProcResource<1>; // Load/Store
46 def M4UnitL1 : ProcResource<1>;
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