1 /* 2 * Copyright (C) 2009 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 18 #define ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 19 20 #include <stdint.h> 21 22 #include <iosfwd> 23 24 #include <android-base/logging.h> 25 26 #include "arch/arm/registers_arm.h" 27 #include "base/casts.h" 28 #include "base/globals.h" 29 30 namespace art { 31 namespace arm { 32 33 // Defines constants and accessor classes to assemble, disassemble and 34 // simulate ARM instructions. 35 // 36 // Section references in the code refer to the "ARM Architecture 37 // Reference Manual ARMv7-A and ARMv7-R edition", issue C.b (24 July 38 // 2012). 39 // 40 // Constants for specific fields are defined in their respective named enums. 41 // General constants are in an anonymous enum in class Instr. 42 43 // 4 bits option for the dmb instruction. 44 // Order and values follows those of the ARM Architecture Reference Manual. 45 enum DmbOptions { 46 SY = 0xf, 47 ST = 0xe, 48 ISH = 0xb, 49 ISHST = 0xa, 50 NSH = 0x7, 51 NSHST = 0x6 52 }; 53 54 // Values for double-precision floating point registers. 55 enum DRegister { // private marker to avoid generate-operator-out.py from processing. 56 D0 = 0, 57 D1 = 1, 58 D2 = 2, 59 D3 = 3, 60 D4 = 4, 61 D5 = 5, 62 D6 = 6, 63 D7 = 7, 64 D8 = 8, 65 D9 = 9, 66 D10 = 10, 67 D11 = 11, 68 D12 = 12, 69 D13 = 13, 70 D14 = 14, 71 D15 = 15, 72 D16 = 16, 73 D17 = 17, 74 D18 = 18, 75 D19 = 19, 76 D20 = 20, 77 D21 = 21, 78 D22 = 22, 79 D23 = 23, 80 D24 = 24, 81 D25 = 25, 82 D26 = 26, 83 D27 = 27, 84 D28 = 28, 85 D29 = 29, 86 D30 = 30, 87 D31 = 31, 88 kNumberOfDRegisters = 32, 89 kNumberOfOverlappingDRegisters = 16, 90 kNoDRegister = -1, 91 }; 92 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 93 94 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 95 // as defined in section A3.4 96 enum Opcode { 97 kNoOperand = -1, 98 AND = 0, // Logical AND 99 EOR = 1, // Logical Exclusive OR 100 SUB = 2, // Subtract 101 RSB = 3, // Reverse Subtract 102 ADD = 4, // Add 103 ADC = 5, // Add with Carry 104 SBC = 6, // Subtract with Carry 105 RSC = 7, // Reverse Subtract with Carry 106 TST = 8, // Test 107 TEQ = 9, // Test Equivalence 108 CMP = 10, // Compare 109 CMN = 11, // Compare Negated 110 ORR = 12, // Logical (inclusive) OR 111 MOV = 13, // Move 112 BIC = 14, // Bit Clear 113 MVN = 15, // Move Not 114 ORN = 16, // Logical OR NOT. 115 kMaxOperand = 17 116 }; 117 118 // Size (in bytes) of registers. 119 const int kRegisterSize = 4; 120 121 // List of registers used in load/store multiple. 122 using RegList = uint16_t; 123 124 } // namespace arm 125 } // namespace art 126 127 #endif // ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 128