1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/interrupt_props.h>
13 #include <drivers/arm/gic_common.h>
14
15 #include "../common/gic_common_private.h"
16 #include "gicv3_private.h"
17
18 /******************************************************************************
19 * This function marks the core as awake in the re-distributor and
20 * ensures that the interface is active.
21 *****************************************************************************/
gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
23 {
24 /*
25 * The WAKER_PS_BIT should be changed to 0
26 * only when WAKER_CA_BIT is 1.
27 */
28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
29
30 /* Mark the connected core as awake */
31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
32
33 /* Wait till the WAKER_CA_BIT changes to 0 */
34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) {
35 }
36 }
37
38 /******************************************************************************
39 * This function marks the core as asleep in the re-distributor and ensures
40 * that the interface is quiescent.
41 *****************************************************************************/
gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
43 {
44 /* Mark the connected core as asleep */
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
46
47 /* Wait till the WAKER_CA_BIT changes to 1 */
48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) {
49 }
50 }
51
52 /*******************************************************************************
53 * This function probes the Redistributor frames when the driver is initialised
54 * and saves their base addresses. These base addresses are used later to
55 * initialise each Redistributor interface.
56 ******************************************************************************/
gicv3_rdistif_base_addrs_probe(uintptr_t * rdistif_base_addrs,unsigned int rdistif_num,uintptr_t gicr_base,mpidr_hash_fn mpidr_to_core_pos)57 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
58 unsigned int rdistif_num,
59 uintptr_t gicr_base,
60 mpidr_hash_fn mpidr_to_core_pos)
61 {
62 u_register_t mpidr;
63 unsigned int proc_num;
64 uint64_t typer_val;
65 uintptr_t rdistif_base = gicr_base;
66
67 assert(rdistif_base_addrs != NULL);
68
69 /*
70 * Iterate over the Redistributor frames. Store the base address of each
71 * frame in the platform provided array. Use the "Processor Number"
72 * field to index into the array if the platform has not provided a hash
73 * function to convert an MPIDR (obtained from the "Affinity Value"
74 * field into a linear index.
75 */
76 do {
77 typer_val = gicr_read_typer(rdistif_base);
78 if (mpidr_to_core_pos != NULL) {
79 mpidr = mpidr_from_gicr_typer(typer_val);
80 proc_num = mpidr_to_core_pos(mpidr);
81 } else {
82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
83 TYPER_PROC_NUM_MASK;
84 }
85
86 if (proc_num < rdistif_num) {
87 rdistif_base_addrs[proc_num] = rdistif_base;
88 }
89
90 rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
91 } while ((typer_val & TYPER_LAST_BIT) == 0U);
92 }
93
94 /*******************************************************************************
95 * Helper function to get the maximum SPI INTID + 1.
96 ******************************************************************************/
gicv3_get_spi_limit(uintptr_t gicd_base)97 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
98 {
99 unsigned int spi_limit;
100 unsigned int typer_reg = gicd_read_typer(gicd_base);
101
102 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
103 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
104
105 /* Filter out special INTIDs 1020-1023 */
106 if (spi_limit > (MAX_SPI_ID + 1U)) {
107 return MAX_SPI_ID + 1U;
108 }
109
110 return spi_limit;
111 }
112
113 #if GIC_EXT_INTID
114 /*******************************************************************************
115 * Helper function to get the maximum ESPI INTID + 1.
116 ******************************************************************************/
gicv3_get_espi_limit(uintptr_t gicd_base)117 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
118 {
119 unsigned int typer_reg = gicd_read_typer(gicd_base);
120
121 /* Check if extended SPI range is implemented */
122 if ((typer_reg & TYPER_ESPI) != 0U) {
123 /*
124 * (maximum ESPI INTID + 1) is equal to
125 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
126 */
127 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
128 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
129 }
130
131 return 0U;
132 }
133 #endif /* GIC_EXT_INTID */
134
135 /*******************************************************************************
136 * Helper function to configure the default attributes of (E)SPIs.
137 ******************************************************************************/
gicv3_spis_config_defaults(uintptr_t gicd_base)138 void gicv3_spis_config_defaults(uintptr_t gicd_base)
139 {
140 unsigned int i, num_ints;
141 #if GIC_EXT_INTID
142 unsigned int num_eints;
143 #endif
144
145 num_ints = gicv3_get_spi_limit(gicd_base);
146 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
147
148 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
149 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
150 gicd_write_igroupr(gicd_base, i, ~0U);
151 }
152
153 #if GIC_EXT_INTID
154 num_eints = gicv3_get_espi_limit(gicd_base);
155 if (num_eints != 0U) {
156 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
157
158 for (i = MIN_ESPI_ID; i < num_eints;
159 i += (1U << IGROUPR_SHIFT)) {
160 gicd_write_igroupr(gicd_base, i, ~0U);
161 }
162 } else {
163 INFO("ESPI range is not implemented.\n");
164 }
165 #endif
166
167 /* Setup the default (E)SPI priorities doing four at a time */
168 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) {
169 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
170 }
171
172 #if GIC_EXT_INTID
173 for (i = MIN_ESPI_ID; i < num_eints;
174 i += (1U << IPRIORITYR_SHIFT)) {
175 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
176 }
177 #endif
178 /*
179 * Treat all (E)SPIs as level triggered by default, write 16 at a time
180 */
181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) {
182 gicd_write_icfgr(gicd_base, i, 0U);
183 }
184
185 #if GIC_EXT_INTID
186 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) {
187 gicd_write_icfgr(gicd_base, i, 0U);
188 }
189 #endif
190 }
191
192 /*******************************************************************************
193 * Helper function to configure properties of secure (E)SPIs
194 ******************************************************************************/
gicv3_secure_spis_config_props(uintptr_t gicd_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)195 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
196 const interrupt_prop_t *interrupt_props,
197 unsigned int interrupt_props_num)
198 {
199 unsigned int i;
200 const interrupt_prop_t *current_prop;
201 unsigned long long gic_affinity_val;
202 unsigned int ctlr_enable = 0U;
203
204 /* Make sure there's a valid property array */
205 if (interrupt_props_num > 0U) {
206 assert(interrupt_props != NULL);
207 }
208
209 for (i = 0U; i < interrupt_props_num; i++) {
210 current_prop = &interrupt_props[i];
211
212 unsigned int intr_num = current_prop->intr_num;
213
214 /* Skip SGI, (E)PPI and LPI interrupts */
215 if (!IS_SPI(intr_num)) {
216 continue;
217 }
218
219 /* Configure this interrupt as a secure interrupt */
220 gicd_clr_igroupr(gicd_base, intr_num);
221
222 /* Configure this interrupt as G0 or a G1S interrupt */
223 assert((current_prop->intr_grp == INTR_GROUP0) ||
224 (current_prop->intr_grp == INTR_GROUP1S));
225
226 if (current_prop->intr_grp == INTR_GROUP1S) {
227 gicd_set_igrpmodr(gicd_base, intr_num);
228 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
229 } else {
230 gicd_clr_igrpmodr(gicd_base, intr_num);
231 ctlr_enable |= CTLR_ENABLE_G0_BIT;
232 }
233
234 /* Set interrupt configuration */
235 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg);
236
237 /* Set the priority of this interrupt */
238 gicd_set_ipriorityr(gicd_base, intr_num,
239 current_prop->intr_pri);
240
241 /* Target (E)SPIs to the primary CPU */
242 gic_affinity_val =
243 gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
244 gicd_write_irouter(gicd_base, intr_num,
245 gic_affinity_val);
246
247 /* Enable this interrupt */
248 gicd_set_isenabler(gicd_base, intr_num);
249 }
250
251 return ctlr_enable;
252 }
253
254 /*******************************************************************************
255 * Helper function to configure the default attributes of (E)SPIs
256 ******************************************************************************/
gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)257 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
258 {
259 unsigned int i, ppi_regs_num, regs_num;
260
261 #if GIC_EXT_INTID
262 /* Calculate number of PPI registers */
263 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
264 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
265 /* All other values except PPInum [0-2] are reserved */
266 if (ppi_regs_num > 3U) {
267 ppi_regs_num = 1U;
268 }
269 #else
270 ppi_regs_num = 1U;
271 #endif
272 /*
273 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
274 * This is a more scalable approach as it avoids clearing
275 * the enable bits in the GICD_CTLR.
276 */
277 for (i = 0U; i < ppi_regs_num; ++i) {
278 gicr_write_icenabler(gicr_base, i, ~0U);
279 }
280
281 /* Wait for pending writes to GICR_ICENABLER */
282 gicr_wait_for_pending_write(gicr_base);
283
284 /* 32 interrupt IDs per GICR_IGROUPR register */
285 for (i = 0U; i < ppi_regs_num; ++i) {
286 /* Treat all SGIs/(E)PPIs as G1NS by default */
287 gicr_write_igroupr(gicr_base, i, ~0U);
288 }
289
290 /* 4 interrupt IDs per GICR_IPRIORITYR register */
291 regs_num = ppi_regs_num << 3;
292 for (i = 0U; i < regs_num; ++i) {
293 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */
294 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL);
295 }
296
297 /* 16 interrupt IDs per GICR_ICFGR register */
298 regs_num = ppi_regs_num << 1;
299 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) {
300 /* Configure all (E)PPIs as level triggered by default */
301 gicr_write_icfgr(gicr_base, i, 0U);
302 }
303 }
304
305 /*******************************************************************************
306 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs
307 ******************************************************************************/
gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)308 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
309 const interrupt_prop_t *interrupt_props,
310 unsigned int interrupt_props_num)
311 {
312 unsigned int i;
313 const interrupt_prop_t *current_prop;
314 unsigned int ctlr_enable = 0U;
315
316 /* Make sure there's a valid property array */
317 if (interrupt_props_num > 0U) {
318 assert(interrupt_props != NULL);
319 }
320
321 for (i = 0U; i < interrupt_props_num; i++) {
322 current_prop = &interrupt_props[i];
323
324 unsigned int intr_num = current_prop->intr_num;
325
326 /* Skip (E)SPI interrupt */
327 if (!IS_SGI_PPI(intr_num)) {
328 continue;
329 }
330
331 /* Configure this interrupt as a secure interrupt */
332 gicr_clr_igroupr(gicr_base, intr_num);
333
334 /* Configure this interrupt as G0 or a G1S interrupt */
335 assert((current_prop->intr_grp == INTR_GROUP0) ||
336 (current_prop->intr_grp == INTR_GROUP1S));
337
338 if (current_prop->intr_grp == INTR_GROUP1S) {
339 gicr_set_igrpmodr(gicr_base, intr_num);
340 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
341 } else {
342 gicr_clr_igrpmodr(gicr_base, intr_num);
343 ctlr_enable |= CTLR_ENABLE_G0_BIT;
344 }
345
346 /* Set the priority of this interrupt */
347 gicr_set_ipriorityr(gicr_base, intr_num,
348 current_prop->intr_pri);
349
350 /*
351 * Set interrupt configuration for (E)PPIs.
352 * Configurations for SGIs 0-15 are ignored.
353 */
354 if (intr_num >= MIN_PPI_ID) {
355 gicr_set_icfgr(gicr_base, intr_num,
356 current_prop->intr_cfg);
357 }
358
359 /* Enable this interrupt */
360 gicr_set_isenabler(gicr_base, intr_num);
361 }
362
363 return ctlr_enable;
364 }
365
366 /**
367 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region
368 * @gicr_frame: base address of the GICR region to check
369 *
370 * This iterates over the GICR_TYPER registers of multiple GICR frames in
371 * a GICR region, to find the instance which has the LAST bit set. For most
372 * systems this corresponds to the number of cores handled by a redistributor,
373 * but there could be disabled cores among them.
374 * It assumes that each GICR region is fully accessible (till the LAST bit
375 * marks the end of the region).
376 * If a platform has multiple GICR regions, this function would need to be
377 * called multiple times, providing the respective GICR base address each time.
378 *
379 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT)
380 ******************************************************************************/
gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)381 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)
382 {
383 uintptr_t rdistif_base = gicr_frame;
384 unsigned int count;
385
386 for (count = 1; count < PLATFORM_CORE_COUNT; count++) {
387 if ((gicr_read_typer(rdistif_base) & TYPER_LAST_BIT) != 0U) {
388 break;
389 }
390 rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
391 }
392
393 return count;
394 }
395