1 /*
2 * Copyright 2018-2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include <assert.h>
9
10 #ifdef LS_EL3_INTERRUPT_HANDLER
11 #include <ls_interrupt_mgmt.h>
12 #endif
13 #include <mmu_def.h>
14 #include <plat_common.h>
15
16 /*
17 * Placeholder variables for copying the arguments that have been passed to
18 * BL31 from BL2.
19 */
20 #ifdef TEST_BL31
21 #define SPSR_FOR_EL2H 0x3C9
22 #define SPSR_FOR_EL1H 0x3C5
23 #else
24 static entry_point_info_t bl31_image_ep_info;
25 #endif
26
27 static entry_point_info_t bl32_image_ep_info;
28 static entry_point_info_t bl33_image_ep_info;
29
30 static dram_regions_info_t dram_regions_info = {0};
31 static uint64_t rcw_porsr1;
32
33 /* Return the pointer to the 'dram_regions_info structure of the DRAM.
34 * This structure is populated after init_ddr().
35 */
get_dram_regions_info(void)36 dram_regions_info_t *get_dram_regions_info(void)
37 {
38 return &dram_regions_info;
39 }
40
41 /* Return the RCW.PORSR1 value which was passed in from BL2
42 */
bl31_get_porsr1(void)43 uint64_t bl31_get_porsr1(void)
44 {
45 return rcw_porsr1;
46 }
47
48 /*
49 * Return pointer to the 'entry_point_info' structure of the next image for the
50 * security state specified:
51 * - BL33 corresponds to the non-secure image type; while
52 * - BL32 corresponds to the secure image type.
53 * - A NULL pointer is returned, if the image does not exist.
54 */
bl31_plat_get_next_image_ep_info(uint32_t type)55 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
56 {
57 entry_point_info_t *next_image_info;
58
59 assert(sec_state_is_valid(type));
60 next_image_info = (type == NON_SECURE)
61 ? &bl33_image_ep_info : &bl32_image_ep_info;
62
63 #ifdef TEST_BL31
64 next_image_info->pc = _get_test_entry();
65 next_image_info->spsr = SPSR_FOR_EL2H;
66 next_image_info->h.attr = NON_SECURE;
67 #endif
68
69 if (next_image_info->pc != 0U) {
70 return next_image_info;
71 } else {
72 return NULL;
73 }
74 }
75
76 /*
77 * Perform any BL31 early platform setup common to NXP platforms.
78 * - Here is an opportunity to copy parameters passed by the calling EL (S-EL1
79 * in BL2 & S-EL3 in BL1) before they are lost (potentially).
80 * - This needs to be done before the MMU is initialized so that the
81 * memory layout can be used while creating page tables.
82 * - BL2 has flushed this information to memory, in order to fetch latest data.
83 */
84
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)85 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
86 u_register_t arg2, u_register_t arg3)
87 {
88 #ifndef TEST_BL31
89 int i = 0;
90 void *from_bl2 = (void *)arg0;
91 #endif
92 soc_early_platform_setup2();
93
94 #ifdef TEST_BL31
95 dram_regions_info.num_dram_regions = 2;
96 dram_regions_info.total_dram_size = 0x100000000;
97 dram_regions_info.region[0].addr = 0x80000000;
98 dram_regions_info.region[0].size = 0x80000000;
99 dram_regions_info.region[1].addr = 0x880000000;
100 dram_regions_info.region[1].size = 0x80000000;
101
102 bl33_image_ep_info.pc = _get_test_entry();
103 #else
104 /*
105 * Check params passed from BL2 should not be NULL,
106 */
107 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
108
109 assert(params_from_bl2 != NULL);
110 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
111 assert(params_from_bl2->h.version >= VERSION_2);
112
113 bl_params_node_t *bl_params = params_from_bl2->head;
114
115 /*
116 * Copy BL33 and BL32 (if present), entry point information.
117 * They are stored in Secure RAM, in BL2's address space.
118 */
119 while (bl_params != NULL) {
120 if (bl_params->image_id == BL31_IMAGE_ID) {
121 bl31_image_ep_info = *bl_params->ep_info;
122 dram_regions_info_t *loc_dram_regions_info =
123 (dram_regions_info_t *) bl31_image_ep_info.args.arg3;
124
125 dram_regions_info.num_dram_regions =
126 loc_dram_regions_info->num_dram_regions;
127 dram_regions_info.total_dram_size =
128 loc_dram_regions_info->total_dram_size;
129 VERBOSE("Number of DRAM Regions = %llx\n",
130 dram_regions_info.num_dram_regions);
131
132 for (i = 0; i < dram_regions_info.num_dram_regions;
133 i++) {
134 dram_regions_info.region[i].addr =
135 loc_dram_regions_info->region[i].addr;
136 dram_regions_info.region[i].size =
137 loc_dram_regions_info->region[i].size;
138 VERBOSE("DRAM%d Size = %llx\n", i,
139 dram_regions_info.region[i].size);
140 }
141 rcw_porsr1 = bl31_image_ep_info.args.arg4;
142 }
143
144 if (bl_params->image_id == BL32_IMAGE_ID) {
145 bl32_image_ep_info = *bl_params->ep_info;
146 }
147
148 if (bl_params->image_id == BL33_IMAGE_ID) {
149 bl33_image_ep_info = *bl_params->ep_info;
150 }
151
152 bl_params = bl_params->next_params_info;
153 }
154 #endif /* TEST_BL31 */
155
156 if (bl33_image_ep_info.pc == 0) {
157 panic();
158 }
159
160 /*
161 * perform basic initialization on the soc
162 */
163 soc_init();
164 }
165
166 /*******************************************************************************
167 * Perform any BL31 platform setup common to ARM standard platforms
168 ******************************************************************************/
bl31_platform_setup(void)169 void bl31_platform_setup(void)
170 {
171 NOTICE("Welcome to %s BL31 Phase\n", BOARD);
172 soc_platform_setup();
173
174 /* Console logs gone missing as part going to
175 * EL1 for initilizing Bl32 if present.
176 * console flush is necessary to avoid it.
177 */
178 (void)console_flush();
179 }
180
bl31_plat_runtime_setup(void)181 void bl31_plat_runtime_setup(void)
182 {
183 #ifdef LS_EL3_INTERRUPT_HANDLER
184 ls_el3_interrupt_config();
185 #endif
186 soc_runtime_setup();
187 }
188
189 /*******************************************************************************
190 * Perform the very early platform specific architectural setup shared between
191 * ARM standard platforms. This only does basic initialization. Later
192 * architectural setup (bl31_arch_setup()) does not do anything platform
193 * specific.
194 ******************************************************************************/
bl31_plat_arch_setup(void)195 void bl31_plat_arch_setup(void)
196 {
197
198 ls_setup_page_tables(BL31_BASE,
199 BL31_END - BL31_BASE,
200 BL_CODE_BASE,
201 BL_CODE_END,
202 BL_RO_DATA_BASE,
203 BL_RO_DATA_END
204 #if USE_COHERENT_MEM
205 , BL_COHERENT_RAM_BASE,
206 BL_COHERENT_RAM_END
207 #endif
208 );
209 enable_mmu_el3(0);
210 }
211