1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neonfma_rr1_p5_x16(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_raddstoreexpminusmax_ukernel__neonfma_rr1_p5_x16(
19 size_t elements,
20 const float* input,
21 const float* max,
22 float* output,
23 float* sum,
24 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(elements % sizeof(float) == 0);
27
28 const float32x4_t vi_max = vld1q_dup_f32(max);
29 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->neonfma_rr1_p5.log2e);
30 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->neonfma_rr1_p5.magic_bias);
31 const float32x4_t vminus_ln2 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.minus_ln2);
32 const float32x4_t vc5 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c5);
33 const float32x4_t vc4 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c4);
34 const float32x4_t vc3 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c3);
35 const float32x4_t vc2 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c2);
36 const float32x4_t vc1 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c1);
37 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->neonfma_rr1_p5.denorm_cutoff);
38
39 float32x4_t vacc0 = vmovq_n_f32(0.0f);
40 for (; elements >= 16 * sizeof(float); elements -= 16 * sizeof(float)) {
41 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
42 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
43 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
44 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
45
46 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
47 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
48 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
49 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
50
51 float32x4_t vn0123 = vfmaq_f32(vmagic_bias, vx0123, vlog2e);
52 float32x4_t vn4567 = vfmaq_f32(vmagic_bias, vx4567, vlog2e);
53 float32x4_t vn89AB = vfmaq_f32(vmagic_bias, vx89AB, vlog2e);
54 float32x4_t vnCDEF = vfmaq_f32(vmagic_bias, vxCDEF, vlog2e);
55
56 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
57 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
58 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
59 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnCDEF), 23));
60
61 vn0123 = vsubq_f32(vn0123, vmagic_bias);
62 vn4567 = vsubq_f32(vn4567, vmagic_bias);
63 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
64 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
65
66 float32x4_t vt0123 = vfmaq_f32(vx0123, vn0123, vminus_ln2);
67 float32x4_t vt4567 = vfmaq_f32(vx4567, vn4567, vminus_ln2);
68 float32x4_t vt89AB = vfmaq_f32(vx89AB, vn89AB, vminus_ln2);
69 float32x4_t vtCDEF = vfmaq_f32(vxCDEF, vnCDEF, vminus_ln2);
70
71 float32x4_t vp0123 = vfmaq_f32(vc4, vc5, vt0123);
72 float32x4_t vp4567 = vfmaq_f32(vc4, vc5, vt4567);
73 float32x4_t vp89AB = vfmaq_f32(vc4, vc5, vt89AB);
74 float32x4_t vpCDEF = vfmaq_f32(vc4, vc5, vtCDEF);
75
76 vp0123 = vfmaq_f32(vc3, vp0123, vt0123);
77 vp4567 = vfmaq_f32(vc3, vp4567, vt4567);
78 vp89AB = vfmaq_f32(vc3, vp89AB, vt89AB);
79 vpCDEF = vfmaq_f32(vc3, vpCDEF, vtCDEF);
80
81 vp0123 = vfmaq_f32(vc2, vp0123, vt0123);
82 vp4567 = vfmaq_f32(vc2, vp4567, vt4567);
83 vp89AB = vfmaq_f32(vc2, vp89AB, vt89AB);
84 vpCDEF = vfmaq_f32(vc2, vpCDEF, vtCDEF);
85
86 vp0123 = vfmaq_f32(vc1, vp0123, vt0123);
87 vp4567 = vfmaq_f32(vc1, vp4567, vt4567);
88 vp89AB = vfmaq_f32(vc1, vp89AB, vt89AB);
89 vpCDEF = vfmaq_f32(vc1, vpCDEF, vtCDEF);
90
91 vt0123 = vmulq_f32(vt0123, vs0123);
92 vt4567 = vmulq_f32(vt4567, vs4567);
93 vt89AB = vmulq_f32(vt89AB, vs89AB);
94 vtCDEF = vmulq_f32(vtCDEF, vsCDEF);
95
96 float32x4_t vf0123 = vfmaq_f32(vs0123, vp0123, vt0123);
97 float32x4_t vf4567 = vfmaq_f32(vs4567, vp4567, vt4567);
98 float32x4_t vf89AB = vfmaq_f32(vs89AB, vp89AB, vt89AB);
99 float32x4_t vfCDEF = vfmaq_f32(vsCDEF, vpCDEF, vtCDEF);
100
101 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
102 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
103 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
104 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
105
106 vst1q_f32(output, vf0123); output += 4;
107 vst1q_f32(output, vf4567); output += 4;
108 vst1q_f32(output, vf89AB); output += 4;
109 vst1q_f32(output, vfCDEF); output += 4;
110
111 vacc0 = vaddq_f32(vacc0, vf0123);
112 vacc0 = vaddq_f32(vacc0, vf4567);
113 vacc0 = vaddq_f32(vacc0, vf89AB);
114 vacc0 = vaddq_f32(vacc0, vfCDEF);
115 }
116
117 float32x4_t vacc = vacc0;
118 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
119 const float32x4_t vi = vld1q_f32(input); input += 4;
120
121 const float32x4_t vx = vsubq_f32(vi, vi_max);
122
123 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
124
125 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
126
127 vn = vsubq_f32(vn, vmagic_bias);
128
129 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2);
130
131 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
132 vp = vfmaq_f32(vc3, vp, vt);
133 vp = vfmaq_f32(vc2, vp, vt);
134 vp = vfmaq_f32(vc1, vp, vt);
135
136 vt = vmulq_f32(vt, vs);
137 float32x4_t vf = vfmaq_f32(vs, vp, vt);
138
139 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
140
141 vst1q_f32(output, vf); output += 4;
142
143 vacc = vaddq_f32(vacc, vf);
144 }
145 #if XNN_ARCH_ARM64
146 float vacc_lo = vaddvq_f32(vacc);
147 #else
148 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
149 #endif
150 if (elements != 0) {
151 assert(elements >= 1 * sizeof(float));
152 assert(elements <= 3 * sizeof(float));
153 const float32x4_t vi = vld1q_f32(input); input += 4;
154
155 const float32x4_t vx = vsubq_f32(vi, vi_max);
156
157 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
158
159 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
160
161 vn = vsubq_f32(vn, vmagic_bias);
162
163 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2);
164
165 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
166 vp = vfmaq_f32(vc3, vp, vt);
167 vp = vfmaq_f32(vc2, vp, vt);
168 vp = vfmaq_f32(vc1, vp, vt);
169
170 vt = vmulq_f32(vt, vs);
171 float32x4_t vf = vfmaq_f32(vs, vp, vt);
172
173 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
174
175 float32x2_t vf_lo = vget_low_f32(vf);
176 if (elements & (2 * sizeof(float))) {
177 vst1_f32(output, vf_lo); output += 2;
178
179 #if XNN_ARCH_ARM64
180 vacc_lo += vaddv_f32(vf_lo);
181 #else
182 vacc_lo = vadd_f32(vacc_lo, vf_lo);
183 #endif
184
185 vf_lo = vget_high_f32(vf);
186 }
187 if (elements & (1 * sizeof(float))) {
188 vst1_lane_f32(output, vf_lo, 0);
189
190 #if XNN_ARCH_ARM64
191 vacc_lo += vget_lane_f32(vf_lo, 0);
192 #else
193 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
194 #endif
195 }
196 }
197 #if XNN_ARCH_ARM64
198 *sum = vacc_lo;
199 #else
200 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
201 #endif
202 }
203