1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 ************************************************************************************************************************ 29 * @file gfx9addrlib.h 30 * @brief Contgfx9ns the Gfx9Lib class definition. 31 ************************************************************************************************************************ 32 */ 33 34 #ifndef __GFX9_ADDR_LIB_H__ 35 #define __GFX9_ADDR_LIB_H__ 36 37 #include "addrlib2.h" 38 #include "coord.h" 39 40 namespace Addr 41 { 42 namespace V2 43 { 44 45 /** 46 ************************************************************************************************************************ 47 * @brief GFX9 specific settings structure. 48 ************************************************************************************************************************ 49 */ 50 struct Gfx9ChipSettings 51 { 52 struct 53 { 54 // Asic/Generation name 55 UINT_32 isArcticIsland : 1; 56 UINT_32 isVega10 : 1; 57 UINT_32 isRaven : 1; 58 UINT_32 isVega12 : 1; 59 UINT_32 isVega20 : 1; 60 UINT_32 reserved0 : 27; 61 62 // Display engine IP version name 63 UINT_32 isDce12 : 1; 64 UINT_32 isDcn1 : 1; 65 UINT_32 isDcn2 : 1; 66 UINT_32 reserved1 : 29; 67 68 // Misc configuration bits 69 UINT_32 metaBaseAlignFix : 1; 70 UINT_32 depthPipeXorDisable : 1; 71 UINT_32 htileAlignFix : 1; 72 UINT_32 applyAliasFix : 1; 73 UINT_32 htileCacheRbConflict: 1; 74 UINT_32 reserved2 : 27; 75 }; 76 }; 77 78 /** 79 ************************************************************************************************************************ 80 * @brief GFX9 data surface type. 81 ************************************************************************************************************************ 82 */ 83 enum Gfx9DataType 84 { 85 Gfx9DataColor, 86 Gfx9DataDepthStencil, 87 Gfx9DataFmask 88 }; 89 90 const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR); 91 92 const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 93 (1u << ADDR_SW_256B_D) | 94 (1u << ADDR_SW_256B_R); 95 96 const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) | 97 (1u << ADDR_SW_4KB_S) | 98 (1u << ADDR_SW_4KB_D) | 99 (1u << ADDR_SW_4KB_R) | 100 (1u << ADDR_SW_4KB_Z_X) | 101 (1u << ADDR_SW_4KB_S_X) | 102 (1u << ADDR_SW_4KB_D_X) | 103 (1u << ADDR_SW_4KB_R_X); 104 105 const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) | 106 (1u << ADDR_SW_64KB_S) | 107 (1u << ADDR_SW_64KB_D) | 108 (1u << ADDR_SW_64KB_R) | 109 (1u << ADDR_SW_64KB_Z_T) | 110 (1u << ADDR_SW_64KB_S_T) | 111 (1u << ADDR_SW_64KB_D_T) | 112 (1u << ADDR_SW_64KB_R_T) | 113 (1u << ADDR_SW_64KB_Z_X) | 114 (1u << ADDR_SW_64KB_S_X) | 115 (1u << ADDR_SW_64KB_D_X) | 116 (1u << ADDR_SW_64KB_R_X); 117 118 const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) | 119 (1u << ADDR_SW_64KB_Z) | 120 (1u << ADDR_SW_64KB_Z_T) | 121 (1u << ADDR_SW_4KB_Z_X) | 122 (1u << ADDR_SW_64KB_Z_X); 123 124 const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) | 125 (1u << ADDR_SW_4KB_S) | 126 (1u << ADDR_SW_64KB_S) | 127 (1u << ADDR_SW_64KB_S_T) | 128 (1u << ADDR_SW_4KB_S_X) | 129 (1u << ADDR_SW_64KB_S_X); 130 131 const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 132 (1u << ADDR_SW_4KB_D) | 133 (1u << ADDR_SW_64KB_D) | 134 (1u << ADDR_SW_64KB_D_T) | 135 (1u << ADDR_SW_4KB_D_X) | 136 (1u << ADDR_SW_64KB_D_X); 137 138 const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) | 139 (1u << ADDR_SW_4KB_R) | 140 (1u << ADDR_SW_64KB_R) | 141 (1u << ADDR_SW_64KB_R_T) | 142 (1u << ADDR_SW_4KB_R_X) | 143 (1u << ADDR_SW_64KB_R_X); 144 145 const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) | 146 (1u << ADDR_SW_4KB_S_X) | 147 (1u << ADDR_SW_4KB_D_X) | 148 (1u << ADDR_SW_4KB_R_X) | 149 (1u << ADDR_SW_64KB_Z_X) | 150 (1u << ADDR_SW_64KB_S_X) | 151 (1u << ADDR_SW_64KB_D_X) | 152 (1u << ADDR_SW_64KB_R_X); 153 154 const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) | 155 (1u << ADDR_SW_64KB_S_T) | 156 (1u << ADDR_SW_64KB_D_T) | 157 (1u << ADDR_SW_64KB_R_T); 158 159 const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask | 160 Gfx9TSwModeMask; 161 162 const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask | 163 Gfx9ZSwModeMask | 164 Gfx9StandardSwModeMask | 165 Gfx9DisplaySwModeMask | 166 Gfx9RotateSwModeMask; 167 168 const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask; 169 170 const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask; 171 172 const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask; 173 174 const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask; 175 176 const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask; 177 178 const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask; 179 180 const UINT_32 Gfx9Rsrc3dThin4KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk4KBSwModeMask; 181 182 const UINT_32 Gfx9Rsrc3dThin64KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk64KBSwModeMask; 183 184 const UINT_32 Gfx9Rsrc3dThickSwModeMask = Gfx9Rsrc3dSwModeMask & ~(Gfx9Rsrc3dThinSwModeMask | Gfx9LinearSwModeMask); 185 186 const UINT_32 Gfx9Rsrc3dThick4KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk4KBSwModeMask; 187 188 const UINT_32 Gfx9Rsrc3dThick64KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk64KBSwModeMask; 189 190 const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask; 191 192 const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) | 193 (1u << ADDR_SW_4KB_D) | 194 (1u << ADDR_SW_4KB_R) | 195 (1u << ADDR_SW_64KB_D) | 196 (1u << ADDR_SW_64KB_R) | 197 (1u << ADDR_SW_4KB_D_X) | 198 (1u << ADDR_SW_4KB_R_X) | 199 (1u << ADDR_SW_64KB_D_X) | 200 (1u << ADDR_SW_64KB_R_X); 201 202 const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) | 203 (1u << ADDR_SW_256B_R) | 204 Dce12NonBpp32SwModeMask; 205 206 const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 207 (1u << ADDR_SW_4KB_S) | 208 (1u << ADDR_SW_64KB_S) | 209 (1u << ADDR_SW_64KB_S_T) | 210 (1u << ADDR_SW_4KB_S_X) | 211 (1u << ADDR_SW_64KB_S_X); 212 const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 213 (1u << ADDR_SW_64KB_D) | 214 (1u << ADDR_SW_64KB_D_T) | 215 (1u << ADDR_SW_4KB_D_X) | 216 (1u << ADDR_SW_64KB_D_X) | 217 Dcn1NonBpp64SwModeMask; 218 219 const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 220 (1u << ADDR_SW_64KB_S) | 221 (1u << ADDR_SW_64KB_S_T) | 222 (1u << ADDR_SW_64KB_S_X); 223 224 const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 225 (1u << ADDR_SW_64KB_D_T) | 226 (1u << ADDR_SW_64KB_D_X) | 227 Dcn2NonBpp64SwModeMask; 228 229 /** 230 ************************************************************************************************************************ 231 * @brief GFX9 meta equation parameters 232 ************************************************************************************************************************ 233 */ 234 struct MetaEqParams 235 { 236 UINT_32 maxMip; 237 UINT_32 elementBytesLog2; 238 UINT_32 numSamplesLog2; 239 ADDR2_META_FLAGS metaFlag; 240 Gfx9DataType dataSurfaceType; 241 AddrSwizzleMode swizzleMode; 242 AddrResourceType resourceType; 243 UINT_32 metaBlkWidthLog2; 244 UINT_32 metaBlkHeightLog2; 245 UINT_32 metaBlkDepthLog2; 246 UINT_32 compBlkWidthLog2; 247 UINT_32 compBlkHeightLog2; 248 UINT_32 compBlkDepthLog2; 249 }; 250 251 /** 252 ************************************************************************************************************************ 253 * @brief This class is the GFX9 specific address library 254 * function set. 255 ************************************************************************************************************************ 256 */ 257 class Gfx9Lib : public Lib 258 { 259 public: 260 /// Creates Gfx9Lib object CreateObj(const Client * pClient)261 static Addr::Lib* CreateObj(const Client* pClient) 262 { 263 VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient); 264 return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL; 265 } 266 267 protected: 268 Gfx9Lib(const Client* pClient); 269 virtual ~Gfx9Lib(); 270 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)271 virtual BOOL_32 HwlIsStandardSwizzle( 272 AddrResourceType resourceType, 273 AddrSwizzleMode swizzleMode) const 274 { 275 return m_swizzleModeTable[swizzleMode].isStd || 276 (IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp); 277 } 278 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)279 virtual BOOL_32 HwlIsDisplaySwizzle( 280 AddrResourceType resourceType, 281 AddrSwizzleMode swizzleMode) const 282 { 283 return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp; 284 } 285 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)286 virtual BOOL_32 HwlIsThin( 287 AddrResourceType resourceType, 288 AddrSwizzleMode swizzleMode) const 289 { 290 return ((IsTex2d(resourceType) == TRUE) || 291 ((IsTex3d(resourceType) == TRUE) && 292 (m_swizzleModeTable[swizzleMode].isZ == FALSE) && 293 (m_swizzleModeTable[swizzleMode].isStd == FALSE))); 294 } 295 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)296 virtual BOOL_32 HwlIsThick( 297 AddrResourceType resourceType, 298 AddrSwizzleMode swizzleMode) const 299 { 300 return (IsTex3d(resourceType) && 301 (m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd)); 302 } 303 304 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 305 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 306 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 307 308 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 309 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 310 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 311 312 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 313 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 314 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 315 316 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 317 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 318 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 319 320 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 321 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 322 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 323 324 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 325 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 326 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 327 328 virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord( 329 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 330 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 331 332 virtual UINT_32 HwlGetEquationIndex( 333 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 334 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 335 336 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 337 AddrResourceType rsrcType, 338 AddrSwizzleMode swMode, 339 UINT_32 elementBytesLog2, 340 ADDR_EQUATION* pEquation) const; 341 342 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 343 AddrResourceType rsrcType, 344 AddrSwizzleMode swMode, 345 UINT_32 elementBytesLog2, 346 ADDR_EQUATION* pEquation) const; 347 348 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 349 AddrResourceType rsrcType, 350 AddrSwizzleMode swMode, 351 UINT_32 elementBytesLog2, 352 ADDR_EQUATION* pEquation) const; 353 354 // Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)355 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 356 { 357 *ppEquationTable = m_equationTable; 358 359 return m_numEquations; 360 } 361 362 virtual BOOL_32 IsEquationSupported( 363 AddrResourceType rsrcType, 364 AddrSwizzleMode swMode, 365 UINT_32 elementBytesLog2) const; 366 367 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 368 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 369 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 370 371 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 372 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 373 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 374 375 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 376 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 377 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 378 379 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 380 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 381 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 382 383 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 384 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 385 386 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 387 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 388 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 389 390 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 391 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 392 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 393 394 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 395 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 396 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 397 398 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 399 400 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 401 402 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 403 404 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 405 406 virtual VOID ComputeThinBlockDimension( 407 UINT_32* pWidth, 408 UINT_32* pHeight, 409 UINT_32* pDepth, 410 UINT_32 bpp, 411 UINT_32 numSamples, 412 AddrResourceType resourceType, 413 AddrSwizzleMode swizzleMode) const; 414 415 private: 416 VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const; 417 418 VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType, 419 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 420 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const; 421 422 VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq, 423 UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2, 424 UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType, 425 AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const; 426 427 VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip, 428 UINT_32 elementBytesLog2, UINT_32 numSamplesLog2, 429 ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType, 430 AddrSwizzleMode swizzleMode, AddrResourceType resourceType, 431 UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2, 432 UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2, 433 UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const; 434 435 const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams); 436 437 VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim, 438 BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo, 439 UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth, 440 UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const; 441 442 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 443 444 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding( 445 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 446 UINT_32* pMipmap0PaddedWidth, 447 UINT_32* pSlice0PaddedHeight, 448 ADDR2_MIP_INFO* pMipInfo = NULL) const; 449 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)450 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 451 { 452 ADDR2_BLOCK_SET allowedBlockSet = {0}; 453 454 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE; 455 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE; 456 457 if (rsrcType == ADDR_RSRC_TEX_3D) 458 { 459 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin4KBSwModeMask) ? TRUE : FALSE; 460 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 461 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 462 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 463 } 464 else 465 { 466 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE; 467 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE; 468 } 469 470 return allowedBlockSet; 471 } 472 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)473 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 474 { 475 ADDR2_SWTYPE_SET allowedSwSet = {0}; 476 477 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE; 478 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE; 479 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE; 480 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE; 481 482 return allowedSwSet; 483 } 484 IsInMipTail(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,Dim3d mipTailDim,UINT_32 width,UINT_32 height,UINT_32 depth)485 BOOL_32 IsInMipTail( 486 AddrResourceType resourceType, 487 AddrSwizzleMode swizzleMode, 488 Dim3d mipTailDim, 489 UINT_32 width, 490 UINT_32 height, 491 UINT_32 depth) const 492 { 493 BOOL_32 inTail = ((width <= mipTailDim.w) && 494 (height <= mipTailDim.h) && 495 (IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d))); 496 497 return inTail; 498 } 499 500 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 501 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 502 GetBankXorBits(UINT_32 macroBlockBits)503 UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const 504 { 505 UINT_32 pipeBits = GetPipeXorBits(macroBlockBits); 506 507 // Bank xor bits 508 UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2); 509 510 return bankBits; 511 } 512 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode)513 UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const 514 { 515 UINT_32 baseAlign; 516 517 if (IsXor(swizzleMode)) 518 { 519 baseAlign = GetBlockSize(swizzleMode); 520 } 521 else 522 { 523 baseAlign = 256; 524 } 525 526 return baseAlign; 527 } 528 529 // Initialize equation table 530 VOID InitEquationTable(); 531 532 ADDR_E_RETURNCODE ComputeStereoInfo( 533 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 534 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 535 UINT_32* pHeightAlign) const; 536 537 UINT_32 GetMipChainInfo( 538 AddrResourceType resourceType, 539 AddrSwizzleMode swizzleMode, 540 UINT_32 bpp, 541 UINT_32 mip0Width, 542 UINT_32 mip0Height, 543 UINT_32 mip0Depth, 544 UINT_32 blockWidth, 545 UINT_32 blockHeight, 546 UINT_32 blockDepth, 547 UINT_32 numMipLevel, 548 ADDR2_MIP_INFO* pMipInfo) const; 549 550 VOID GetMetaMiptailInfo( 551 ADDR2_META_MIP_INFO* pInfo, 552 Dim3d mipCoord, 553 UINT_32 numMipInTail, 554 Dim3d* pMetaBlkDim) const; 555 556 Dim3d GetMipStartPos( 557 AddrResourceType resourceType, 558 AddrSwizzleMode swizzleMode, 559 UINT_32 width, 560 UINT_32 height, 561 UINT_32 depth, 562 UINT_32 blockWidth, 563 UINT_32 blockHeight, 564 UINT_32 blockDepth, 565 UINT_32 mipId, 566 UINT_32 log2ElementBytes, 567 UINT_32* pMipTailBytesOffset) const; 568 GetMajorMode(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 mip0WidthInBlk,UINT_32 mip0HeightInBlk,UINT_32 mip0DepthInBlk)569 AddrMajorMode GetMajorMode( 570 AddrResourceType resourceType, 571 AddrSwizzleMode swizzleMode, 572 UINT_32 mip0WidthInBlk, 573 UINT_32 mip0HeightInBlk, 574 UINT_32 mip0DepthInBlk) const 575 { 576 BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk); 577 BOOL_32 xMajor = (yMajor == FALSE); 578 579 if (IsThick(resourceType, swizzleMode)) 580 { 581 yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk); 582 xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk); 583 } 584 585 AddrMajorMode majorMode; 586 if (xMajor) 587 { 588 majorMode = ADDR_MAJOR_X; 589 } 590 else if (yMajor) 591 { 592 majorMode = ADDR_MAJOR_Y; 593 } 594 else 595 { 596 majorMode = ADDR_MAJOR_Z; 597 } 598 599 return majorMode; 600 } 601 GetDccCompressBlk(AddrResourceType resourceType,AddrSwizzleMode swizzleMode,UINT_32 bpp)602 Dim3d GetDccCompressBlk( 603 AddrResourceType resourceType, 604 AddrSwizzleMode swizzleMode, 605 UINT_32 bpp) const 606 { 607 UINT_32 index = Log2(bpp >> 3); 608 Dim3d compressBlkDim; 609 610 if (IsThin(resourceType, swizzleMode)) 611 { 612 compressBlkDim.w = Block256_2d[index].w; 613 compressBlkDim.h = Block256_2d[index].h; 614 compressBlkDim.d = 1; 615 } 616 else if (IsStandardSwizzle(resourceType, swizzleMode)) 617 { 618 compressBlkDim = Block256_3dS[index]; 619 } 620 else 621 { 622 compressBlkDim = Block256_3dZ[index]; 623 } 624 625 return compressBlkDim; 626 } 627 628 static const UINT_32 MaxSeLog2 = 3; 629 static const UINT_32 MaxRbPerSeLog2 = 2; 630 631 static const Dim3d Block256_3dS[MaxNumOfBpp]; 632 static const Dim3d Block256_3dZ[MaxNumOfBpp]; 633 634 static const UINT_32 MipTailOffset256B[]; 635 636 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 637 638 static const UINT_32 MaxCachedMetaEq = 2; 639 640 Gfx9ChipSettings m_settings; 641 642 CoordEq m_cachedMetaEq[MaxCachedMetaEq]; 643 MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq]; 644 UINT_32 m_metaEqOverrideIndex; 645 }; 646 647 } // V2 648 } // Addr 649 650 #endif 651 652