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Searched refs:SP (Results 1 – 16 of 16) sorted by relevance

/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc69 StoreToOffset(TR, SP, offset.Int32Value()); in GetCurrentThread()
76 AddConstant(SP, -adjust); in IncreaseFrameSize()
85 AddConstant(SP, adjust); in DecreaseFrameSize()
96 static_assert(WSP == static_cast<std::underlying_type_t<XRegister>>(SP)); in CoreRegisterWithSize()
156 CHECK_NE(source, SP); in StoreToOffset()
169 Store(Arm64ManagedRegister::FromXRegister(SP), MemberOffset(offs.Int32Value()), m_src, size); in Store()
197 StoreWToOffset(kStoreWord, src.AsOverlappingWRegister(), SP, in StoreRef()
204 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in StoreRawPtr()
211 ___ Str(scratch, MEM_OP(reg_x(SP), offs.Int32Value())); in StoreImmediateToFrame()
217 ___ Add(scratch, reg_x(SP), fr_offs.Int32Value()); in StoreStackOffsetToThread()
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Dmanaged_register_arm64_test.cc94 reg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
102 EXPECT_EQ(SP, reg.AsXRegister()); in TEST()
158 xreg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
297 Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromXRegister(SP); in TEST()
380 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
402 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
424 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
445 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
449 EXPECT_NE(SP, reg_o.AsOverlappingXRegister()); in TEST()
462 reg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
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Dmanaged_register_arm64.h187 return IsXRegister() && (id_ == SP); in IsStackPointer()
Dassembler_arm64.h165 if (code == SP) { in reg_x()
/art/runtime/arch/arm64/
Dcontext_arm64.cc40 gprs_[SP] = &sp_; in Reset()
44 sp_ = Arm64Context::kBadGprBase + SP; in Reset()
138 DCHECK_EQ(SP, 31); in DoLongJump()
149 __hwasan_handle_longjmp(reinterpret_cast<void*>(gprs[SP])); in DoLongJump()
Dcontext_arm64.h42 SetGPR(SP, new_sp); in SetSP()
Dregisters_arm64.h58 SP = 31, // SP and XZR are encoded in instructions using the register enumerator
/art/runtime/arch/arm/
Dcontext_arm.cc32 gprs_[SP] = &sp_; in Reset()
36 sp_ = ArmContext::kBadGprBase + SP; in Reset()
Dregisters_arm.h47 SP = 13, enumerator
Dcontext_arm.h42 SetGPR(SP, new_sp); in SetSP()
Dquick_entrypoints_arm.S478 mov sp, r0 @ Make SP point to gprs_.
479 @ Do not access fprs_ from now, they may be below SP.
483 ldr sp, [sp, #52] @ Load SP from gprs_ 52 = 4 * 13.
484 @ Do not access gprs_ from now, they are below SP.
1313 mov r3, sp @ pass SP
1314 blx artQuickProxyInvokeHandler @ (Method* proxy method, receiver, Thread*, SP)
1479 mov r2, sp @ pass SP
1480 blx artQuickToInterpreterBridge @ (Method* method, Thread*, SP)
2360 mov r2, sp @ r2 := SP
2361 bl artInvokePolymorphic @ artInvokePolymorphic(receiver, Thread*, SP)
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/art/compiler/optimizing/
Dcommon_arm64.h43 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
47 if (code == SP) { in VIXLRegCodeFromART()
58 return SP; in ARTRegCodeFromVIXL()
Dcommon_arm.h38 static_assert(vixl::aarch32::kSpCode == SP, "vixl::aarch32::kSpCode must equal ART's SP");
Dcode_generator_arm_vixl.cc2100 blocked_core_registers_[SP] = true; in SetupBlockedRegisters()
/art/libnativeloader/
DREADME.md32 with the [VNDK-SP](https://source.android.com/devices/architecture/vndk#sp-hal)
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc277 Store(ArmManagedRegister::FromCoreRegister(SP), MemberOffset(dest.Int32Value()), m_src, size); in Store()