Searched refs:core_spill_mask_ (Results 1 – 10 of 10) sorted by relevance
| /art/runtime/quick/ |
| D | quick_method_frame_info.h | 30 core_spill_mask_(0u), in QuickMethodFrameInfo()
37 core_spill_mask_(core_spill_mask), in QuickMethodFrameInfo()
46 return core_spill_mask_; in CoreSpillMask()
59 uint32_t core_spill_mask_; variable
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| /art/compiler/jni/quick/ |
| D | jni_compiler.h | 43 core_spill_mask_(core_spill_mask), in JniCompiledMethod()
53 uint32_t GetCoreSpillMask() const { return core_spill_mask_; } in GetCoreSpillMask()
61 uint32_t core_spill_mask_; variable
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| /art/runtime/ |
| D | stack_map.h | 301 code_info.core_spill_mask_, in DecodeFrameInfo()
468 callback(index++, &CodeInfo::core_spill_mask_); in ForEachHeaderField()
505 uint32_t core_spill_mask_ = 0; variable
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| D | stack_map.cc | 208 << " CoreSpillMask:" << std::hex << core_spill_mask_ in Dump()
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| /art/compiler/optimizing/ |
| D | stack_map_stream.cc | 59 core_spill_mask_ = core_spill_mask; in BeginMethod()
67 DCHECK_EQ(code_info.core_spill_mask_, core_spill_mask); in BeginMethod()
384 core_spill_mask_, in Encode()
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| D | code_generator.h | 255 uint32_t GetCoreSpillMask() const { return core_spill_mask_; } in GetCoreSpillMask()
263 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; in ComputeSpillMask()
264 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; in ComputeSpillMask()
755 return POPCOUNT(core_spill_mask_) * GetWordSize(); in GetCoreSpillSize()
807 uint32_t core_spill_mask_; variable
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| D | stack_map_stream.h | 124 uint32_t core_spill_mask_ = 0; variable
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| D | code_generator.cc | 389 core_spill_mask_, in Compile()
1046 core_spill_mask_(0), in CodeGenerator()
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| D | code_generator_arm_vixl.cc | 2134 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; in ComputeSpillMask()
2135 DCHECK_NE(core_spill_mask_ & (1u << kLrCode), 0u) in ComputeSpillMask()
2285 DCHECK_LT(MostSignificantBit(extra_regs), LeastSignificantBit(core_spill_mask_)); in GenerateFrameEntry()
2286 __ Push(RegisterList(core_spill_mask_ | extra_regs)); in GenerateFrameEntry()
2290 core_spill_mask_, in GenerateFrameEntry()
2299 __ Push(RegisterList(core_spill_mask_)); in GenerateFrameEntry()
2300 GetAssembler()->cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(core_spill_mask_)); in GenerateFrameEntry()
2303 core_spill_mask_, in GenerateFrameEntry()
2353 DCHECK_NE(core_spill_mask_ & (1 << kLrCode), 0U); in GenerateFrameExit()
2354 uint32_t pop_mask = (core_spill_mask_ & (~(1 << kLrCode))) | 1 << kPcCode; in GenerateFrameExit()
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| D | code_generator_arm64.cc | 1338 DCHECK(ArtVixlRegCodeCoherentForRegSet(core_spill_mask_, GetNumberOfCoreRegisters(), 0, 0)); in GetFramePreservedCoreRegisters()
1340 core_spill_mask_); in GetFramePreservedCoreRegisters()
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