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Searched refs:logic (Results 1 – 25 of 36) sorted by relevance

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/device/generic/goldfish/sepolicy/common/
Ddlkm_loader.te17 # Needed because CONFIG_USB_DUMMY_HCD adds some additional logic to
/device/generic/vulkan-cereal/third-party/angle/src/third_party/volk/
DREADME.md24 …sible to set the platform defines mentioned above with arbitrary (preprocessor) logic in your code.
93 /* ...any logic setting VK_USE_PLATFORM_WIN32_KHR and friends... */
/device/generic/vulkan-cereal/third-party/googletest/docs/
Dsamples.md14 * Sample #5 puts shared testing logic in a base test fixture, and reuses it in
Dfaq.md228 In googletest, you share a fixture among test suites by putting the shared logic
230 test suite that wants to use this common logic. You then use `TEST_F()` to write
313 When you need to write per-test set-up and tear-down logic, you have the choice
413 ## I have several test suites which share the same test fixture logic, do I have to define a new te…
624 things accordingly, you are leaking test-only logic into production code and
633 production code doesn't link in the for-test logic at all (the
Dadvanced.md922 // You can define per-test set-up logic as usual.
925 // You can define per-test tear-down logic as usual.
1230 verify it. In both cases, you want the same test logic repeated for different
1234 you may even factor the test logic into a function template that you invoke from
1238 *Typed tests* allow you to repeat the same test logic over a list of types. You
1239 only need to write the test logic once, although you must know the type list
1301 logic first and instantiate it with different type lists later. You can even
1537 where runtime registration logic is required. For those cases, the framework
Dgmock_cook_book.md1668 This pattern is also useful when the arguments are interesting, but match logic
3106 unless required by your test logic.
3128 interleave. If this is a problem, you should add proper synchronization logic to
3843 in new code; they hide a lot of logic behind the macro, potentially leading to
/device/amlogic/yukawa/hal/hdmicec/
DAndroid.bp21 // are responsible for having their own logic, for fine-grained control.
/device/google/cuttlefish/guest/hals/confirmationui/
DAndroid.bp20 // are responsible for having their own logic, for fine-grained control.
/device/generic/vulkan-cereal/protocols/vulkan/appendices/
DVK_FUCHSIA_buffer_collection.txt54 simplifies the implied logic of the implementation and expectations for the
DVK_NV_corner_sampled_image.txt45 Additionally, using the modified mipmapping logic along with texture
DVK_AMD_rasterization_order.txt31 * blending, logic op, and color write
DVK_NV_mesh_shader.txt33 assembly and rasterization logic.
DVK_NV_shader_image_footprint.txt182 * Have logic that detects returned footprints where all components of the
/device/generic/vulkan-cereal/protocols/vulkan/config/
Dattribs.txt26 // Math operators and logic symbols
/device/generic/vulkan-cereal/third-party/angle/src/libANGLE/renderer/vulkan/
Dvk_cache_utils.cpp586 inputAndBlend.logic.opEnable = 0; in initDefaults()
587 inputAndBlend.logic.op = static_cast<uint32_t>(VK_LOGIC_OP_CLEAR); in initDefaults()
892 blendState.logicOpEnable = static_cast<VkBool32>(inputAndBlend.logic.opEnable); in initializePipeline()
893 blendState.logicOp = static_cast<VkLogicOp>(inputAndBlend.logic.op); in initializePipeline()
Dvk_cache_utils.h315 LogicOpState logic; member
/device/generic/vulkan-cereal/third-party/angle/doc/
DUpdate20120704.md37 for short-circuiting boolean logic operations. In GLSL, Boolean expressions do
/device/google/coral/
DWCNSS_qcom_cfg.ini351 # Set channel selection logic for different concurrency combinations to DBS or inter band MCC.
/device/google/sunfish/
DWCNSS_qcom_cfg.ini351 # Set channel selection logic for different concurrency combinations to DBS or inter band MCC.
/device/google/redbull/
DWCNSS_qcom_cfg.ini364 # Set channel selection logic for different concurrency combinations to DBS or inter band MCC.
/device/generic/vulkan-cereal/protocols/vulkan/xml/
Dregistry.rnc546 # to the asciidoctor conditional logic in the spec. For version and
/device/generic/vulkan-cereal/third-party/angle/src/tests/
DBUILD.gn734 "$gles1_conform_root/conform/primtest/logic.c",
/device/generic/vulkan-cereal/protocols/vulkan/chapters/
Dframebuffer.txt98 If the <<features-logicOp,logic operations>> feature is not enabled,
Ddrawing.txt1221 // Jon: conditional logic on connective clauses with 3 forms of the command including VK_VERSION_1_…
1389 // Jon: conditional logic on connective clauses with 3 forms of the command including VK_VERSION_1_…
/device/generic/vulkan-cereal/protocols/vulkan/
DChangeLog.txt278 `[open]` blocks to bypass logic problem with VUID assignment script
371 * Update `-validate` logic in registry scripts to validate the `limittype`
3845 * Fix broken asciidoctor conditional logic in the
4663 * Fix reversed logic of slink:VkFormatProperties discussion of multi-plane
8071 logic error in reflib.py which could cause a fatal error for
8514 * Fix +vk_platform.h+ conditional logic causing compile failure with some
8958 * Add logic to generate spec boilerplate without using the 'git'

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