Searched refs:SelectOpcode (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3055 auto SelectOpcode = [&](unsigned Opc64, unsigned Opc32, unsigned Opc16, in foldLoadStoreIntoMemOperand() local
3076 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, in foldLoadStoreIntoMemOperand()
3093 ? SelectOpcode(X86::INC64m, X86::INC32m, X86::INC16m, X86::INC8m) in foldLoadStoreIntoMemOperand()
3094 : SelectOpcode(X86::DEC64m, X86::DEC32m, X86::DEC16m, X86::DEC8m); in foldLoadStoreIntoMemOperand()
3107 auto SelectRegOpcode = [SelectOpcode](unsigned Opc) { in foldLoadStoreIntoMemOperand()
3110 return SelectOpcode(X86::ADD64mr, X86::ADD32mr, X86::ADD16mr, in foldLoadStoreIntoMemOperand()
3113 return SelectOpcode(X86::ADC64mr, X86::ADC32mr, X86::ADC16mr, in foldLoadStoreIntoMemOperand()
3116 return SelectOpcode(X86::SUB64mr, X86::SUB32mr, X86::SUB16mr, in foldLoadStoreIntoMemOperand()
3119 return SelectOpcode(X86::SBB64mr, X86::SBB32mr, X86::SBB16mr, in foldLoadStoreIntoMemOperand()
3122 return SelectOpcode(X86::AND64mr, X86::AND32mr, X86::AND16mr, in foldLoadStoreIntoMemOperand()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 461 CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode, in CmpConstants()
464 SelectResultOpcode(SelectOpcode), OperandRegBankID(OpRegBank), in CmpConstants()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 1182 unsigned SelectOpcode = Size == 64 ? AMDGPU::S_CSELECT_B64 : in selectG_SELECT() local
1192 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg) in selectG_SELECT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 6039 auto SelectOpcode = [&](unsigned NeededShift, unsigned MulOrDivVariant) { in extractShiftForRotate() local
6048 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
6049 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 29892 auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT; in combineFMinNumFMaxNum() local
29893 return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, MinOrMax); in combineFMinNumFMaxNum()
|