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/external/llvm/test/CodeGen/ARM/
Dvaba.ll10 %tmp5 = add <8 x i8> %tmp1, %tmp4
11 ret <8 x i8> %tmp5
21 %tmp5 = add <4 x i16> %tmp1, %tmp4
22 ret <4 x i16> %tmp5
32 %tmp5 = add <2 x i32> %tmp1, %tmp4
33 ret <2 x i32> %tmp5
43 %tmp5 = add <8 x i8> %tmp1, %tmp4
44 ret <8 x i8> %tmp5
54 %tmp5 = add <4 x i16> %tmp1, %tmp4
55 ret <4 x i16> %tmp5
[all …]
Dvmla.ll10 %tmp5 = add <8 x i8> %tmp1, %tmp4
11 ret <8 x i8> %tmp5
21 %tmp5 = add <4 x i16> %tmp1, %tmp4
22 ret <4 x i16> %tmp5
32 %tmp5 = add <2 x i32> %tmp1, %tmp4
33 ret <2 x i32> %tmp5
43 %tmp5 = fadd <2 x float> %tmp1, %tmp4
44 ret <2 x float> %tmp5
54 %tmp5 = add <16 x i8> %tmp1, %tmp4
55 ret <16 x i8> %tmp5
[all …]
Dvmls.ll10 %tmp5 = sub <8 x i8> %tmp1, %tmp4
11 ret <8 x i8> %tmp5
21 %tmp5 = sub <4 x i16> %tmp1, %tmp4
22 ret <4 x i16> %tmp5
32 %tmp5 = sub <2 x i32> %tmp1, %tmp4
33 ret <2 x i32> %tmp5
43 %tmp5 = fsub <2 x float> %tmp1, %tmp4
44 ret <2 x float> %tmp5
54 %tmp5 = sub <16 x i8> %tmp1, %tmp4
55 ret <16 x i8> %tmp5
[all …]
Duxtb.ll37 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
38 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
46 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
47 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
54 %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
55 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
62 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
63 %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
71 %tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1]
72 %tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
Dvldlane.ll108 %tmp5 = add <8 x i8> %tmp3, %tmp4
109 ret <8 x i8> %tmp5
121 %tmp5 = add <4 x i16> %tmp3, %tmp4
122 ret <4 x i16> %tmp5
133 %tmp5 = add <2 x i32> %tmp3, %tmp4
134 ret <2 x i32> %tmp5
147 %tmp5 = add <2 x i32> %tmp3, %tmp4
150 ret <2 x i32> %tmp5
161 %tmp5 = fadd <2 x float> %tmp3, %tmp4
162 ret <2 x float> %tmp5
[all …]
/external/llvm/test/CodeGen/X86/
D2007-03-15-GEP-Idx-Sink.ll16 %tmp5.sum72 = add i32 %col, 7 ; <i32> [#uses=1]
17 %tmp5.sum71 = add i32 %col, 5 ; <i32> [#uses=1]
18 %tmp5.sum70 = add i32 %col, 3 ; <i32> [#uses=1]
19 %tmp5.sum69 = add i32 %col, 2 ; <i32> [#uses=1]
20 %tmp5.sum68 = add i32 %col, 1 ; <i32> [#uses=1]
21 %tmp5.sum66 = add i32 %col, 4 ; <i32> [#uses=1]
22 %tmp5.sum = add i32 %col, 6 ; <i32> [#uses=1]
31 %tmp5 = getelementptr i8, i8* %tmp3, i32 %col ; <i8*> [#uses=1]
33 store i8 %tmp7, i8* %tmp5
37 %tmp15 = getelementptr i8, i8* %tmp3, i32 %tmp5.sum72 ; <i8*> [#uses=1]
[all …]
Davx1-logical-load-folding.ll12 %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
13 %tmp6 = extractelement <8 x float> %tmp5, i32 0
26 %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
27 %tmp6 = extractelement <8 x float> %tmp5, i32 0
40 %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
41 %tmp6 = extractelement <8 x float> %tmp5, i32 0
53 …%tmp5 = and <8 x i32> %tmp4, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 …
54 %tmp6 = bitcast <8 x i32> %tmp5 to <8 x float>
/external/llvm/test/CodeGen/AArch64/
Darm64-trn.ll12 %tmp5 = add <8 x i8> %tmp3, %tmp4
13 ret <8 x i8> %tmp5
25 %tmp5 = add <4 x i16> %tmp3, %tmp4
26 ret <4 x i16> %tmp5
39 %tmp5 = add <2 x i32> %tmp3, %tmp4
40 ret <2 x i32> %tmp5
52 %tmp5 = fadd <2 x float> %tmp3, %tmp4
53 ret <2 x float> %tmp5
65 %tmp5 = add <16 x i8> %tmp3, %tmp4
66 ret <16 x i8> %tmp5
[all …]
Daarch64-smull.ll10 %tmp5 = mul <8 x i16> %tmp3, %tmp4
11 ret <8 x i16> %tmp5
21 %tmp5 = mul <4 x i32> %tmp3, %tmp4
22 ret <4 x i32> %tmp5
32 %tmp5 = mul <2 x i64> %tmp3, %tmp4
33 ret <2 x i64> %tmp5
43 %tmp5 = mul <8 x i16> %tmp3, %tmp4
44 ret <8 x i16> %tmp5
54 %tmp5 = mul <4 x i32> %tmp3, %tmp4
55 ret <4 x i32> %tmp5
[all …]
Darm64-zip.ll12 %tmp5 = add <8 x i8> %tmp3, %tmp4
13 ret <8 x i8> %tmp5
25 %tmp5 = add <4 x i16> %tmp3, %tmp4
26 ret <4 x i16> %tmp5
38 %tmp5 = add <16 x i8> %tmp3, %tmp4
39 ret <16 x i8> %tmp5
51 %tmp5 = add <8 x i16> %tmp3, %tmp4
52 ret <8 x i16> %tmp5
64 %tmp5 = add <4 x i32> %tmp3, %tmp4
65 ret <4 x i32> %tmp5
[all …]
Darm64-uzp.ll12 %tmp5 = add <8 x i8> %tmp3, %tmp4
13 ret <8 x i8> %tmp5
25 %tmp5 = add <4 x i16> %tmp3, %tmp4
26 ret <4 x i16> %tmp5
38 %tmp5 = add <16 x i8> %tmp3, %tmp4
39 ret <16 x i8> %tmp5
51 %tmp5 = add <8 x i16> %tmp3, %tmp4
52 ret <8 x i16> %tmp5
64 %tmp5 = add <4 x i32> %tmp3, %tmp4
65 ret <4 x i32> %tmp5
[all …]
/external/llvm/test/Transforms/InstCombine/
Dapint-cast.ll10 %tmp5 = shl i37 %tmp, 8 ; <i37> [#uses=1]
11 ; CHECK: %tmp5 = shl i17 %a, 8
12 %tmp.upgrd.32 = or i37 %tmp21, %tmp5 ; <i37> [#uses=1]
13 ; CHECK: %tmp.upgrd.32 = or i17 %tmp21, %tmp5
23 %tmp5 = shl i577 %tmp, 8 ; <i577> [#uses=1]
24 ; CHECK: %tmp5 = shl i167 %a, 8
25 %tmp.upgrd.32 = or i577 %tmp21, %tmp5 ; <i577> [#uses=1]
26 ; CHECK: %tmp.upgrd.32 = or i167 %tmp21, %tmp5
Dbswap.ll11 %tmp5 = or i32 %tmp1, %tmp4
14 %tmp9 = or i32 %tmp5, %tmp8
25 %tmp5 = and i32 %tmp4, 16711680
26 %tmp6 = or i32 %tmp2, %tmp5
40 %tmp5 = or i16 %tmp2, %tmp4
41 ret i16 %tmp5
49 %tmp5 = or i16 %tmp4, %tmp2
50 ret i16 %tmp5
61 %tmp5 = shl i32 %tmp4, 8
62 %tmp5.upgrd.2 = trunc i32 %tmp5 to i16
[all …]
/external/libjpeg-turbo/
Djfdctint.c145 JLONG tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
163 tmp5 = dataptr[2] - dataptr[5];
191 z2 = tmp5 + tmp6;
193 z4 = tmp5 + tmp7;
197 tmp5 = MULTIPLY(tmp5, FIX_2_053119869); /* sqrt(2) * ( c1+c3-c5+c7) */
209 dataptr[5] = (DCTELEM)DESCALE(tmp5 + z2 + z4, CONST_BITS - PASS1_BITS);
228 tmp5 = dataptr[DCTSIZE * 2] - dataptr[DCTSIZE * 5];
258 z2 = tmp5 + tmp6;
260 z4 = tmp5 + tmp7;
264 tmp5 = MULTIPLY(tmp5, FIX_2_053119869); /* sqrt(2) * ( c1+c3-c5+c7) */
[all …]
Djidctflt.c76 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
147 tmp5 = DEQUANTIZE(inptr[DCTSIZE * 3], quantptr[DCTSIZE * 3] * _0_125);
151 z13 = tmp6 + tmp5; /* phase 6 */
152 z10 = tmp6 - tmp5;
164 tmp5 = tmp11 - tmp6;
165 tmp4 = tmp10 - tmp5;
171 wsptr[DCTSIZE * 2] = tmp2 + tmp5;
172 wsptr[DCTSIZE * 5] = tmp2 - tmp5;
222 tmp5 = tmp11 - tmp6;
223 tmp4 = tmp10 - tmp5;
[all …]
Djidctfst.c175 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
246 tmp5 = DEQUANTIZE(inptr[DCTSIZE * 3], quantptr[DCTSIZE * 3]);
250 z13 = tmp6 + tmp5; /* phase 6 */
251 z10 = tmp6 - tmp5;
263 tmp5 = tmp11 - tmp6;
264 tmp4 = tmp10 + tmp5;
270 wsptr[DCTSIZE * 2] = (int)(tmp2 + tmp5);
271 wsptr[DCTSIZE * 5] = (int)(tmp2 - tmp5);
345 tmp5 = tmp11 - tmp6;
346 tmp4 = tmp10 + tmp5;
[all …]
Djfdctflt.c62 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
77 tmp5 = dataptr[2] - dataptr[5];
97 tmp10 = tmp4 + tmp5; /* phase 2 */
98 tmp11 = tmp5 + tmp6;
127 tmp5 = dataptr[DCTSIZE * 2] - dataptr[DCTSIZE * 5];
147 tmp10 = tmp4 + tmp5; /* phase 2 */
148 tmp11 = tmp5 + tmp6;
/external/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dno-return-blocks.ll3 ; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
4 ; CHECK: DIVERGENT: %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
5 ; CHECK: DIVERGENT: %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
12 %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
13 %tmp6 = load volatile float, float addrspace(1)* %tmp5, align 4
18 %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
22 %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
/external/llvm/test/Transforms/Reassociate/
Drepeats.ll71 %tmp5 = mul i3 %tmp4, %x
72 ret i3 %tmp5
85 %tmp5 = mul i3 %tmp4, %x
86 %tmp6 = mul i3 %tmp5, %x
100 %tmp5 = mul i4 %tmp4, %x
101 %tmp6 = mul i4 %tmp5, %x
117 %tmp5 = mul i4 %tmp4, %x
118 %tmp6 = mul i4 %tmp5, %x
135 %tmp5 = mul i4 %tmp4, %x
136 %tmp6 = mul i4 %tmp5, %x
[all …]
/external/llvm/test/Analysis/BasicAA/
Dfull-store-partial-alias.ll6 ; so the %tmp5 load is PartialAlias with the store and suppress TBAA.
7 ; Without BasicAA, TBAA should say that %tmp5 is NoAlias with the store.
17 ; BASICAA: ret i32 %tmp5.lobit
27 %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
28 %tmp5.lobit = lshr i32 %tmp5, 31
29 ret i32 %tmp5.lobit
/external/libjpeg-turbo/simd/arm/
Djidctfst-neon.c148 int16x4_t tmp5 = vmul_s16(vget_high_s16(row3), quant_row3); in jsimd_idct_ifast_neon() local
152 int16x4_t z13 = vadd_s16(tmp6, tmp5); /* phase 6 */ in jsimd_idct_ifast_neon()
153 int16x4_t neg_z10 = vsub_s16(tmp5, tmp6); in jsimd_idct_ifast_neon()
173 tmp5 = vsub_s16(tmp11, tmp6); in jsimd_idct_ifast_neon()
174 tmp4 = vadd_s16(tmp10, tmp5); in jsimd_idct_ifast_neon()
180 row2 = vcombine_s16(dcval, vadd_s16(tmp2, tmp5)); in jsimd_idct_ifast_neon()
181 row5 = vcombine_s16(dcval, vsub_s16(tmp2, tmp5)); in jsimd_idct_ifast_neon()
223 int16x4_t tmp5 = vmul_s16(vget_low_s16(row3), quant_row3); in jsimd_idct_ifast_neon() local
227 int16x4_t z13 = vadd_s16(tmp6, tmp5); /* phase 6 */ in jsimd_idct_ifast_neon()
228 int16x4_t neg_z10 = vsub_s16(tmp5, tmp6); in jsimd_idct_ifast_neon()
[all …]
/external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dfull-store-partial-alias.ll6 ; so the %tmp5 load is PartialAlias with the store and suppress TBAA.
8 ; Without CFL AA, TBAA should say that %tmp5 is NoAlias with the store.
18 ; FIXME: This would be ret i32 %tmp5.lobit if CFLSteensAA could prove PartialAlias
29 %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
30 %tmp5.lobit = lshr i32 %tmp5, 31
31 ret i32 %tmp5.lobit
/external/libyuv/files/source/
Drotate_mmi.cc27 uint64_t tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; in TransposeWx8_MMI() local
139 [tmp3] "=&f"(tmp3), [tmp4] "=&f"(tmp4), [tmp5] "=&f"(tmp5), in TransposeWx8_MMI()
156 uint64_t tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; in TransposeUVWx8_MMI() local
276 [tmp3] "=&f"(tmp3), [tmp4] "=&f"(tmp4), [tmp5] "=&f"(tmp5), in TransposeUVWx8_MMI()
/external/webrtc/common_audio/signal_processing/
Dcomplex_fft_mips.c34 int32_t tmp5 = 0; in WebRtcSpl_ComplexFFT() local
137 [tmp4] "=&r" (tmp4), [tmp5] "=&r" (tmp5), [tmp6] "=&r" (tmp6), in WebRtcSpl_ComplexFFT()
157 int32_t tmp5 = 0, tmp6 = 0, tmp = 0, tempMax = 0, round2 = 0; in WebRtcSpl_ComplexIFFT() local
314 [tmp4] "=&r" (tmp4), [tmp5] "=&r" (tmp5), [tmp6] "=&r" (tmp6), in WebRtcSpl_ComplexIFFT()
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_estimator_mips.c34 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
79 [tmp4] "=&r" (tmp4), [tmp5] "=&r" (tmp5), [tmp6] "=&r" (tmp6), in WebRtcIsacfix_PCorr2Q32()
105 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
171 [tmp4] "=&r" (tmp4), [tmp5] "=&r" (tmp5), [tmp6] "=&r" (tmp6), in WebRtcIsacfix_PCorr2Q32()

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