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/external/llvm/test/CodeGen/X86/
Dfield-extract-use-trunc.ll5 %tmp7.25 = lshr i32 %f12, 16
6 %tmp7.26 = trunc i32 %tmp7.25 to i8
7 %tmp78.2 = sext i8 %tmp7.26 to i32
13 %tmp7.25 = ashr i32 %f11, 24
14 ret i32 %tmp7.25
19 %tmp7.25 = ashr i32 %f11, 24
20 ret i32 %tmp7.25
25 %tmp7.25 = ashr i64 %f11, 32
26 ret i64 %tmp7.25
31 %tmp7.25 = ashr i16 %f11, 8
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Drv7x0_count3.ll13 %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 3
14 %tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
16 …%tmp10 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
18 …%tmp12 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
20 …%tmp14 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
22 …%tmp16 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
24 …%tmp18 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
26 …%tmp20 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
28 …%tmp22 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
30 …%tmp24 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
[all …]
/external/llvm/test/Transforms/InstCombine/
Dand-xor-merge.ll7 ; CHECK-NEXT: %tmp7 = and i32 %tmp61, %z
8 ; CHECK-NEXT: ret i32 %tmp7
11 %tmp7 = xor i32 %tmp3, %tmp6
12 ret i32 %tmp7
18 ; CHECK-NEXT: %tmp7 = xor i32 %y, %x
19 ; CHECK-NEXT: ret i32 %tmp7
22 %tmp7 = xor i32 %tmp3, %tmp6
23 ret i32 %tmp7
Dand-or-not.ll11 %tmp7 = or i32 %tmp6, %tmp3not ; <i32> [#uses=1]
12 %tmp7not = xor i32 %tmp7, -1 ; <i32> [#uses=1]
24 %tmp7 = and i32 %tmp3, %tmp6not ; <i32> [#uses=1]
25 ret i32 %tmp7
36 %tmp7 = or <4 x i32> %tmp6, %tmp3not ; <<4 x i32>> [#uses=1]
37 …%tmp7not = xor <4 x i32> %tmp7, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#us…
49 %tmp7 = and <4 x i32> %tmp3, %tmp6not ; <<4 x i32>> [#uses=1]
50 ret <4 x i32> %tmp7
/external/llvm/test/CodeGen/ARM/
Dvbsl-constant.ll13 %tmp7 = or <8 x i8> %tmp4, %tmp6
14 ret <8 x i8> %tmp7
27 %tmp7 = or <4 x i16> %tmp4, %tmp6
28 ret <4 x i16> %tmp7
41 %tmp7 = or <2 x i32> %tmp4, %tmp6
42 ret <2 x i32> %tmp7
56 %tmp7 = or <1 x i64> %tmp4, %tmp6
57 ret <1 x i64> %tmp7
70 %tmp7 = or <16 x i8> %tmp4, %tmp6
71 ret <16 x i8> %tmp7
[all …]
/external/libjpeg-turbo/
Djfdctint.c145 JLONG tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
159 tmp7 = dataptr[0] - dataptr[7];
190 z1 = tmp4 + tmp7;
193 z4 = tmp5 + tmp7;
199 tmp7 = MULTIPLY(tmp7, FIX_1_501321110); /* sqrt(2) * ( c1+c3-c5-c7) */
211 dataptr[1] = (DCTELEM)DESCALE(tmp7 + z1 + z4, CONST_BITS - PASS1_BITS);
224 tmp7 = dataptr[DCTSIZE * 0] - dataptr[DCTSIZE * 7];
257 z1 = tmp4 + tmp7;
260 z4 = tmp5 + tmp7;
266 tmp7 = MULTIPLY(tmp7, FIX_1_501321110); /* sqrt(2) * ( c1+c3-c5-c7) */
[all …]
Djidctflt.c76 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
149 tmp7 = DEQUANTIZE(inptr[DCTSIZE * 7], quantptr[DCTSIZE * 7] * _0_125);
153 z11 = tmp4 + tmp7;
154 z12 = tmp4 - tmp7;
156 tmp7 = z11 + z13; /* phase 5 */
163 tmp6 = tmp12 - tmp7; /* phase 2 */
167 wsptr[DCTSIZE * 0] = tmp0 + tmp7;
168 wsptr[DCTSIZE * 7] = tmp0 - tmp7;
214 tmp7 = z11 + z13;
221 tmp6 = tmp12 - tmp7;
[all …]
Djfdctflt.c62 FAST_FLOAT tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
73 tmp7 = dataptr[0] - dataptr[7];
99 tmp12 = tmp6 + tmp7;
107 z11 = tmp7 + z3; /* phase 5 */
108 z13 = tmp7 - z3;
123 tmp7 = dataptr[DCTSIZE * 0] - dataptr[DCTSIZE * 7];
149 tmp12 = tmp6 + tmp7;
157 z11 = tmp7 + z3; /* phase 5 */
158 z13 = tmp7 - z3;
Djfdctfst.c119 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
131 tmp7 = dataptr[0] - dataptr[7];
157 tmp12 = tmp6 + tmp7;
165 z11 = tmp7 + z3; /* phase 5 */
166 z13 = tmp7 - z3;
181 tmp7 = dataptr[DCTSIZE * 0] - dataptr[DCTSIZE * 7];
207 tmp12 = tmp6 + tmp7;
215 z11 = tmp7 + z3; /* phase 5 */
216 z13 = tmp7 - z3;
Djidctfst.c175 DCTELEM tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; variable
248 tmp7 = DEQUANTIZE(inptr[DCTSIZE * 7], quantptr[DCTSIZE * 7]);
252 z11 = tmp4 + tmp7;
253 z12 = tmp4 - tmp7;
255 tmp7 = z11 + z13; /* phase 5 */
262 tmp6 = tmp12 - tmp7; /* phase 2 */
266 wsptr[DCTSIZE * 0] = (int)(tmp0 + tmp7);
267 wsptr[DCTSIZE * 7] = (int)(tmp0 - tmp7);
337 tmp7 = z11 + z13; /* phase 5 */
344 tmp6 = tmp12 - tmp7; /* phase 2 */
[all …]
/external/libjpeg-turbo/simd/arm/
Djidctfst-neon.c150 int16x4_t tmp7 = vmul_s16(vget_high_s16(row7), quant_row7); in jsimd_idct_ifast_neon() local
154 int16x4_t z11 = vadd_s16(tmp4, tmp7); in jsimd_idct_ifast_neon()
155 int16x4_t z12 = vsub_s16(tmp4, tmp7); in jsimd_idct_ifast_neon()
157 tmp7 = vadd_s16(z11, z13); /* phase 5 */ in jsimd_idct_ifast_neon()
172 tmp6 = vsub_s16(tmp12, tmp7); /* phase 2 */ in jsimd_idct_ifast_neon()
176 row0 = vcombine_s16(dcval, vadd_s16(tmp0, tmp7)); in jsimd_idct_ifast_neon()
177 row7 = vcombine_s16(dcval, vsub_s16(tmp0, tmp7)); in jsimd_idct_ifast_neon()
225 int16x4_t tmp7 = vmul_s16(vget_low_s16(row7), quant_row7); in jsimd_idct_ifast_neon() local
229 int16x4_t z11 = vadd_s16(tmp4, tmp7); in jsimd_idct_ifast_neon()
230 int16x4_t z12 = vsub_s16(tmp4, tmp7); in jsimd_idct_ifast_neon()
[all …]
/external/libyuv/files/source/
Drotate_mmi.cc28 uint64_t tmp7, tmp8, tmp9, tmp10, tmp11, tmp12, tmp13; in TransposeWx8_MMI() local
140 [tmp6] "=&f"(tmp6), [tmp7] "=&f"(tmp7), [tmp8] "=&f"(tmp8), in TransposeWx8_MMI()
157 uint64_t tmp7, tmp8, tmp9, tmp10, tmp11, tmp12, tmp13; in TransposeUVWx8_MMI() local
277 [tmp6] "=&f"(tmp6), [tmp7] "=&f"(tmp7), [tmp8] "=&f"(tmp8), in TransposeUVWx8_MMI()
/external/llvm/test/Transforms/IndVarSimplify/
Dada-loops.ll46 %i.0.reg2mem.0 = phi i8 [ 0, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=1]
47 %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
48 %tmp1 = zext i8 %tmp7 to i32 ; <i32> [#uses=1]
51 %0 = icmp eq i8 %tmp7, -1 ; <i1> [#uses=1]
63 %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
68 %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
69 %0 = icmp sgt i8 %tmp7, 10 ; <i1> [#uses=1]
81 %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
86 %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
87 %0 = icmp sgt i8 %tmp7, 30 ; <i1> [#uses=1]
/external/llvm/test/Transforms/GVN/
Dload-pre-licm.ll9 ; CHECK-NEXT: %tmp7.pre = load i32
14 ; CHECK: %tmp7 = phi i32
15 ; CHECK-NOT: %tmp7 = load i32
22 %tmp7 = load i32, i32* %arrayidx, align 4
24 %cmp11 = icmp sgt i32 %tmp7, %tmp10
30 store i32 %tmp7, i32* %arrayidx9, align 4
/external/llvm/test/Transforms/Reassociate/
Drepeats.ll102 %tmp7 = mul i4 %tmp6, %x
103 ret i4 %tmp7
119 %tmp7 = mul i4 %tmp6, %x
120 %tmp8 = mul i4 %tmp7, %x
137 %tmp7 = mul i4 %tmp6, %x
138 %tmp8 = mul i4 %tmp7, %x
157 %tmp7 = mul i4 %tmp6, %x
158 %tmp8 = mul i4 %tmp7, %x
176 %tmp7 = mul i4 %tmp6, %x
177 %tmp8 = mul i4 %tmp7, %x
[all …]
Dsubtest.ll19 ; CHECK-NEXT: %tmp7 = sub i32 0, %sum
20 ; CHECK-NEXT: ret i32 %tmp7
24 %tmp7 = sub i32 %tmp5, %a
25 ret i32 %tmp7
/external/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_estimator_mips.c34 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
80 [tmp7] "=&r" (tmp7), [tmp8] "=&r" (tmp8), [tmp_in] "+r" (tmp_in), in WebRtcIsacfix_PCorr2Q32()
105 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
172 [tmp7] "=&r" (tmp7), [tmp8] "=&r" (tmp8), [inptr] "+r" (inptr), in WebRtcIsacfix_PCorr2Q32()
/external/llvm/test/CodeGen/WebAssembly/
Dirreducible-cfg.ll25 %tmp7 = phi i32 [ %tmp18, %bb13 ], [ 0, %bb ]
26 %tmp8 = icmp slt i32 %tmp7, %arg1
30 %tmp10 = getelementptr double, double* %arg, i32 %tmp7
38 %tmp15 = phi i32 [ undef, %bb3 ], [ %tmp7, %bb9 ]
66 %tmp7 = phi i32 [ %tmp18, %bb13 ], [ 0, %bb ]
67 %tmp8 = icmp slt i32 %tmp7, %arg1
71 %tmp10 = getelementptr double, double* %arg, i32 %tmp7
85 %tmp15 = phi i32 [ undef, %bb3 ], [ %tmp7, %bb10 ]
/external/llvm/test/Transforms/TailCallElim/
Ddont_reorder_load.ll22 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
23 …%tmp8 = call fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
41 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
42 …%tmp8 = call fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
59 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
60 …%tmp8 = call fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
77 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
78 …%tmp8 = call fastcc i32 @no_tailrecelim_4(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
Dreorder_load.ll30 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
31 %tmp8 = call fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
61 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
62 %tmp8 = call fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
85 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
86 %tmp8 = call fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
118 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
120 %tmp8 = call fastcc i32 @raise_load_4(i32* %a_arg, i32 %first, i32 %tmp7) ; <i32> [#uses=1]
142 %tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
143 %tmp8 = call fastcc i32 @raise_load_5(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
/external/llvm/test/CodeGen/AArch64/
Daarch64-smull.ll78 %tmp7 = add <8 x i16> %tmp1, %tmp6
79 ret <8 x i16> %tmp7
91 %tmp7 = add <4 x i32> %tmp1, %tmp6
92 ret <4 x i32> %tmp7
104 %tmp7 = add <2 x i64> %tmp1, %tmp6
105 ret <2 x i64> %tmp7
117 %tmp7 = add <8 x i16> %tmp1, %tmp6
118 ret <8 x i16> %tmp7
130 %tmp7 = add <4 x i32> %tmp1, %tmp6
131 ret <4 x i32> %tmp7
[all …]
/external/llvm/test/Analysis/BasicAA/
D2007-10-24-ArgumentsGlobals.ll8 ; CHECK: %tmp7 = load
9 ; CHECK: ret i32 %tmp7
14 …%tmp7 = load i32, i32* getelementptr (%struct.B, %struct.B* @a, i32 0, i32 0, i32 0), align 8 …
15 ret i32 %tmp7
/external/libvpx/libvpx/vpx_dsp/mips/
Davg_msa.c64 v8i16 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; in vpx_hadamard_8x8_msa() local
68 tmp6, tmp7, tmp5, tmp3, tmp1); in vpx_hadamard_8x8_msa()
69 BUTTERFLY_8(tmp0, tmp1, tmp4, tmp5, tmp7, tmp6, tmp3, tmp2, src0, src1, src4, in vpx_hadamard_8x8_msa()
71 BUTTERFLY_8(src0, src1, src2, src3, src7, src6, src5, src4, tmp0, tmp7, tmp3, in vpx_hadamard_8x8_msa()
73 TRANSPOSE8x8_SH_SH(tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, src0, src1, in vpx_hadamard_8x8_msa()
76 tmp6, tmp7, tmp5, tmp3, tmp1); in vpx_hadamard_8x8_msa()
77 BUTTERFLY_8(tmp0, tmp1, tmp4, tmp5, tmp7, tmp6, tmp3, tmp2, src0, src1, src4, in vpx_hadamard_8x8_msa()
79 BUTTERFLY_8(src0, src1, src2, src3, src7, src6, src5, src4, tmp0, tmp7, tmp3, in vpx_hadamard_8x8_msa()
81 TRANSPOSE8x8_SH_SH(tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, src0, src1, in vpx_hadamard_8x8_msa()
90 v8i16 tmp6, tmp7, tmp8, tmp9, tmp10, tmp11, tmp12, tmp13, tmp14, tmp15; in vpx_hadamard_16x16_msa() local
[all …]
/external/llvm/test/CodeGen/PowerPC/
D2006-09-28-shift_64.ll18 %tmp7 = lshr i64 %tmp3, %shift.upgrd.1 ; <i64> [#uses=1]
19 %tmp7.upgrd.2 = trunc i64 %tmp7 to i32 ; <i32> [#uses=1]
20 %tmp8 = and i32 %tmp7.upgrd.2, 1 ; <i32> [#uses=1]
/external/llvm/test/Transforms/LoopUnroll/
D2011-08-09-PhiUpdate.ll17 …tmp7.i, %land.lhs.true ], [ 0, %do.cond ], [ %tmp7.i.1, %land.lhs.true.1 ], [ 0, %do.cond.1 ], [ %…
56 %tmp7 = call i32 @getval()
60 %cond = phi i32 [ %tmp7, %cond.true ], [ 0, %land.lhs.true ], [ 0, %entry ]

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