/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the AArch64 target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = 27; using PredicateBitset = llvm::PredicateBitsetImpl; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const; const ISelInfoTy ISelInfo; static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static AArch64InstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const int64_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(1), ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_HasJSBit = 5, Feature_HasComplxNumBit = 15, Feature_HasFPARMv8Bit = 4, Feature_HasNEONBit = 3, Feature_HasSHA2Bit = 12, Feature_HasAESBit = 11, Feature_HasDotProdBit = 1, Feature_HasCRCBit = 7, Feature_HasLSEBit = 13, Feature_HasRDMBit = 10, Feature_HasPerfMonBit = 16, Feature_HasFullFP16Bit = 9, Feature_HasFP16FMLBit = 2, Feature_HasFuseAESBit = 22, Feature_HasSVEBit = 0, Feature_HasSVE2Bit = 14, Feature_HasMTEBit = 8, Feature_HasTMEBit = 6, Feature_IsLEBit = 18, Feature_IsBEBit = 24, Feature_IsWindowsBit = 23, Feature_UseAlternateSExtLoadCVTF32Bit = 21, Feature_NotForCodeSizeBit = 20, Feature_UseSTRQroBit = 19, Feature_UseBTIBit = 26, Feature_NotUseBTIBit = 25, Feature_OptimizedGISelOrOtherSelectorBit = 17, }; PredicateBitset AArch64InstructionSelector:: computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const { PredicateBitset Features; if (Subtarget->hasJS()) Features.set(Feature_HasJSBit); if (Subtarget->hasComplxNum()) Features.set(Feature_HasComplxNumBit); if (Subtarget->hasFPARMv8()) Features.set(Feature_HasFPARMv8Bit); if (Subtarget->hasNEON()) Features.set(Feature_HasNEONBit); if (Subtarget->hasSHA2()) Features.set(Feature_HasSHA2Bit); if (Subtarget->hasAES()) Features.set(Feature_HasAESBit); if (Subtarget->hasDotProd()) Features.set(Feature_HasDotProdBit); if (Subtarget->hasCRC()) Features.set(Feature_HasCRCBit); if (Subtarget->hasLSE()) Features.set(Feature_HasLSEBit); if (Subtarget->hasRDM()) Features.set(Feature_HasRDMBit); if (Subtarget->hasPerfMon()) Features.set(Feature_HasPerfMonBit); if (Subtarget->hasFullFP16()) Features.set(Feature_HasFullFP16Bit); if (Subtarget->hasFP16FML()) Features.set(Feature_HasFP16FMLBit); if (Subtarget->hasFuseAES()) Features.set(Feature_HasFuseAESBit); if (Subtarget->hasSVE()) Features.set(Feature_HasSVEBit); if (Subtarget->hasSVE2()) Features.set(Feature_HasSVE2Bit); if (Subtarget->hasMTE()) Features.set(Feature_HasMTEBit); if (Subtarget->hasTME()) Features.set(Feature_HasTMEBit); if (Subtarget->isLittleEndian()) Features.set(Feature_IsLEBit); if (!Subtarget->isLittleEndian()) Features.set(Feature_IsBEBit); if (Subtarget->isTargetWindows()) Features.set(Feature_IsWindowsBit); if (Subtarget->useAlternateSExtLoadCVTF32Pattern()) Features.set(Feature_UseAlternateSExtLoadCVTF32Bit); return Features; } void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget*)&MF.getSubtarget(), &MF); } static bool shouldOptForSize(const MachineFunction *MF) { return MF->getFunction().hasOptSize(); } PredicateBitset AArch64InstructionSelector:: computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features; if (!shouldOptForSize(MF)) Features.set(Feature_NotForCodeSizeBit); if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF)) Features.set(Feature_UseSTRQroBit); if ( MF->getFunction().hasFnAttribute("branch-target-enforcement") ) Features.set(Feature_UseBTIBit); if ( !MF->getFunction().hasFnAttribute("branch-target-enforcement") ) Features.set(Feature_NotUseBTIBit); if (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)) Features.set(Feature_OptimizedGISelOrOtherSelectorBit); return Features; } // LLT Objects. enum { GILLT_s16, GILLT_s32, GILLT_s64, GILLT_s128, GILLT_v2s1, GILLT_v2s32, GILLT_v2s64, GILLT_v4s1, GILLT_v4s16, GILLT_v4s32, GILLT_v8s1, GILLT_v8s8, GILLT_v8s16, GILLT_v16s1, GILLT_v16s8, }; const static size_t NumTypeObjects = 15; const static LLT TypeObjects[] = { LLT::scalar(16), LLT::scalar(32), LLT::scalar(64), LLT::scalar(128), LLT::vector(2, 1), LLT::vector(2, 32), LLT::vector(2, 64), LLT::vector(4, 1), LLT::vector(4, 16), LLT::vector(4, 32), LLT::vector(8, 1), LLT::vector(8, 8), LLT::vector(8, 16), LLT::vector(16, 1), LLT::vector(16, 8), }; // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HasAES, GIFBS_HasCRC, GIFBS_HasDotProd, GIFBS_HasFPARMv8, GIFBS_HasFullFP16, GIFBS_HasFuseAES, GIFBS_HasLSE, GIFBS_HasMTE, GIFBS_HasNEON, GIFBS_HasPerfMon, GIFBS_HasRDM, GIFBS_HasSHA2, GIFBS_HasSVE, GIFBS_HasTME, GIFBS_IsBE, GIFBS_IsLE, GIFBS_OptimizedGISelOrOtherSelector, GIFBS_UseSTRQro, GIFBS_HasComplxNum_HasNEON, GIFBS_HasFP16FML_HasNEON, GIFBS_HasFPARMv8_HasJS, GIFBS_HasFullFP16_HasNEON, GIFBS_HasNEON_HasRDM, GIFBS_IsLE_UseSTRQro, GIFBS_HasComplxNum_HasFullFP16_HasNEON, }; const static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HasAESBit, }, {Feature_HasCRCBit, }, {Feature_HasDotProdBit, }, {Feature_HasFPARMv8Bit, }, {Feature_HasFullFP16Bit, }, {Feature_HasFuseAESBit, }, {Feature_HasLSEBit, }, {Feature_HasMTEBit, }, {Feature_HasNEONBit, }, {Feature_HasPerfMonBit, }, {Feature_HasRDMBit, }, {Feature_HasSHA2Bit, }, {Feature_HasSVEBit, }, {Feature_HasTMEBit, }, {Feature_IsBEBit, }, {Feature_IsLEBit, }, {Feature_OptimizedGISelOrOtherSelectorBit, }, {Feature_UseSTRQroBit, }, {Feature_HasComplxNumBit, Feature_HasNEONBit, }, {Feature_HasFP16FMLBit, Feature_HasNEONBit, }, {Feature_HasFPARMv8Bit, Feature_HasJSBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasNEONBit, Feature_HasRDMBit, }, {Feature_IsLEBit, Feature_UseSTRQroBit, }, {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, GICP_gi_addsub_shifted_imm32, GICP_gi_addsub_shifted_imm64, GICP_gi_am_indexed128, GICP_gi_am_indexed16, GICP_gi_am_indexed32, GICP_gi_am_indexed64, GICP_gi_am_indexed8, GICP_gi_am_unscaled128, GICP_gi_am_unscaled16, GICP_gi_am_unscaled32, GICP_gi_am_unscaled64, GICP_gi_am_unscaled8, GICP_gi_arith_extended_reg32_i32, GICP_gi_arith_extended_reg32_i64, GICP_gi_arith_extended_reg32to64_i64, GICP_gi_arith_shifted_reg32, GICP_gi_arith_shifted_reg64, GICP_gi_logical_shifted_reg32, GICP_gi_logical_shifted_reg64, GICP_gi_neg_addsub_shifted_imm32, GICP_gi_neg_addsub_shifted_imm64, GICP_gi_ro_Windexed128, GICP_gi_ro_Windexed16, GICP_gi_ro_Windexed32, GICP_gi_ro_Windexed64, GICP_gi_ro_Windexed8, GICP_gi_ro_Xindexed128, GICP_gi_ro_Xindexed16, GICP_gi_ro_Xindexed32, GICP_gi_ro_Xindexed64, GICP_gi_ro_Xindexed8, }; // See constructor for table contents // PatFrag predicates. enum { GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1, GIPFP_I64_Predicate_VectorIndex132b, GIPFP_I64_Predicate_VectorIndexB, GIPFP_I64_Predicate_VectorIndexB32b, GIPFP_I64_Predicate_VectorIndexD, GIPFP_I64_Predicate_VectorIndexD32b, GIPFP_I64_Predicate_VectorIndexH, GIPFP_I64_Predicate_VectorIndexH32b, GIPFP_I64_Predicate_VectorIndexS, GIPFP_I64_Predicate_VectorIndexS32b, GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16, GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32, GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64, GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8, GIPFP_I64_Predicate_complexrotateop, GIPFP_I64_Predicate_complexrotateopodd, GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16, GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32, GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64, GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8, GIPFP_I64_Predicate_i32_imm0_65535, GIPFP_I64_Predicate_i64_imm0_65535, GIPFP_I64_Predicate_i64imm_32bit, GIPFP_I64_Predicate_imm0_1, GIPFP_I64_Predicate_imm0_127, GIPFP_I64_Predicate_imm0_127_64b, GIPFP_I64_Predicate_imm0_15, GIPFP_I64_Predicate_imm0_255, GIPFP_I64_Predicate_imm0_31, GIPFP_I64_Predicate_imm0_63, GIPFP_I64_Predicate_imm0_7, GIPFP_I64_Predicate_imm32_0_15, GIPFP_I64_Predicate_imm32_0_31, GIPFP_I64_Predicate_imm32_0_7, GIPFP_I64_Predicate_maski16_or_more, GIPFP_I64_Predicate_maski8_or_more, GIPFP_I64_Predicate_s64imm_32bit, GIPFP_I64_Predicate_simm4s1, GIPFP_I64_Predicate_simm4s16, GIPFP_I64_Predicate_simm4s2, GIPFP_I64_Predicate_simm4s3, GIPFP_I64_Predicate_simm4s4, GIPFP_I64_Predicate_simm5_32b, GIPFP_I64_Predicate_simm5_64b, GIPFP_I64_Predicate_simm6_32b, GIPFP_I64_Predicate_simm6s1, GIPFP_I64_Predicate_simm8, GIPFP_I64_Predicate_simm9, GIPFP_I64_Predicate_sve_elm_idx_extdup_b, GIPFP_I64_Predicate_sve_elm_idx_extdup_d, GIPFP_I64_Predicate_sve_elm_idx_extdup_h, GIPFP_I64_Predicate_sve_elm_idx_extdup_q, GIPFP_I64_Predicate_sve_elm_idx_extdup_s, GIPFP_I64_Predicate_sve_incdec_imm, GIPFP_I64_Predicate_sve_pred_enum, GIPFP_I64_Predicate_sve_prfop, GIPFP_I64_Predicate_tbz_imm0_31_diag, GIPFP_I64_Predicate_tbz_imm0_31_nodiag, GIPFP_I64_Predicate_tbz_imm32_63, GIPFP_I64_Predicate_timm0_31, GIPFP_I64_Predicate_tuimm5s2, GIPFP_I64_Predicate_tuimm5s4, GIPFP_I64_Predicate_tuimm5s8, GIPFP_I64_Predicate_tvecshiftR16, GIPFP_I64_Predicate_tvecshiftR32, GIPFP_I64_Predicate_tvecshiftR8, GIPFP_I64_Predicate_uimm16, GIPFP_I64_Predicate_uimm5s2, GIPFP_I64_Predicate_uimm5s4, GIPFP_I64_Predicate_uimm5s8, GIPFP_I64_Predicate_uimm6, GIPFP_I64_Predicate_uimm6s1, GIPFP_I64_Predicate_uimm6s16, GIPFP_I64_Predicate_uimm6s2, GIPFP_I64_Predicate_uimm6s4, GIPFP_I64_Predicate_uimm6s8, GIPFP_I64_Predicate_vecshiftL16, GIPFP_I64_Predicate_vecshiftL32, GIPFP_I64_Predicate_vecshiftL64, GIPFP_I64_Predicate_vecshiftL8, GIPFP_I64_Predicate_vecshiftR16, GIPFP_I64_Predicate_vecshiftR16Narrow, GIPFP_I64_Predicate_vecshiftR32, GIPFP_I64_Predicate_vecshiftR32Narrow, GIPFP_I64_Predicate_vecshiftR64, GIPFP_I64_Predicate_vecshiftR64Narrow, GIPFP_I64_Predicate_vecshiftR8, }; bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GIPFP_I64_Predicate_VectorIndex1: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex132b: { return ((uint64_t)Imm) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexB32b: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexD32b: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexH32b: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndexS32b: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i16: { return AArch64_AM::isSVEAddSubImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i32: { return AArch64_AM::isSVEAddSubImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i64: { return AArch64_AM::isSVEAddSubImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_addsub_imm8_opt_lsl_i8: { return AArch64_AM::isSVEAddSubImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_complexrotateop: { return Imm >= 0 && Imm <= 270; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_complexrotateopodd: { return Imm >= 0 && Imm <= 270; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i16: { return AArch64_AM::isSVECpyImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i32: { return AArch64_AM::isSVECpyImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i64: { return AArch64_AM::isSVECpyImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_cpy_imm8_opt_lsl_i8: { return AArch64_AM::isSVECpyImm(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_i32_imm0_65535: { return ((uint32_t)Imm) < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_i64_imm0_65535: { return ((uint64_t)Imm) < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_i64imm_32bit: { return (Imm & 0xffffffffULL) == static_cast(Imm); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_1: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_127: { return ((uint32_t)Imm) < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_127_64b: { return ((uint64_t)Imm) < 128; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_15: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_255: { return ((uint32_t)Imm) < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_63: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_7: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32_0_15: { return ((uint32_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32_0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32_0_7: { return ((uint32_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_maski16_or_more: { return (Imm & 0xffff) == 0xffff; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_maski8_or_more: { return (Imm & 0xff) == 0xff; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_s64imm_32bit: { int64_t Imm64 = static_cast(Imm); return Imm64 >= std::numeric_limits::min() && Imm64 <= std::numeric_limits::max(); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s1: { return Imm >=-8 && Imm <= 7; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s16: { return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s2: { return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s3: { return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm4s4: { return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_32b: { return Imm >= -16 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm5_64b: { return Imm >= -16 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm6_32b: { return Imm >= -32 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm6s1: { return Imm >= -32 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm8: { return Imm >= -128 && Imm < 127; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_simm9: { return Imm >= -256 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: { return ((uint64_t)Imm) < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: { return ((uint64_t)Imm) < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_incdec_imm: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_pred_enum: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_sve_prfop: { return (((uint32_t)Imm) <= 15); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm0_31_diag: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tbz_imm32_63: { return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_timm0_31: { return ((uint64_t)Imm) < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s2: { return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s4: { return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tuimm5s8: { return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR16: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR32: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_tvecshiftR8: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm16: { return Imm >= 0 && Imm < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s2: { return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s4: { return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm5s8: { return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6: { return Imm >= 0 && Imm < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s1: { return Imm >= 0 && Imm < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s16: { return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s2: { return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s4: { return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_uimm6s8: { return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL16: { return (((uint32_t)Imm) < 16); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL32: { return (((uint32_t)Imm) < 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL64: { return (((uint32_t)Imm) < 64); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftL8: { return (((uint32_t)Imm) < 8); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR16: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR16Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR32: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR32Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR64: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR64Narrow: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_vecshiftR8: { return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, GIPFP_APFloat_Predicate_fpimm16, GIPFP_APFloat_Predicate_fpimm32, GIPFP_APFloat_Predicate_fpimm64, GIPFP_APFloat_Predicate_simdimmtype10, }; bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { switch (PredicateID) { case GIPFP_APFloat_Predicate_fpimm0: { return Imm.isExactlyValue(+0.0); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm16: { return AArch64_AM::getFP16Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm32: { return AArch64_AM::getFP32Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_fpimm64: { return AArch64_AM::getFP64Imm(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APFloat_Predicate_simdimmtype10: { return AArch64_AM::isAdvSIMDModImmType10( Imm.bitcastToAPInt().getZExtValue()); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1, GIPFP_APInt_Predicate_logical_imm64, }; bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { switch (PredicateID) { case GIPFP_APInt_Predicate_logical_imm32: { return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32); llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_APInt_Predicate_logical_imm64: { return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_MI_Predicate_ldaxr_1 = GIPFP_MI_Invalid + 1, GIPFP_MI_Predicate_ldaxr_2, GIPFP_MI_Predicate_ldaxr_4, GIPFP_MI_Predicate_ldaxr_8, GIPFP_MI_Predicate_ldxr_1, GIPFP_MI_Predicate_ldxr_2, GIPFP_MI_Predicate_ldxr_4, GIPFP_MI_Predicate_ldxr_8, GIPFP_MI_Predicate_stlxr_1, GIPFP_MI_Predicate_stlxr_2, GIPFP_MI_Predicate_stlxr_4, GIPFP_MI_Predicate_stlxr_8, GIPFP_MI_Predicate_stxr_1, GIPFP_MI_Predicate_stxr_2, GIPFP_MI_Predicate_stxr_4, GIPFP_MI_Predicate_stxr_8, }; bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); (void)MRI; switch (PredicateID) { case GIPFP_MI_Predicate_ldaxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldaxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_ldxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stlxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_1: { return isLoadStoreOfNumBytes(MI, 1); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_2: { return isLoadStoreOfNumBytes(MI, 2); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_4: { return isLoadStoreOfNumBytes(MI, 4); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_stxr_8: { return isLoadStoreOfNumBytes(MI, 8); llvm_unreachable("GISelPredicateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } AArch64InstructionSelector::ComplexMatcherMemFn AArch64InstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64 &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128 &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16 &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32 &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64 &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8 &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128 &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16 &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32 &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64 &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64 &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128 &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16 &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32 &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64 &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8 &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128 &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16 &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32 &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64 &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8 }; // Custom renderers. enum { GICR_Invalid, GICR_renderLogicalImm32, GICR_renderLogicalImm64, GICR_renderTruncImm, }; AArch64InstructionSelector::CustomRendererFn AArch64InstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid &AArch64InstructionSelector::renderLogicalImm32, // gi_logical_imm32_XFORM &AArch64InstructionSelector::renderLogicalImm64, // gi_logical_imm64_XFORM &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm }; bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { MachineFunction &MF = *I.getParent()->getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); const PredicateBitset AvailableFeatures = getAvailableFeatures(); NewMIVector OutMIs; State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { return true; } return false; } const int64_t *AArch64InstructionSelector::getMatchTable() const { constexpr static int64_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/35, 171, /*)*//*default:*//*Label 73*/ 114739, /*TargetOpcode::G_ADD*//*Label 0*/ 141, /*TargetOpcode::G_SUB*//*Label 1*/ 7282, /*TargetOpcode::G_MUL*//*Label 2*/ 9747, /*TargetOpcode::G_SDIV*//*Label 3*/ 10542, /*TargetOpcode::G_UDIV*//*Label 4*/ 10611, 0, 0, /*TargetOpcode::G_AND*//*Label 5*/ 10680, /*TargetOpcode::G_OR*//*Label 6*/ 12314, /*TargetOpcode::G_XOR*//*Label 7*/ 13308, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 14920, 0, 0, /*TargetOpcode::G_BITCAST*//*Label 9*/ 21187, /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 30112, /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 30324, /*TargetOpcode::G_READCYCLECOUNTER*//*Label 12*/ 30536, /*TargetOpcode::G_LOAD*//*Label 13*/ 30564, /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ 36849, /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ 37820, 0, 0, 0, /*TargetOpcode::G_STORE*//*Label 16*/ 39863, 0, 0, /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 17*/ 44202, /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 18*/ 45399, /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 19*/ 46428, /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 20*/ 47457, /*TargetOpcode::G_ATOMICRMW_AND*//*Label 21*/ 48886, 0, /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ 50315, /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ 51344, /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ 52373, /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ 53402, /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ 54431, /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ 55460, 0, 0, /*TargetOpcode::G_FENCE*//*Label 28*/ 56489, 0, 0, /*TargetOpcode::G_INTRINSIC*//*Label 29*/ 56541, /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ 94205, /*TargetOpcode::G_ANYEXT*//*Label 31*/ 97021, /*TargetOpcode::G_TRUNC*//*Label 32*/ 97201, /*TargetOpcode::G_CONSTANT*//*Label 33*/ 97329, /*TargetOpcode::G_FCONSTANT*//*Label 34*/ 97437, 0, 0, /*TargetOpcode::G_SEXT*//*Label 35*/ 97515, 0, /*TargetOpcode::G_ZEXT*//*Label 36*/ 97774, /*TargetOpcode::G_SHL*//*Label 37*/ 98235, /*TargetOpcode::G_LSHR*//*Label 38*/ 98548, /*TargetOpcode::G_ASHR*//*Label 39*/ 98933, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_UMULH*//*Label 40*/ 99428, /*TargetOpcode::G_SMULH*//*Label 41*/ 99865, /*TargetOpcode::G_FADD*//*Label 42*/ 100302, /*TargetOpcode::G_FSUB*//*Label 43*/ 100890, /*TargetOpcode::G_FMUL*//*Label 44*/ 101166, /*TargetOpcode::G_FMA*//*Label 45*/ 101835, 0, /*TargetOpcode::G_FDIV*//*Label 46*/ 105507, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_FNEG*//*Label 47*/ 105783, /*TargetOpcode::G_FPEXT*//*Label 48*/ 106334, /*TargetOpcode::G_FPTRUNC*//*Label 49*/ 106465, /*TargetOpcode::G_FPTOSI*//*Label 50*/ 106596, /*TargetOpcode::G_FPTOUI*//*Label 51*/ 107499, /*TargetOpcode::G_SITOFP*//*Label 52*/ 108402, /*TargetOpcode::G_UITOFP*//*Label 53*/ 108683, /*TargetOpcode::G_FABS*//*Label 54*/ 110440, 0, 0, /*TargetOpcode::G_FMINNUM*//*Label 55*/ 111000, /*TargetOpcode::G_FMAXNUM*//*Label 56*/ 111288, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_SMIN*//*Label 57*/ 111576, /*TargetOpcode::G_SMAX*//*Label 58*/ 111785, /*TargetOpcode::G_UMIN*//*Label 59*/ 111994, /*TargetOpcode::G_UMAX*//*Label 60*/ 112203, /*TargetOpcode::G_BR*//*Label 61*/ 112412, 0, 0, /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 62*/ 112425, 0, /*TargetOpcode::G_CTTZ*//*Label 63*/ 112784, 0, /*TargetOpcode::G_CTLZ*//*Label 64*/ 112887, 0, /*TargetOpcode::G_CTPOP*//*Label 65*/ 113514, /*TargetOpcode::G_BSWAP*//*Label 66*/ 113573, /*TargetOpcode::G_BITREVERSE*//*Label 67*/ 113626, /*TargetOpcode::G_FCEIL*//*Label 68*/ 113679, 0, 0, /*TargetOpcode::G_FSQRT*//*Label 69*/ 113891, /*TargetOpcode::G_FFLOOR*//*Label 70*/ 114103, /*TargetOpcode::G_FRINT*//*Label 71*/ 114315, /*TargetOpcode::G_FNEARBYINT*//*Label 72*/ 114527, // Label 0: @141 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 83*/ 7281, /*GILLT_s32*//*Label 74*/ 161, /*GILLT_s64*//*Label 75*/ 466, 0, 0, /*GILLT_v2s32*//*Label 76*/ 1880, /*GILLT_v2s64*//*Label 77*/ 2379, 0, /*GILLT_v4s16*//*Label 78*/ 3482, /*GILLT_v4s32*//*Label 79*/ 3981, 0, /*GILLT_v8s8*//*Label 80*/ 5340, /*GILLT_v8s16*//*Label 81*/ 5631, 0, /*GILLT_v16s8*//*Label 82*/ 6990, // Label 74: @161 GIM_Try, /*On fail goto*//*Label 84*/ 465, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 85*/ 205, // Rule ID 5384 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5384, GIR_Done, // Label 85: @205 GIM_Try, /*On fail goto*//*Label 86*/ 239, // Rule ID 61 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 61, GIR_Done, // Label 86: @239 GIM_Try, /*On fail goto*//*Label 87*/ 273, // Rule ID 5388 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$R3, GPR32sp:{ *:[i32] }:$R2) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5388, GIR_Done, // Label 87: @273 GIM_Try, /*On fail goto*//*Label 88*/ 307, // Rule ID 5641 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5641, GIR_Done, // Label 88: @307 GIM_Try, /*On fail goto*//*Label 89*/ 341, // Rule ID 67 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 67, GIR_Done, // Label 89: @341 GIM_Try, /*On fail goto*//*Label 90*/ 375, // Rule ID 2343 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2343, GIR_Done, // Label 90: @375 GIM_Try, /*On fail goto*//*Label 91*/ 409, // Rule ID 5386 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5386, GIR_Done, // Label 91: @409 GIM_Try, /*On fail goto*//*Label 92*/ 443, // Rule ID 65 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 65, GIR_Done, // Label 92: @443 GIM_Try, /*On fail goto*//*Label 93*/ 464, // Rule ID 63 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 63, GIR_Done, // Label 93: @464 GIM_Reject, // Label 84: @465 GIM_Reject, // Label 75: @466 GIM_Try, /*On fail goto*//*Label 94*/ 1879, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 95*/ 545, // Rule ID 4040 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4040, GIR_Done, // Label 95: @545 GIM_Try, /*On fail goto*//*Label 96*/ 614, // Rule ID 5814 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5814, GIR_Done, // Label 96: @614 GIM_Try, /*On fail goto*//*Label 97*/ 648, // Rule ID 5385 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5385, GIR_Done, // Label 97: @648 GIM_Try, /*On fail goto*//*Label 98*/ 744, // Rule ID 2389 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2389, GIR_Done, // Label 98: @744 GIM_Try, /*On fail goto*//*Label 99*/ 840, // Rule ID 2390 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2390, GIR_Done, // Label 99: @840 GIM_Try, /*On fail goto*//*Label 100*/ 874, // Rule ID 62 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 62, GIR_Done, // Label 100: @874 GIM_Try, /*On fail goto*//*Label 101*/ 970, // Rule ID 5647 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5647, GIR_Done, // Label 101: @970 GIM_Try, /*On fail goto*//*Label 102*/ 1066, // Rule ID 5648 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5648, GIR_Done, // Label 102: @1066 GIM_Try, /*On fail goto*//*Label 103*/ 1151, // Rule ID 5396 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5396, GIR_Done, // Label 103: @1151 GIM_Try, /*On fail goto*//*Label 104*/ 1236, // Rule ID 5397 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5397, GIR_Done, // Label 104: @1236 GIM_Try, /*On fail goto*//*Label 105*/ 1321, // Rule ID 93 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 93, GIR_Done, // Label 105: @1321 GIM_Try, /*On fail goto*//*Label 106*/ 1406, // Rule ID 95 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 95, GIR_Done, // Label 106: @1406 GIM_Try, /*On fail goto*//*Label 107*/ 1440, // Rule ID 5389 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$R3, GPR64sp:{ *:[i64] }:$R2) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5389, GIR_Done, // Label 107: @1440 GIM_Try, /*On fail goto*//*Label 108*/ 1474, // Rule ID 5642 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5642, GIR_Done, // Label 108: @1474 GIM_Try, /*On fail goto*//*Label 109*/ 1508, // Rule ID 68 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 68, GIR_Done, // Label 109: @1508 GIM_Try, /*On fail goto*//*Label 110*/ 1542, // Rule ID 2344 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2344, GIR_Done, // Label 110: @1542 GIM_Try, /*On fail goto*//*Label 111*/ 1576, // Rule ID 5387 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5387, GIR_Done, // Label 111: @1576 GIM_Try, /*On fail goto*//*Label 112*/ 1610, // Rule ID 66 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 66, GIR_Done, // Label 112: @1610 GIM_Try, /*On fail goto*//*Label 113*/ 1666, // Rule ID 5462 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 371:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5462, GIR_Done, // Label 113: @1666 GIM_Try, /*On fail goto*//*Label 114*/ 1722, // Rule ID 5468 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 429:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5468, GIR_Done, // Label 114: @1722 GIM_Try, /*On fail goto*//*Label 115*/ 1778, // Rule ID 791 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 371:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 791, GIR_Done, // Label 115: @1778 GIM_Try, /*On fail goto*//*Label 116*/ 1834, // Rule ID 835 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 429:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 835, GIR_Done, // Label 116: @1834 GIM_Try, /*On fail goto*//*Label 117*/ 1855, // Rule ID 64 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 64, GIR_Done, // Label 117: @1855 GIM_Try, /*On fail goto*//*Label 118*/ 1878, // Rule ID 1278 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1278, GIR_Done, // Label 118: @1878 GIM_Reject, // Label 94: @1879 GIM_Reject, // Label 76: @1880 GIM_Try, /*On fail goto*//*Label 119*/ 2378, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 120*/ 1958, // Rule ID 5474 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5474, GIR_Done, // Label 120: @1958 GIM_Try, /*On fail goto*//*Label 121*/ 2022, // Rule ID 5480 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5480, GIR_Done, // Label 121: @2022 GIM_Try, /*On fail goto*//*Label 122*/ 2074, // Rule ID 5460 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 371:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5460, GIR_Done, // Label 122: @2074 GIM_Try, /*On fail goto*//*Label 123*/ 2126, // Rule ID 5466 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 429:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5466, GIR_Done, // Label 123: @2126 GIM_Try, /*On fail goto*//*Label 124*/ 2190, // Rule ID 1053 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1053, GIR_Done, // Label 124: @2190 GIM_Try, /*On fail goto*//*Label 125*/ 2254, // Rule ID 1164 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1164, GIR_Done, // Label 125: @2254 GIM_Try, /*On fail goto*//*Label 126*/ 2306, // Rule ID 789 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 371:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 789, GIR_Done, // Label 126: @2306 GIM_Try, /*On fail goto*//*Label 127*/ 2358, // Rule ID 833 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 429:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 833, GIR_Done, // Label 127: @2358 GIM_Try, /*On fail goto*//*Label 128*/ 2377, // Rule ID 869 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 869, GIR_Done, // Label 128: @2377 GIM_Reject, // Label 119: @2378 GIM_Reject, // Label 77: @2379 GIM_Try, /*On fail goto*//*Label 129*/ 3481, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 130*/ 2470, // Rule ID 5528 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5528, GIR_Done, // Label 130: @2470 GIM_Try, /*On fail goto*//*Label 131*/ 2547, // Rule ID 5546 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5546, GIR_Done, // Label 131: @2547 GIM_Try, /*On fail goto*//*Label 132*/ 2624, // Rule ID 1360 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1360, GIR_Done, // Label 132: @2624 GIM_Try, /*On fail goto*//*Label 133*/ 2701, // Rule ID 1426 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1426, GIR_Done, // Label 133: @2701 GIM_Try, /*On fail goto*//*Label 134*/ 2765, // Rule ID 5540 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 387:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5540, GIR_Done, // Label 134: @2765 GIM_Try, /*On fail goto*//*Label 135*/ 2829, // Rule ID 5558 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5558, GIR_Done, // Label 135: @2829 GIM_Try, /*On fail goto*//*Label 136*/ 2881, // Rule ID 5463 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 371:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5463, GIR_Done, // Label 136: @2881 GIM_Try, /*On fail goto*//*Label 137*/ 2933, // Rule ID 5469 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 429:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5469, GIR_Done, // Label 137: @2933 GIM_Try, /*On fail goto*//*Label 138*/ 2997, // Rule ID 1384 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 387:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1384, GIR_Done, // Label 138: @2997 GIM_Try, /*On fail goto*//*Label 139*/ 3061, // Rule ID 1444 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1444, GIR_Done, // Label 139: @3061 GIM_Try, /*On fail goto*//*Label 140*/ 3113, // Rule ID 792 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 371:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 792, GIR_Done, // Label 140: @3113 GIM_Try, /*On fail goto*//*Label 141*/ 3165, // Rule ID 836 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 429:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 836, GIR_Done, // Label 141: @3165 GIM_Try, /*On fail goto*//*Label 142*/ 3223, // Rule ID 1372 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1372, GIR_Done, // Label 142: @3223 GIM_Try, /*On fail goto*//*Label 143*/ 3281, // Rule ID 1432 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1432, GIR_Done, // Label 143: @3281 GIM_Try, /*On fail goto*//*Label 144*/ 3326, // Rule ID 5534 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5534, GIR_Done, // Label 144: @3326 GIM_Try, /*On fail goto*//*Label 145*/ 3371, // Rule ID 5552 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5552, GIR_Done, // Label 145: @3371 GIM_Try, /*On fail goto*//*Label 146*/ 3416, // Rule ID 1378 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1378, GIR_Done, // Label 146: @3416 GIM_Try, /*On fail goto*//*Label 147*/ 3461, // Rule ID 1438 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1438, GIR_Done, // Label 147: @3461 GIM_Try, /*On fail goto*//*Label 148*/ 3480, // Rule ID 871 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 871, GIR_Done, // Label 148: @3480 GIM_Reject, // Label 129: @3481 GIM_Reject, // Label 78: @3482 GIM_Try, /*On fail goto*//*Label 149*/ 3980, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 150*/ 3560, // Rule ID 5472 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5472, GIR_Done, // Label 150: @3560 GIM_Try, /*On fail goto*//*Label 151*/ 3624, // Rule ID 5478 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5478, GIR_Done, // Label 151: @3624 GIM_Try, /*On fail goto*//*Label 152*/ 3676, // Rule ID 5458 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 371:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5458, GIR_Done, // Label 152: @3676 GIM_Try, /*On fail goto*//*Label 153*/ 3728, // Rule ID 5464 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 429:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5464, GIR_Done, // Label 153: @3728 GIM_Try, /*On fail goto*//*Label 154*/ 3792, // Rule ID 1051 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1051, GIR_Done, // Label 154: @3792 GIM_Try, /*On fail goto*//*Label 155*/ 3856, // Rule ID 1162 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1162, GIR_Done, // Label 155: @3856 GIM_Try, /*On fail goto*//*Label 156*/ 3908, // Rule ID 787 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 371:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 787, GIR_Done, // Label 156: @3908 GIM_Try, /*On fail goto*//*Label 157*/ 3960, // Rule ID 831 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 429:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 831, GIR_Done, // Label 157: @3960 GIM_Try, /*On fail goto*//*Label 158*/ 3979, // Rule ID 867 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 867, GIR_Done, // Label 158: @3979 GIM_Reject, // Label 149: @3980 GIM_Reject, // Label 79: @3981 GIM_Try, /*On fail goto*//*Label 159*/ 5339, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 160*/ 4072, // Rule ID 5526 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5526, GIR_Done, // Label 160: @4072 GIM_Try, /*On fail goto*//*Label 161*/ 4149, // Rule ID 5544 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5544, GIR_Done, // Label 161: @4149 GIM_Try, /*On fail goto*//*Label 162*/ 4226, // Rule ID 1358 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1358, GIR_Done, // Label 162: @4226 GIM_Try, /*On fail goto*//*Label 163*/ 4303, // Rule ID 1424 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1424, GIR_Done, // Label 163: @4303 GIM_Try, /*On fail goto*//*Label 164*/ 4367, // Rule ID 5475 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 370:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5475, GIR_Done, // Label 164: @4367 GIM_Try, /*On fail goto*//*Label 165*/ 4431, // Rule ID 5481 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 428:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5481, GIR_Done, // Label 165: @4431 GIM_Try, /*On fail goto*//*Label 166*/ 4495, // Rule ID 5538 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 387:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5538, GIR_Done, // Label 166: @4495 GIM_Try, /*On fail goto*//*Label 167*/ 4559, // Rule ID 5556 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5556, GIR_Done, // Label 167: @4559 GIM_Try, /*On fail goto*//*Label 168*/ 4611, // Rule ID 5461 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 371:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5461, GIR_Done, // Label 168: @4611 GIM_Try, /*On fail goto*//*Label 169*/ 4663, // Rule ID 5467 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 429:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5467, GIR_Done, // Label 169: @4663 GIM_Try, /*On fail goto*//*Label 170*/ 4727, // Rule ID 1054 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 370:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1054, GIR_Done, // Label 170: @4727 GIM_Try, /*On fail goto*//*Label 171*/ 4791, // Rule ID 1165 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 428:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1165, GIR_Done, // Label 171: @4791 GIM_Try, /*On fail goto*//*Label 172*/ 4855, // Rule ID 1382 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 387:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1382, GIR_Done, // Label 172: @4855 GIM_Try, /*On fail goto*//*Label 173*/ 4919, // Rule ID 1442 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1442, GIR_Done, // Label 173: @4919 GIM_Try, /*On fail goto*//*Label 174*/ 4971, // Rule ID 790 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 371:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 790, GIR_Done, // Label 174: @4971 GIM_Try, /*On fail goto*//*Label 175*/ 5023, // Rule ID 834 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 429:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 834, GIR_Done, // Label 175: @5023 GIM_Try, /*On fail goto*//*Label 176*/ 5081, // Rule ID 1370 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1370, GIR_Done, // Label 176: @5081 GIM_Try, /*On fail goto*//*Label 177*/ 5139, // Rule ID 1430 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1430, GIR_Done, // Label 177: @5139 GIM_Try, /*On fail goto*//*Label 178*/ 5184, // Rule ID 5532 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5532, GIR_Done, // Label 178: @5184 GIM_Try, /*On fail goto*//*Label 179*/ 5229, // Rule ID 5550 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5550, GIR_Done, // Label 179: @5229 GIM_Try, /*On fail goto*//*Label 180*/ 5274, // Rule ID 1376 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1376, GIR_Done, // Label 180: @5274 GIM_Try, /*On fail goto*//*Label 181*/ 5319, // Rule ID 1436 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1436, GIR_Done, // Label 181: @5319 GIM_Try, /*On fail goto*//*Label 182*/ 5338, // Rule ID 870 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 870, GIR_Done, // Label 182: @5338 GIM_Reject, // Label 159: @5339 GIM_Reject, // Label 80: @5340 GIM_Try, /*On fail goto*//*Label 183*/ 5630, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 184*/ 5418, // Rule ID 5470 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5470, GIR_Done, // Label 184: @5418 GIM_Try, /*On fail goto*//*Label 185*/ 5482, // Rule ID 5476 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5476, GIR_Done, // Label 185: @5482 GIM_Try, /*On fail goto*//*Label 186*/ 5546, // Rule ID 1049 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1049, GIR_Done, // Label 186: @5546 GIM_Try, /*On fail goto*//*Label 187*/ 5610, // Rule ID 1160 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1160, GIR_Done, // Label 187: @5610 GIM_Try, /*On fail goto*//*Label 188*/ 5629, // Rule ID 865 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 865, GIR_Done, // Label 188: @5629 GIM_Reject, // Label 183: @5630 GIM_Reject, // Label 81: @5631 GIM_Try, /*On fail goto*//*Label 189*/ 6989, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 190*/ 5722, // Rule ID 5524 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5524, GIR_Done, // Label 190: @5722 GIM_Try, /*On fail goto*//*Label 191*/ 5799, // Rule ID 5542 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5542, GIR_Done, // Label 191: @5799 GIM_Try, /*On fail goto*//*Label 192*/ 5876, // Rule ID 1356 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1356, GIR_Done, // Label 192: @5876 GIM_Try, /*On fail goto*//*Label 193*/ 5953, // Rule ID 1422 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1422, GIR_Done, // Label 193: @5953 GIM_Try, /*On fail goto*//*Label 194*/ 6017, // Rule ID 5473 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 370:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5473, GIR_Done, // Label 194: @6017 GIM_Try, /*On fail goto*//*Label 195*/ 6081, // Rule ID 5479 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 428:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5479, GIR_Done, // Label 195: @6081 GIM_Try, /*On fail goto*//*Label 196*/ 6145, // Rule ID 5536 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 387:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5536, GIR_Done, // Label 196: @6145 GIM_Try, /*On fail goto*//*Label 197*/ 6209, // Rule ID 5554 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 441:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5554, GIR_Done, // Label 197: @6209 GIM_Try, /*On fail goto*//*Label 198*/ 6261, // Rule ID 5459 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 371:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5459, GIR_Done, // Label 198: @6261 GIM_Try, /*On fail goto*//*Label 199*/ 6313, // Rule ID 5465 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 429:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5465, GIR_Done, // Label 199: @6313 GIM_Try, /*On fail goto*//*Label 200*/ 6377, // Rule ID 1052 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 370:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1052, GIR_Done, // Label 200: @6377 GIM_Try, /*On fail goto*//*Label 201*/ 6441, // Rule ID 1163 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 428:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1163, GIR_Done, // Label 201: @6441 GIM_Try, /*On fail goto*//*Label 202*/ 6505, // Rule ID 1380 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 387:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1380, GIR_Done, // Label 202: @6505 GIM_Try, /*On fail goto*//*Label 203*/ 6569, // Rule ID 1440 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 441:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1440, GIR_Done, // Label 203: @6569 GIM_Try, /*On fail goto*//*Label 204*/ 6621, // Rule ID 788 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 371:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 788, GIR_Done, // Label 204: @6621 GIM_Try, /*On fail goto*//*Label 205*/ 6673, // Rule ID 832 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 429:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 832, GIR_Done, // Label 205: @6673 GIM_Try, /*On fail goto*//*Label 206*/ 6731, // Rule ID 1368 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1368, GIR_Done, // Label 206: @6731 GIM_Try, /*On fail goto*//*Label 207*/ 6789, // Rule ID 1428 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1428, GIR_Done, // Label 207: @6789 GIM_Try, /*On fail goto*//*Label 208*/ 6834, // Rule ID 5530 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5530, GIR_Done, // Label 208: @6834 GIM_Try, /*On fail goto*//*Label 209*/ 6879, // Rule ID 5548 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5548, GIR_Done, // Label 209: @6879 GIM_Try, /*On fail goto*//*Label 210*/ 6924, // Rule ID 1374 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1374, GIR_Done, // Label 210: @6924 GIM_Try, /*On fail goto*//*Label 211*/ 6969, // Rule ID 1434 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1434, GIR_Done, // Label 211: @6969 GIM_Try, /*On fail goto*//*Label 212*/ 6988, // Rule ID 868 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 868, GIR_Done, // Label 212: @6988 GIM_Reject, // Label 189: @6989 GIM_Reject, // Label 82: @6990 GIM_Try, /*On fail goto*//*Label 213*/ 7280, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 214*/ 7068, // Rule ID 5471 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 370:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5471, GIR_Done, // Label 214: @7068 GIM_Try, /*On fail goto*//*Label 215*/ 7132, // Rule ID 5477 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 428:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5477, GIR_Done, // Label 215: @7132 GIM_Try, /*On fail goto*//*Label 216*/ 7196, // Rule ID 1050 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 370:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1050, GIR_Done, // Label 216: @7196 GIM_Try, /*On fail goto*//*Label 217*/ 7260, // Rule ID 1161 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 428:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1161, GIR_Done, // Label 217: @7260 GIM_Try, /*On fail goto*//*Label 218*/ 7279, // Rule ID 866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 866, GIR_Done, // Label 218: @7279 GIM_Reject, // Label 213: @7280 GIM_Reject, // Label 83: @7281 GIM_Reject, // Label 1: @7282 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 228*/ 9746, /*GILLT_s32*//*Label 219*/ 7302, /*GILLT_s64*//*Label 220*/ 7533, 0, 0, /*GILLT_v2s32*//*Label 221*/ 8511, /*GILLT_v2s64*//*Label 222*/ 8543, 0, /*GILLT_v4s16*//*Label 223*/ 8912, /*GILLT_v4s32*//*Label 224*/ 8944, 0, /*GILLT_v8s8*//*Label 225*/ 9313, /*GILLT_v8s16*//*Label 226*/ 9345, 0, /*GILLT_v16s8*//*Label 227*/ 9714, // Label 219: @7302 GIM_Try, /*On fail goto*//*Label 229*/ 7532, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 230*/ 7371, // Rule ID 2375 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2375, GIR_Done, // Label 230: @7371 GIM_Try, /*On fail goto*//*Label 231*/ 7405, // Rule ID 2341 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2341, GIR_Done, // Label 231: @7405 GIM_Try, /*On fail goto*//*Label 232*/ 7439, // Rule ID 2345 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2345, GIR_Done, // Label 232: @7439 GIM_Try, /*On fail goto*//*Label 233*/ 7473, // Rule ID 2335 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2335, GIR_Done, // Label 233: @7473 GIM_Try, /*On fail goto*//*Label 234*/ 7507, // Rule ID 2339 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2339, GIR_Done, // Label 234: @7507 GIM_Try, /*On fail goto*//*Label 235*/ 7531, // Rule ID 2337 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr, GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2337, GIR_Done, // Label 235: @7531 GIM_Reject, // Label 229: @7532 GIM_Reject, // Label 220: @7533 GIM_Try, /*On fail goto*//*Label 236*/ 8510, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 237*/ 7639, // Rule ID 2386 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2386, GIR_Done, // Label 237: @7639 GIM_Try, /*On fail goto*//*Label 238*/ 7735, // Rule ID 2387 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2387, GIR_Done, // Label 238: @7735 GIM_Try, /*On fail goto*//*Label 239*/ 7820, // Rule ID 2381 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2381, GIR_Done, // Label 239: @7820 GIM_Try, /*On fail goto*//*Label 240*/ 7905, // Rule ID 2382 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2382, GIR_Done, // Label 240: @7905 GIM_Try, /*On fail goto*//*Label 241*/ 8001, // Rule ID 2392 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2392, GIR_Done, // Label 241: @8001 GIM_Try, /*On fail goto*//*Label 242*/ 8097, // Rule ID 2393 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2393, GIR_Done, // Label 242: @8097 GIM_Try, /*On fail goto*//*Label 243*/ 8182, // Rule ID 94 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 94, GIR_Done, // Label 243: @8182 GIM_Try, /*On fail goto*//*Label 244*/ 8267, // Rule ID 96 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 96, GIR_Done, // Label 244: @8267 GIM_Try, /*On fail goto*//*Label 245*/ 8326, // Rule ID 2376 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2376, GIR_Done, // Label 245: @8326 GIM_Try, /*On fail goto*//*Label 246*/ 8360, // Rule ID 2342 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrx, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2342, GIR_Done, // Label 246: @8360 GIM_Try, /*On fail goto*//*Label 247*/ 8394, // Rule ID 2346 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2346, GIR_Done, // Label 247: @8394 GIM_Try, /*On fail goto*//*Label 248*/ 8428, // Rule ID 2336 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2336, GIR_Done, // Label 248: @8428 GIM_Try, /*On fail goto*//*Label 249*/ 8462, // Rule ID 2340 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2340, GIR_Done, // Label 249: @8462 GIM_Try, /*On fail goto*//*Label 250*/ 8485, // Rule ID 1315 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1315, GIR_Done, // Label 250: @8485 GIM_Try, /*On fail goto*//*Label 251*/ 8509, // Rule ID 2338 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr, GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2338, GIR_Done, // Label 251: @8509 GIM_Reject, // Label 236: @8510 GIM_Reject, // Label 221: @8511 GIM_Try, /*On fail goto*//*Label 252*/ 8542, // Rule ID 1157 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1157, GIR_Done, // Label 252: @8542 GIM_Reject, // Label 222: @8543 GIM_Try, /*On fail goto*//*Label 253*/ 8911, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 254*/ 8621, // Rule ID 1390 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 387:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1390, GIR_Done, // Label 254: @8621 GIM_Try, /*On fail goto*//*Label 255*/ 8685, // Rule ID 1450 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1450, GIR_Done, // Label 255: @8685 GIM_Try, /*On fail goto*//*Label 256*/ 8743, // Rule ID 1414 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1414, GIR_Done, // Label 256: @8743 GIM_Try, /*On fail goto*//*Label 257*/ 8801, // Rule ID 1462 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1462, GIR_Done, // Label 257: @8801 GIM_Try, /*On fail goto*//*Label 258*/ 8846, // Rule ID 1420 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1420, GIR_Done, // Label 258: @8846 GIM_Try, /*On fail goto*//*Label 259*/ 8891, // Rule ID 1468 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1468, GIR_Done, // Label 259: @8891 GIM_Try, /*On fail goto*//*Label 260*/ 8910, // Rule ID 1159 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1159, GIR_Done, // Label 260: @8910 GIM_Reject, // Label 253: @8911 GIM_Reject, // Label 223: @8912 GIM_Try, /*On fail goto*//*Label 261*/ 8943, // Rule ID 1155 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1155, GIR_Done, // Label 261: @8943 GIM_Reject, // Label 224: @8944 GIM_Try, /*On fail goto*//*Label 262*/ 9312, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 263*/ 9022, // Rule ID 1388 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 387:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1388, GIR_Done, // Label 263: @9022 GIM_Try, /*On fail goto*//*Label 264*/ 9086, // Rule ID 1448 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1448, GIR_Done, // Label 264: @9086 GIM_Try, /*On fail goto*//*Label 265*/ 9144, // Rule ID 1412 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1412, GIR_Done, // Label 265: @9144 GIM_Try, /*On fail goto*//*Label 266*/ 9202, // Rule ID 1460 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1460, GIR_Done, // Label 266: @9202 GIM_Try, /*On fail goto*//*Label 267*/ 9247, // Rule ID 1418 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1418, GIR_Done, // Label 267: @9247 GIM_Try, /*On fail goto*//*Label 268*/ 9292, // Rule ID 1466 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1466, GIR_Done, // Label 268: @9292 GIM_Try, /*On fail goto*//*Label 269*/ 9311, // Rule ID 1158 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1158, GIR_Done, // Label 269: @9311 GIM_Reject, // Label 262: @9312 GIM_Reject, // Label 225: @9313 GIM_Try, /*On fail goto*//*Label 270*/ 9344, // Rule ID 1153 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1153, GIR_Done, // Label 270: @9344 GIM_Reject, // Label 226: @9345 GIM_Try, /*On fail goto*//*Label 271*/ 9713, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 272*/ 9423, // Rule ID 1386 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 387:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1386, GIR_Done, // Label 272: @9423 GIM_Try, /*On fail goto*//*Label 273*/ 9487, // Rule ID 1446 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 441:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1446, GIR_Done, // Label 273: @9487 GIM_Try, /*On fail goto*//*Label 274*/ 9545, // Rule ID 1410 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1410, GIR_Done, // Label 274: @9545 GIM_Try, /*On fail goto*//*Label 275*/ 9603, // Rule ID 1458 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1458, GIR_Done, // Label 275: @9603 GIM_Try, /*On fail goto*//*Label 276*/ 9648, // Rule ID 1416 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1416, GIR_Done, // Label 276: @9648 GIM_Try, /*On fail goto*//*Label 277*/ 9693, // Rule ID 1464 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1464, GIR_Done, // Label 277: @9693 GIM_Try, /*On fail goto*//*Label 278*/ 9712, // Rule ID 1156 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1156, GIR_Done, // Label 278: @9712 GIM_Reject, // Label 271: @9713 GIM_Reject, // Label 227: @9714 GIM_Try, /*On fail goto*//*Label 279*/ 9745, // Rule ID 1154 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1154, GIR_Done, // Label 279: @9745 GIM_Reject, // Label 228: @9746 GIM_Reject, // Label 2: @9747 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 288*/ 10541, /*GILLT_s32*//*Label 280*/ 9767, /*GILLT_s64*//*Label 281*/ 9927, 0, 0, /*GILLT_v2s32*//*Label 282*/ 10349, 0, 0, /*GILLT_v4s16*//*Label 283*/ 10381, /*GILLT_v4s32*//*Label 284*/ 10413, 0, /*GILLT_v8s8*//*Label 285*/ 10445, /*GILLT_v8s16*//*Label 286*/ 10477, 0, /*GILLT_v16s8*//*Label 287*/ 10509, // Label 280: @9767 GIM_Try, /*On fail goto*//*Label 289*/ 9926, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 290*/ 9836, // Rule ID 2377 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2377, GIR_Done, // Label 290: @9836 GIM_Try, /*On fail goto*//*Label 291*/ 9891, // Rule ID 5645 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5645, GIR_Done, // Label 291: @9891 GIM_Try, /*On fail goto*//*Label 292*/ 9925, // Rule ID 2373 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDWrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2373, GIR_Done, // Label 292: @9925 GIM_Reject, // Label 289: @9926 GIM_Reject, // Label 281: @9927 GIM_Try, /*On fail goto*//*Label 293*/ 10348, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 294*/ 9996, // Rule ID 2378 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2378, GIR_Done, // Label 294: @9996 GIM_Try, /*On fail goto*//*Label 295*/ 10051, // Rule ID 5646 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5646, GIR_Done, // Label 295: @10051 GIM_Try, /*On fail goto*//*Label 296*/ 10122, // Rule ID 2383 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2383, GIR_Done, // Label 296: @10122 GIM_Try, /*On fail goto*//*Label 297*/ 10193, // Rule ID 2384 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$C) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2384, GIR_Done, // Label 297: @10193 GIM_Try, /*On fail goto*//*Label 298*/ 10253, // Rule ID 2379 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2379, GIR_Done, // Label 298: @10253 GIM_Try, /*On fail goto*//*Label 299*/ 10313, // Rule ID 2380 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2380, GIR_Done, // Label 299: @10313 GIM_Try, /*On fail goto*//*Label 300*/ 10347, // Rule ID 2374 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDXrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2374, GIR_Done, // Label 300: @10347 GIM_Reject, // Label 293: @10348 GIM_Reject, // Label 282: @10349 GIM_Try, /*On fail goto*//*Label 301*/ 10380, // Rule ID 1045 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1045, GIR_Done, // Label 301: @10380 GIM_Reject, // Label 283: @10381 GIM_Try, /*On fail goto*//*Label 302*/ 10412, // Rule ID 1043 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1043, GIR_Done, // Label 302: @10412 GIM_Reject, // Label 284: @10413 GIM_Try, /*On fail goto*//*Label 303*/ 10444, // Rule ID 1046 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1046, GIR_Done, // Label 303: @10444 GIM_Reject, // Label 285: @10445 GIM_Try, /*On fail goto*//*Label 304*/ 10476, // Rule ID 1041 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1041, GIR_Done, // Label 304: @10476 GIM_Reject, // Label 286: @10477 GIM_Try, /*On fail goto*//*Label 305*/ 10508, // Rule ID 1044 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1044, GIR_Done, // Label 305: @10508 GIM_Reject, // Label 287: @10509 GIM_Try, /*On fail goto*//*Label 306*/ 10540, // Rule ID 1042 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1042, GIR_Done, // Label 306: @10540 GIM_Reject, // Label 288: @10541 GIM_Reject, // Label 3: @10542 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 309*/ 10610, /*GILLT_s32*//*Label 307*/ 10550, /*GILLT_s64*//*Label 308*/ 10580, // Label 307: @10550 GIM_Try, /*On fail goto*//*Label 310*/ 10579, // Rule ID 87 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 87, GIR_Done, // Label 310: @10579 GIM_Reject, // Label 308: @10580 GIM_Try, /*On fail goto*//*Label 311*/ 10609, // Rule ID 88 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 88, GIR_Done, // Label 311: @10609 GIM_Reject, // Label 309: @10610 GIM_Reject, // Label 4: @10611 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 314*/ 10679, /*GILLT_s32*//*Label 312*/ 10619, /*GILLT_s64*//*Label 313*/ 10649, // Label 312: @10619 GIM_Try, /*On fail goto*//*Label 315*/ 10648, // Rule ID 85 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 85, GIR_Done, // Label 315: @10648 GIM_Reject, // Label 313: @10649 GIM_Try, /*On fail goto*//*Label 316*/ 10678, // Rule ID 86 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 86, GIR_Done, // Label 316: @10678 GIM_Reject, // Label 314: @10679 GIM_Reject, // Label 5: @10680 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 326*/ 12313, /*GILLT_s32*//*Label 317*/ 10700, /*GILLT_s64*//*Label 318*/ 11187, 0, 0, /*GILLT_v2s32*//*Label 319*/ 12089, /*GILLT_v2s64*//*Label 320*/ 12121, 0, /*GILLT_v4s16*//*Label 321*/ 12153, /*GILLT_v4s32*//*Label 322*/ 12185, 0, /*GILLT_v8s8*//*Label 323*/ 12217, /*GILLT_v8s16*//*Label 324*/ 12249, 0, /*GILLT_v16s8*//*Label 325*/ 12281, // Label 317: @10700 GIM_Try, /*On fail goto*//*Label 327*/ 11186, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 328*/ 10765, // Rule ID 5408 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5408, GIR_Done, // Label 328: @10765 GIM_Try, /*On fail goto*//*Label 329*/ 10820, // Rule ID 132 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 132, GIR_Done, // Label 329: @10820 GIM_Try, /*On fail goto*//*Label 330*/ 10882, // Rule ID 3236 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx), 255:{ *:[i32] }) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3236, GIR_Done, // Label 330: @10882 GIM_Try, /*On fail goto*//*Label 331*/ 10944, // Rule ID 3237 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx), 65535:{ *:[i32] }) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3237, GIR_Done, // Label 331: @10944 GIM_Try, /*On fail goto*//*Label 332*/ 10986, // Rule ID 112 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 112, GIR_Done, // Label 332: @10986 GIM_Try, /*On fail goto*//*Label 333*/ 11020, // Rule ID 5404 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5404, GIR_Done, // Label 333: @11020 GIM_Try, /*On fail goto*//*Label 334*/ 11054, // Rule ID 128 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 128, GIR_Done, // Label 334: @11054 GIM_Try, /*On fail goto*//*Label 335*/ 11109, // Rule ID 5406 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5406, GIR_Done, // Label 335: @11109 GIM_Try, /*On fail goto*//*Label 336*/ 11164, // Rule ID 130 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 130, GIR_Done, // Label 336: @11164 GIM_Try, /*On fail goto*//*Label 337*/ 11185, // Rule ID 126 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 126, GIR_Done, // Label 337: @11185 GIM_Reject, // Label 327: @11186 GIM_Reject, // Label 318: @11187 GIM_Try, /*On fail goto*//*Label 338*/ 12088, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 339*/ 11252, // Rule ID 5409 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5409, GIR_Done, // Label 339: @11252 GIM_Try, /*On fail goto*//*Label 340*/ 11307, // Rule ID 133 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 133, GIR_Done, // Label 340: @11307 GIM_Try, /*On fail goto*//*Label 341*/ 11393, // Rule ID 4117 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_1, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4117, GIR_Done, // Label 341: @11393 GIM_Try, /*On fail goto*//*Label 342*/ 11479, // Rule ID 4118 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_2, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4118, GIR_Done, // Label 342: @11479 GIM_Try, /*On fail goto*//*Label 343*/ 11565, // Rule ID 4119 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_4, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4119, GIR_Done, // Label 343: @11565 GIM_Try, /*On fail goto*//*Label 344*/ 11651, // Rule ID 4124 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4124, GIR_Done, // Label 344: @11651 GIM_Try, /*On fail goto*//*Label 345*/ 11737, // Rule ID 4125 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4125, GIR_Done, // Label 345: @11737 GIM_Try, /*On fail goto*//*Label 346*/ 11823, // Rule ID 4126 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, // MIs[1] addr GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4126, GIR_Done, // Label 346: @11823 GIM_Try, /*On fail goto*//*Label 347*/ 11865, // Rule ID 113 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 113, GIR_Done, // Label 347: @11865 GIM_Try, /*On fail goto*//*Label 348*/ 11899, // Rule ID 5405 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5405, GIR_Done, // Label 348: @11899 GIM_Try, /*On fail goto*//*Label 349*/ 11933, // Rule ID 129 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 129, GIR_Done, // Label 349: @11933 GIM_Try, /*On fail goto*//*Label 350*/ 11988, // Rule ID 5407 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5407, GIR_Done, // Label 350: @11988 GIM_Try, /*On fail goto*//*Label 351*/ 12043, // Rule ID 131 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 131, GIR_Done, // Label 351: @12043 GIM_Try, /*On fail goto*//*Label 352*/ 12064, // Rule ID 127 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 127, GIR_Done, // Label 352: @12064 GIM_Try, /*On fail goto*//*Label 353*/ 12087, // Rule ID 1863 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1863, GIR_Done, // Label 353: @12087 GIM_Reject, // Label 338: @12088 GIM_Reject, // Label 319: @12089 GIM_Try, /*On fail goto*//*Label 354*/ 12120, // Rule ID 1862 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1862, GIR_Done, // Label 354: @12120 GIM_Reject, // Label 320: @12121 GIM_Try, /*On fail goto*//*Label 355*/ 12152, // Rule ID 1866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1866, GIR_Done, // Label 355: @12152 GIM_Reject, // Label 321: @12153 GIM_Try, /*On fail goto*//*Label 356*/ 12184, // Rule ID 1861 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1861, GIR_Done, // Label 356: @12184 GIM_Reject, // Label 322: @12185 GIM_Try, /*On fail goto*//*Label 357*/ 12216, // Rule ID 1865 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1865, GIR_Done, // Label 357: @12216 GIM_Reject, // Label 323: @12217 GIM_Try, /*On fail goto*//*Label 358*/ 12248, // Rule ID 1264 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1264, GIR_Done, // Label 358: @12248 GIM_Reject, // Label 324: @12249 GIM_Try, /*On fail goto*//*Label 359*/ 12280, // Rule ID 1864 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1864, GIR_Done, // Label 359: @12280 GIM_Reject, // Label 325: @12281 GIM_Try, /*On fail goto*//*Label 360*/ 12312, // Rule ID 1265 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1265, GIR_Done, // Label 360: @12312 GIM_Reject, // Label 326: @12313 GIM_Reject, // Label 6: @12314 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 370*/ 13307, /*GILLT_s32*//*Label 361*/ 12334, /*GILLT_s64*//*Label 362*/ 12697, 0, 0, /*GILLT_v2s32*//*Label 363*/ 13083, /*GILLT_v2s64*//*Label 364*/ 13115, 0, /*GILLT_v4s16*//*Label 365*/ 13147, /*GILLT_v4s32*//*Label 366*/ 13179, 0, /*GILLT_v8s8*//*Label 367*/ 13211, /*GILLT_v8s16*//*Label 368*/ 13243, 0, /*GILLT_v16s8*//*Label 369*/ 13275, // Label 361: @12334 GIM_Try, /*On fail goto*//*Label 371*/ 12696, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 372*/ 12399, // Rule ID 5428 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5428, GIR_Done, // Label 372: @12399 GIM_Try, /*On fail goto*//*Label 373*/ 12454, // Rule ID 144 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 144, GIR_Done, // Label 373: @12454 GIM_Try, /*On fail goto*//*Label 374*/ 12496, // Rule ID 116 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 116, GIR_Done, // Label 374: @12496 GIM_Try, /*On fail goto*//*Label 375*/ 12530, // Rule ID 5430 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5430, GIR_Done, // Label 375: @12530 GIM_Try, /*On fail goto*//*Label 376*/ 12564, // Rule ID 148 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 148, GIR_Done, // Label 376: @12564 GIM_Try, /*On fail goto*//*Label 377*/ 12619, // Rule ID 5426 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5426, GIR_Done, // Label 377: @12619 GIM_Try, /*On fail goto*//*Label 378*/ 12674, // Rule ID 142 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 142, GIR_Done, // Label 378: @12674 GIM_Try, /*On fail goto*//*Label 379*/ 12695, // Rule ID 146 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 146, GIR_Done, // Label 379: @12695 GIM_Reject, // Label 371: @12696 GIM_Reject, // Label 362: @12697 GIM_Try, /*On fail goto*//*Label 380*/ 13082, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 381*/ 12762, // Rule ID 5429 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5429, GIR_Done, // Label 381: @12762 GIM_Try, /*On fail goto*//*Label 382*/ 12817, // Rule ID 145 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 145, GIR_Done, // Label 382: @12817 GIM_Try, /*On fail goto*//*Label 383*/ 12859, // Rule ID 117 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 117, GIR_Done, // Label 383: @12859 GIM_Try, /*On fail goto*//*Label 384*/ 12893, // Rule ID 5431 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5431, GIR_Done, // Label 384: @12893 GIM_Try, /*On fail goto*//*Label 385*/ 12927, // Rule ID 149 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 149, GIR_Done, // Label 385: @12927 GIM_Try, /*On fail goto*//*Label 386*/ 12982, // Rule ID 5427 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5427, GIR_Done, // Label 386: @12982 GIM_Try, /*On fail goto*//*Label 387*/ 13037, // Rule ID 143 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 143, GIR_Done, // Label 387: @13037 GIM_Try, /*On fail goto*//*Label 388*/ 13058, // Rule ID 147 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 147, GIR_Done, // Label 388: @13058 GIM_Try, /*On fail goto*//*Label 389*/ 13081, // Rule ID 2954 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2954, GIR_Done, // Label 389: @13081 GIM_Reject, // Label 380: @13082 GIM_Reject, // Label 363: @13083 GIM_Try, /*On fail goto*//*Label 390*/ 13114, // Rule ID 2953 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2953, GIR_Done, // Label 390: @13114 GIM_Reject, // Label 364: @13115 GIM_Try, /*On fail goto*//*Label 391*/ 13146, // Rule ID 2957 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2957, GIR_Done, // Label 391: @13146 GIM_Reject, // Label 365: @13147 GIM_Try, /*On fail goto*//*Label 392*/ 13178, // Rule ID 2952 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2952, GIR_Done, // Label 392: @13178 GIM_Reject, // Label 366: @13179 GIM_Try, /*On fail goto*//*Label 393*/ 13210, // Rule ID 2956 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2956, GIR_Done, // Label 393: @13210 GIM_Reject, // Label 367: @13211 GIM_Try, /*On fail goto*//*Label 394*/ 13242, // Rule ID 1276 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1276, GIR_Done, // Label 394: @13242 GIM_Reject, // Label 368: @13243 GIM_Try, /*On fail goto*//*Label 395*/ 13274, // Rule ID 2955 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2955, GIR_Done, // Label 395: @13274 GIM_Reject, // Label 369: @13275 GIM_Try, /*On fail goto*//*Label 396*/ 13306, // Rule ID 1277 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1277, GIR_Done, // Label 396: @13306 GIM_Reject, // Label 370: @13307 GIM_Reject, // Label 7: @13308 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 406*/ 14919, /*GILLT_s32*//*Label 397*/ 13328, /*GILLT_s64*//*Label 398*/ 14000, 0, 0, /*GILLT_v2s32*//*Label 399*/ 14695, /*GILLT_v2s64*//*Label 400*/ 14727, 0, /*GILLT_v4s16*//*Label 401*/ 14759, /*GILLT_v4s32*//*Label 402*/ 14791, 0, /*GILLT_v8s8*//*Label 403*/ 14823, /*GILLT_v8s16*//*Label 404*/ 14855, 0, /*GILLT_v16s8*//*Label 405*/ 14887, // Label 397: @13328 GIM_Try, /*On fail goto*//*Label 407*/ 13999, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 408*/ 13393, // Rule ID 5417 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5417, GIR_Done, // Label 408: @13393 GIM_Try, /*On fail goto*//*Label 409*/ 13448, // Rule ID 5416 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5416, GIR_Done, // Label 409: @13448 GIM_Try, /*On fail goto*//*Label 410*/ 13503, // Rule ID 5414 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5414, GIR_Done, // Label 410: @13503 GIM_Try, /*On fail goto*//*Label 411*/ 13558, // Rule ID 136 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 136, GIR_Done, // Label 411: @13558 GIM_Try, /*On fail goto*//*Label 412*/ 13613, // Rule ID 5415 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5415, GIR_Done, // Label 412: @13613 GIM_Try, /*On fail goto*//*Label 413*/ 13668, // Rule ID 5418 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5418, GIR_Done, // Label 413: @13668 GIM_Try, /*On fail goto*//*Label 414*/ 13710, // Rule ID 114 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<><>:$imm) => (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 114, GIR_Done, // Label 414: @13710 GIM_Try, /*On fail goto*//*Label 415*/ 13744, // Rule ID 5424 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5424, GIR_Done, // Label 415: @13744 GIM_Try, /*On fail goto*//*Label 416*/ 13778, // Rule ID 140 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 140, GIR_Done, // Label 416: @13778 GIM_Try, /*On fail goto*//*Label 417*/ 13833, // Rule ID 5410 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5410, GIR_Done, // Label 417: @13833 GIM_Try, /*On fail goto*//*Label 418*/ 13888, // Rule ID 134 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 134, GIR_Done, // Label 418: @13888 GIM_Try, /*On fail goto*//*Label 419*/ 13943, // Rule ID 5411 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5411, GIR_Done, // Label 419: @13943 GIM_Try, /*On fail goto*//*Label 420*/ 13977, // Rule ID 2404 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2404, GIR_Done, // Label 420: @13977 GIM_Try, /*On fail goto*//*Label 421*/ 13998, // Rule ID 138 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORWrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 138, GIR_Done, // Label 421: @13998 GIM_Reject, // Label 407: @13999 GIM_Reject, // Label 398: @14000 GIM_Try, /*On fail goto*//*Label 422*/ 14694, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 423*/ 14065, // Rule ID 5422 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5422, GIR_Done, // Label 423: @14065 GIM_Try, /*On fail goto*//*Label 424*/ 14120, // Rule ID 5421 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5421, GIR_Done, // Label 424: @14120 GIM_Try, /*On fail goto*//*Label 425*/ 14175, // Rule ID 5419 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5419, GIR_Done, // Label 425: @14175 GIM_Try, /*On fail goto*//*Label 426*/ 14230, // Rule ID 137 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 137, GIR_Done, // Label 426: @14230 GIM_Try, /*On fail goto*//*Label 427*/ 14285, // Rule ID 5420 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5420, GIR_Done, // Label 427: @14285 GIM_Try, /*On fail goto*//*Label 428*/ 14340, // Rule ID 5423 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5423, GIR_Done, // Label 428: @14340 GIM_Try, /*On fail goto*//*Label 429*/ 14382, // Rule ID 115 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<><>:$imm) => (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 115, GIR_Done, // Label 429: @14382 GIM_Try, /*On fail goto*//*Label 430*/ 14416, // Rule ID 5425 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5425, GIR_Done, // Label 430: @14416 GIM_Try, /*On fail goto*//*Label 431*/ 14450, // Rule ID 141 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 141, GIR_Done, // Label 431: @14450 GIM_Try, /*On fail goto*//*Label 432*/ 14505, // Rule ID 5412 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5412, GIR_Done, // Label 432: @14505 GIM_Try, /*On fail goto*//*Label 433*/ 14560, // Rule ID 135 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 135, GIR_Done, // Label 433: @14560 GIM_Try, /*On fail goto*//*Label 434*/ 14615, // Rule ID 5413 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5413, GIR_Done, // Label 434: @14615 GIM_Try, /*On fail goto*//*Label 435*/ 14649, // Rule ID 2405 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] }) => (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Xm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2405, GIR_Done, // Label 435: @14649 GIM_Try, /*On fail goto*//*Label 436*/ 14670, // Rule ID 139 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORXrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 139, GIR_Done, // Label 436: @14670 GIM_Try, /*On fail goto*//*Label 437*/ 14693, // Rule ID 2942 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2942, GIR_Done, // Label 437: @14693 GIM_Reject, // Label 422: @14694 GIM_Reject, // Label 399: @14695 GIM_Try, /*On fail goto*//*Label 438*/ 14726, // Rule ID 2941 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2941, GIR_Done, // Label 438: @14726 GIM_Reject, // Label 400: @14727 GIM_Try, /*On fail goto*//*Label 439*/ 14758, // Rule ID 2945 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2945, GIR_Done, // Label 439: @14758 GIM_Reject, // Label 401: @14759 GIM_Try, /*On fail goto*//*Label 440*/ 14790, // Rule ID 2940 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2940, GIR_Done, // Label 440: @14790 GIM_Reject, // Label 402: @14791 GIM_Try, /*On fail goto*//*Label 441*/ 14822, // Rule ID 2944 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2944, GIR_Done, // Label 441: @14822 GIM_Reject, // Label 403: @14823 GIM_Try, /*On fail goto*//*Label 442*/ 14854, // Rule ID 1272 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1272, GIR_Done, // Label 442: @14854 GIM_Reject, // Label 404: @14855 GIM_Try, /*On fail goto*//*Label 443*/ 14886, // Rule ID 2943 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2943, GIR_Done, // Label 443: @14886 GIM_Reject, // Label 405: @14887 GIM_Try, /*On fail goto*//*Label 444*/ 14918, // Rule ID 1273 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1273, GIR_Done, // Label 444: @14918 GIM_Reject, // Label 406: @14919 GIM_Reject, // Label 8: @14920 GIM_Try, /*On fail goto*//*Label 445*/ 21186, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 15, /*)*//*default:*//*Label 450*/ 21185, /*GILLT_v2s64*//*Label 446*/ 14940, 0, 0, /*GILLT_v4s32*//*Label 447*/ 15316, 0, 0, /*GILLT_v8s16*//*Label 448*/ 17438, 0, /*GILLT_v16s8*//*Label 449*/ 19418, // Label 446: @14940 GIM_Try, /*On fail goto*//*Label 451*/ 15315, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 452*/ 15014, // Rule ID 3286 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] })) => (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3286, GIR_Done, // Label 452: @15014 GIM_Try, /*On fail goto*//*Label 453*/ 15070, // Rule ID 3287 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] })) => (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3287, GIR_Done, // Label 453: @15070 GIM_Try, /*On fail goto*//*Label 454*/ 15192, // Rule ID 3279 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn) => (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3279, GIR_Done, // Label 454: @15192 GIM_Try, /*On fail goto*//*Label 455*/ 15314, // Rule ID 3280 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn) => (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3280, GIR_Done, // Label 455: @15314 GIM_Reject, // Label 451: @15315 GIM_Reject, // Label 447: @15316 GIM_Try, /*On fail goto*//*Label 456*/ 17437, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 457*/ 15446, // Rule ID 1910 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 368:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1910, GIR_Done, // Label 457: @15446 GIM_Try, /*On fail goto*//*Label 458*/ 15558, // Rule ID 3532 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 396:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3532, GIR_Done, // Label 458: @15558 GIM_Try, /*On fail goto*//*Label 459*/ 15670, // Rule ID 3535 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 397:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3535, GIR_Done, // Label 459: @15670 GIM_Try, /*On fail goto*//*Label 460*/ 15782, // Rule ID 3538 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 400:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3538, GIR_Done, // Label 460: @15782 GIM_Try, /*On fail goto*//*Label 461*/ 15894, // Rule ID 3541 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 401:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3541, GIR_Done, // Label 461: @15894 GIM_Try, /*On fail goto*//*Label 462*/ 16006, // Rule ID 3545 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 444:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3545, GIR_Done, // Label 462: @16006 GIM_Try, /*On fail goto*//*Label 463*/ 16118, // Rule ID 3548 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3548, GIR_Done, // Label 463: @16118 GIM_Try, /*On fail goto*//*Label 464*/ 16223, // Rule ID 1879 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 309:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1879, GIR_Done, // Label 464: @16223 GIM_Try, /*On fail goto*//*Label 465*/ 16328, // Rule ID 3070 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 418:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3070, GIR_Done, // Label 465: @16328 GIM_Try, /*On fail goto*//*Label 466*/ 16433, // Rule ID 3073 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 366:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3073, GIR_Done, // Label 466: @16433 GIM_Try, /*On fail goto*//*Label 467*/ 16538, // Rule ID 3076 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 369:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3076, GIR_Done, // Label 467: @16538 GIM_Try, /*On fail goto*//*Label 468*/ 16631, // Rule ID 1875 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 403:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1875, GIR_Done, // Label 468: @16631 GIM_Try, /*On fail goto*//*Label 469*/ 16724, // Rule ID 1876 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 325:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)) => (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1876, GIR_Done, // Label 469: @16724 GIM_Try, /*On fail goto*//*Label 470*/ 16817, // Rule ID 2868 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 404:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTUNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2868, GIR_Done, // Label 470: @16817 GIM_Try, /*On fail goto*//*Label 471*/ 16910, // Rule ID 2871 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 448:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (UQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2871, GIR_Done, // Label 471: @16910 GIM_Try, /*On fail goto*//*Label 472*/ 16994, // Rule ID 2835 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)) => (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2835, GIR_Done, // Label 472: @16994 GIM_Try, /*On fail goto*//*Label 473*/ 17080, // Rule ID 2874 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)) => (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2874, GIR_Done, // Label 473: @17080 GIM_Try, /*On fail goto*//*Label 474*/ 17136, // Rule ID 3288 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] })) => (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3288, GIR_Done, // Label 474: @17136 GIM_Try, /*On fail goto*//*Label 475*/ 17192, // Rule ID 3289 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] })) => (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3289, GIR_Done, // Label 475: @17192 GIM_Try, /*On fail goto*//*Label 476*/ 17314, // Rule ID 3281 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3281, GIR_Done, // Label 476: @17314 GIM_Try, /*On fail goto*//*Label 477*/ 17436, // Rule ID 3282 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn) => (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3282, GIR_Done, // Label 477: @17436 GIM_Reject, // Label 456: @17437 GIM_Reject, // Label 448: @17438 GIM_Try, /*On fail goto*//*Label 478*/ 19417, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 479*/ 17568, // Rule ID 1909 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 368:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (RSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1909, GIR_Done, // Label 479: @17568 GIM_Try, /*On fail goto*//*Label 480*/ 17680, // Rule ID 3531 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 396:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3531, GIR_Done, // Label 480: @17680 GIM_Try, /*On fail goto*//*Label 481*/ 17792, // Rule ID 3534 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 397:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3534, GIR_Done, // Label 481: @17792 GIM_Try, /*On fail goto*//*Label 482*/ 17904, // Rule ID 3537 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 400:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3537, GIR_Done, // Label 482: @17904 GIM_Try, /*On fail goto*//*Label 483*/ 18016, // Rule ID 3540 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 401:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3540, GIR_Done, // Label 483: @18016 GIM_Try, /*On fail goto*//*Label 484*/ 18128, // Rule ID 3544 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 444:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3544, GIR_Done, // Label 484: @18128 GIM_Try, /*On fail goto*//*Label 485*/ 18240, // Rule ID 3547 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3547, GIR_Done, // Label 485: @18240 GIM_Try, /*On fail goto*//*Label 486*/ 18345, // Rule ID 1878 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 309:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1878, GIR_Done, // Label 486: @18345 GIM_Try, /*On fail goto*//*Label 487*/ 18450, // Rule ID 3069 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 418:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3069, GIR_Done, // Label 487: @18450 GIM_Try, /*On fail goto*//*Label 488*/ 18555, // Rule ID 3072 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 366:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3072, GIR_Done, // Label 488: @18555 GIM_Try, /*On fail goto*//*Label 489*/ 18660, // Rule ID 3075 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 369:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3075, GIR_Done, // Label 489: @18660 GIM_Try, /*On fail goto*//*Label 490*/ 18753, // Rule ID 1874 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 403:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1874, GIR_Done, // Label 490: @18753 GIM_Try, /*On fail goto*//*Label 491*/ 18844, // Rule ID 2832 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 461:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)) => (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2832, GIR_Done, // Label 491: @18844 GIM_Try, /*On fail goto*//*Label 492*/ 18937, // Rule ID 2867 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 404:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTUNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2867, GIR_Done, // Label 492: @18937 GIM_Try, /*On fail goto*//*Label 493*/ 19030, // Rule ID 2870 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 448:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2870, GIR_Done, // Label 493: @19030 GIM_Try, /*On fail goto*//*Label 494*/ 19116, // Rule ID 2873 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)) => (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2873, GIR_Done, // Label 494: @19116 GIM_Try, /*On fail goto*//*Label 495*/ 19172, // Rule ID 3290 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] })) => (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3290, GIR_Done, // Label 495: @19172 GIM_Try, /*On fail goto*//*Label 496*/ 19294, // Rule ID 3283 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3283, GIR_Done, // Label 496: @19294 GIM_Try, /*On fail goto*//*Label 497*/ 19416, // Rule ID 3284 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn) => (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3284, GIR_Done, // Label 497: @19416 GIM_Reject, // Label 478: @19417 GIM_Reject, // Label 449: @19418 GIM_Try, /*On fail goto*//*Label 498*/ 21184, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 499*/ 19548, // Rule ID 1908 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 368:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (RSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1908, GIR_Done, // Label 499: @19548 GIM_Try, /*On fail goto*//*Label 500*/ 19660, // Rule ID 3530 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 396:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3530, GIR_Done, // Label 500: @19660 GIM_Try, /*On fail goto*//*Label 501*/ 19772, // Rule ID 3533 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 397:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQRSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3533, GIR_Done, // Label 501: @19772 GIM_Try, /*On fail goto*//*Label 502*/ 19884, // Rule ID 3536 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 400:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3536, GIR_Done, // Label 502: @19884 GIM_Try, /*On fail goto*//*Label 503*/ 19996, // Rule ID 3539 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 401:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (SQSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3539, GIR_Done, // Label 503: @19996 GIM_Try, /*On fail goto*//*Label 504*/ 20108, // Rule ID 3543 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 444:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3543, GIR_Done, // Label 504: @20108 GIM_Try, /*On fail goto*//*Label 505*/ 20220, // Rule ID 3546 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 446:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm)) => (UQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3546, GIR_Done, // Label 505: @20220 GIM_Try, /*On fail goto*//*Label 506*/ 20325, // Rule ID 1877 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 309:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1877, GIR_Done, // Label 506: @20325 GIM_Try, /*On fail goto*//*Label 507*/ 20430, // Rule ID 3068 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 418:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3068, GIR_Done, // Label 507: @20430 GIM_Try, /*On fail goto*//*Label 508*/ 20535, // Rule ID 3071 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 366:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3071, GIR_Done, // Label 508: @20535 GIM_Try, /*On fail goto*//*Label 509*/ 20640, // Rule ID 3074 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 369:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3074, GIR_Done, // Label 509: @20640 GIM_Try, /*On fail goto*//*Label 510*/ 20733, // Rule ID 1873 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 403:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1873, GIR_Done, // Label 510: @20733 GIM_Try, /*On fail goto*//*Label 511*/ 20826, // Rule ID 2866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 404:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTUNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2866, GIR_Done, // Label 511: @20826 GIM_Try, /*On fail goto*//*Label 512*/ 20919, // Rule ID 2869 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 448:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2869, GIR_Done, // Label 512: @20919 GIM_Try, /*On fail goto*//*Label 513*/ 21005, // Rule ID 2872 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)) => (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2872, GIR_Done, // Label 513: @21005 GIM_Try, /*On fail goto*//*Label 514*/ 21061, // Rule ID 3291 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, GIM_CheckIsSafeToFold, /*InsnID*/1, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] })) => (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR64*/16, // GIR_Coverage, 3291, GIR_Done, // Label 514: @21061 GIM_Try, /*On fail goto*//*Label 515*/ 21183, // Rule ID 3285 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/3, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3285, GIR_Done, // Label 515: @21183 GIM_Reject, // Label 498: @21184 GIM_Reject, // Label 450: @21185 GIM_Reject, // Label 445: @21186 GIM_Reject, // Label 9: @21187 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 526*/ 30111, /*GILLT_s32*//*Label 516*/ 21207, /*GILLT_s64*//*Label 517*/ 21253, /*GILLT_s128*//*Label 518*/ 22829, 0, /*GILLT_v2s32*//*Label 519*/ 23501, /*GILLT_v2s64*//*Label 520*/ 24396, 0, /*GILLT_v4s16*//*Label 521*/ 25585, /*GILLT_v4s32*//*Label 522*/ 26480, 0, /*GILLT_v8s8*//*Label 523*/ 27733, /*GILLT_v8s16*//*Label 524*/ 28206, 0, /*GILLT_v16s8*//*Label 525*/ 29459, // Label 516: @21207 GIM_Try, /*On fail goto*//*Label 527*/ 21252, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 528*/ 21232, // Rule ID 3802 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, // GIR_Coverage, 3802, GIR_Done, // Label 528: @21232 GIM_Try, /*On fail goto*//*Label 529*/ 21251, // Rule ID 3803 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/6, // GIR_Coverage, 3803, GIR_Done, // Label 529: @21251 GIM_Reject, // Label 527: @21252 GIM_Reject, // Label 517: @21253 GIM_Try, /*On fail goto*//*Label 530*/ 21278, // Rule ID 3780 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3780, GIR_Done, // Label 530: @21278 GIM_Try, /*On fail goto*//*Label 531*/ 21303, // Rule ID 3781 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3781, GIR_Done, // Label 531: @21303 GIM_Try, /*On fail goto*//*Label 532*/ 21328, // Rule ID 3782 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3782, GIR_Done, // Label 532: @21328 GIM_Try, /*On fail goto*//*Label 533*/ 21353, // Rule ID 3783 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3783, GIR_Done, // Label 533: @21353 GIM_Try, /*On fail goto*//*Label 534*/ 21378, // Rule ID 3784 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3784, GIR_Done, // Label 534: @21378 GIM_Try, /*On fail goto*//*Label 535*/ 21403, // Rule ID 3785 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3785, GIR_Done, // Label 535: @21403 GIM_Try, /*On fail goto*//*Label 536*/ 21451, // Rule ID 3791 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3791, GIR_Done, // Label 536: @21451 GIM_Try, /*On fail goto*//*Label 537*/ 21499, // Rule ID 3792 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3792, GIR_Done, // Label 537: @21499 GIM_Try, /*On fail goto*//*Label 538*/ 21547, // Rule ID 3793 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3793, GIR_Done, // Label 538: @21547 GIM_Try, /*On fail goto*//*Label 539*/ 21595, // Rule ID 3794 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3794, GIR_Done, // Label 539: @21595 GIM_Try, /*On fail goto*//*Label 540*/ 21643, // Rule ID 3795 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3795, GIR_Done, // Label 540: @21643 GIM_Try, /*On fail goto*//*Label 541*/ 21666, // Rule ID 3796 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3796, GIR_Done, // Label 541: @21666 GIM_Try, /*On fail goto*//*Label 542*/ 21689, // Rule ID 3797 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3797, GIR_Done, // Label 542: @21689 GIM_Try, /*On fail goto*//*Label 543*/ 21712, // Rule ID 3798 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3798, GIR_Done, // Label 543: @21712 GIM_Try, /*On fail goto*//*Label 544*/ 21735, // Rule ID 3804 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3804, GIR_Done, // Label 544: @21735 GIM_Try, /*On fail goto*//*Label 545*/ 21758, // Rule ID 3805 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3805, GIR_Done, // Label 545: @21758 GIM_Try, /*On fail goto*//*Label 546*/ 21781, // Rule ID 3806 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64*/17, // GIR_Coverage, 3806, GIR_Done, // Label 546: @21781 GIM_Try, /*On fail goto*//*Label 547*/ 21815, // Rule ID 3807 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3807, GIR_Done, // Label 547: @21815 GIM_Try, /*On fail goto*//*Label 548*/ 21849, // Rule ID 3808 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3808, GIR_Done, // Label 548: @21849 GIM_Try, /*On fail goto*//*Label 549*/ 21883, // Rule ID 3809 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3809, GIR_Done, // Label 549: @21883 GIM_Try, /*On fail goto*//*Label 550*/ 21917, // Rule ID 3810 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3810, GIR_Done, // Label 550: @21917 GIM_Try, /*On fail goto*//*Label 551*/ 21951, // Rule ID 3811 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3811, GIR_Done, // Label 551: @21951 GIM_Try, /*On fail goto*//*Label 552*/ 21974, // Rule ID 3812 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3812, GIR_Done, // Label 552: @21974 GIM_Try, /*On fail goto*//*Label 553*/ 21997, // Rule ID 3813 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3813, GIR_Done, // Label 553: @21997 GIM_Try, /*On fail goto*//*Label 554*/ 22020, // Rule ID 3814 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3814, GIR_Done, // Label 554: @22020 GIM_Try, /*On fail goto*//*Label 555*/ 22043, // Rule ID 3815 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3815, GIR_Done, // Label 555: @22043 GIM_Try, /*On fail goto*//*Label 556*/ 22066, // Rule ID 3816 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3816, GIR_Done, // Label 556: @22066 GIM_Try, /*On fail goto*//*Label 557*/ 22098, // Rule ID 3817 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3817, GIR_Done, // Label 557: @22098 GIM_Try, /*On fail goto*//*Label 558*/ 22130, // Rule ID 3818 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3818, GIR_Done, // Label 558: @22130 GIM_Try, /*On fail goto*//*Label 559*/ 22164, // Rule ID 3872 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3872, GIR_Done, // Label 559: @22164 GIM_Try, /*On fail goto*//*Label 560*/ 22198, // Rule ID 3873 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3873, GIR_Done, // Label 560: @22198 GIM_Try, /*On fail goto*//*Label 561*/ 22232, // Rule ID 3874 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3874, GIR_Done, // Label 561: @22232 GIM_Try, /*On fail goto*//*Label 562*/ 22266, // Rule ID 3875 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3875, GIR_Done, // Label 562: @22266 GIM_Try, /*On fail goto*//*Label 563*/ 22300, // Rule ID 3876 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3876, GIR_Done, // Label 563: @22300 GIM_Try, /*On fail goto*//*Label 564*/ 22323, // Rule ID 3877 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3877, GIR_Done, // Label 564: @22323 GIM_Try, /*On fail goto*//*Label 565*/ 22346, // Rule ID 3878 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3878, GIR_Done, // Label 565: @22346 GIM_Try, /*On fail goto*//*Label 566*/ 22369, // Rule ID 3879 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3879, GIR_Done, // Label 566: @22369 GIM_Try, /*On fail goto*//*Label 567*/ 22392, // Rule ID 3880 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3880, GIR_Done, // Label 567: @22392 GIM_Try, /*On fail goto*//*Label 568*/ 22415, // Rule ID 3881 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3881, GIR_Done, // Label 568: @22415 GIM_Try, /*On fail goto*//*Label 569*/ 22447, // Rule ID 3882 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3882, GIR_Done, // Label 569: @22447 GIM_Try, /*On fail goto*//*Label 570*/ 22479, // Rule ID 3883 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3883, GIR_Done, // Label 570: @22479 GIM_Try, /*On fail goto*//*Label 571*/ 22513, // Rule ID 3884 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3884, GIR_Done, // Label 571: @22513 GIM_Try, /*On fail goto*//*Label 572*/ 22547, // Rule ID 3885 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3885, GIR_Done, // Label 572: @22547 GIM_Try, /*On fail goto*//*Label 573*/ 22581, // Rule ID 3886 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3886, GIR_Done, // Label 573: @22581 GIM_Try, /*On fail goto*//*Label 574*/ 22615, // Rule ID 3887 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3887, GIR_Done, // Label 574: @22615 GIM_Try, /*On fail goto*//*Label 575*/ 22649, // Rule ID 3888 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3888, GIR_Done, // Label 575: @22649 GIM_Try, /*On fail goto*//*Label 576*/ 22672, // Rule ID 3889 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3889, GIR_Done, // Label 576: @22672 GIM_Try, /*On fail goto*//*Label 577*/ 22695, // Rule ID 3890 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3890, GIR_Done, // Label 577: @22695 GIM_Try, /*On fail goto*//*Label 578*/ 22718, // Rule ID 3891 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3891, GIR_Done, // Label 578: @22718 GIM_Try, /*On fail goto*//*Label 579*/ 22741, // Rule ID 3892 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3892, GIR_Done, // Label 579: @22741 GIM_Try, /*On fail goto*//*Label 580*/ 22764, // Rule ID 3893 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3893, GIR_Done, // Label 580: @22764 GIM_Try, /*On fail goto*//*Label 581*/ 22796, // Rule ID 3894 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3894, GIR_Done, // Label 581: @22796 GIM_Try, /*On fail goto*//*Label 582*/ 22828, // Rule ID 3895 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3895, GIR_Done, // Label 582: @22828 GIM_Reject, // Label 518: @22829 GIM_Try, /*On fail goto*//*Label 583*/ 22863, // Rule ID 3909 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3909, GIR_Done, // Label 583: @22863 GIM_Try, /*On fail goto*//*Label 584*/ 22897, // Rule ID 3910 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3910, GIR_Done, // Label 584: @22897 GIM_Try, /*On fail goto*//*Label 585*/ 22931, // Rule ID 3911 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3911, GIR_Done, // Label 585: @22931 GIM_Try, /*On fail goto*//*Label 586*/ 22965, // Rule ID 3912 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3912, GIR_Done, // Label 586: @22965 GIM_Try, /*On fail goto*//*Label 587*/ 22999, // Rule ID 3913 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3913, GIR_Done, // Label 587: @22999 GIM_Try, /*On fail goto*//*Label 588*/ 23033, // Rule ID 3914 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3914, GIR_Done, // Label 588: @23033 GIM_Try, /*On fail goto*//*Label 589*/ 23067, // Rule ID 3915 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[f128] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3915, GIR_Done, // Label 589: @23067 GIM_Try, /*On fail goto*//*Label 590*/ 23106, // Rule ID 3916 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3916, GIR_Done, // Label 590: @23106 GIM_Try, /*On fail goto*//*Label 591*/ 23177, // Rule ID 3917 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3917, GIR_Done, // Label 591: @23177 GIM_Try, /*On fail goto*//*Label 592*/ 23248, // Rule ID 3918 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3918, GIR_Done, // Label 592: @23248 GIM_Try, /*On fail goto*//*Label 593*/ 23319, // Rule ID 3919 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3919, GIR_Done, // Label 593: @23319 GIM_Try, /*On fail goto*//*Label 594*/ 23358, // Rule ID 3920 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3920, GIR_Done, // Label 594: @23358 GIM_Try, /*On fail goto*//*Label 595*/ 23429, // Rule ID 3921 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3921, GIR_Done, // Label 595: @23429 GIM_Try, /*On fail goto*//*Label 596*/ 23500, // Rule ID 3922 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3922, GIR_Done, // Label 596: @23500 GIM_Reject, // Label 519: @23501 GIM_Try, /*On fail goto*//*Label 597*/ 23526, // Rule ID 3777 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3777, GIR_Done, // Label 597: @23526 GIM_Try, /*On fail goto*//*Label 598*/ 23551, // Rule ID 3779 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3779, GIR_Done, // Label 598: @23551 GIM_Try, /*On fail goto*//*Label 599*/ 23599, // Rule ID 3788 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3788, GIR_Done, // Label 599: @23599 GIM_Try, /*On fail goto*//*Label 600*/ 23647, // Rule ID 3790 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3790, GIR_Done, // Label 600: @23647 GIM_Try, /*On fail goto*//*Label 601*/ 23681, // Rule ID 3819 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3819, GIR_Done, // Label 601: @23681 GIM_Try, /*On fail goto*//*Label 602*/ 23715, // Rule ID 3820 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3820, GIR_Done, // Label 602: @23715 GIM_Try, /*On fail goto*//*Label 603*/ 23749, // Rule ID 3821 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3821, GIR_Done, // Label 603: @23749 GIM_Try, /*On fail goto*//*Label 604*/ 23783, // Rule ID 3822 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3822, GIR_Done, // Label 604: @23783 GIM_Try, /*On fail goto*//*Label 605*/ 23817, // Rule ID 3823 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3823, GIR_Done, // Label 605: @23817 GIM_Try, /*On fail goto*//*Label 606*/ 23851, // Rule ID 3824 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3824, GIR_Done, // Label 606: @23851 GIM_Try, /*On fail goto*//*Label 607*/ 23874, // Rule ID 3825 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3825, GIR_Done, // Label 607: @23874 GIM_Try, /*On fail goto*//*Label 608*/ 23897, // Rule ID 3826 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3826, GIR_Done, // Label 608: @23897 GIM_Try, /*On fail goto*//*Label 609*/ 23920, // Rule ID 3827 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3827, GIR_Done, // Label 609: @23920 GIM_Try, /*On fail goto*//*Label 610*/ 23943, // Rule ID 3828 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3828, GIR_Done, // Label 610: @23943 GIM_Try, /*On fail goto*//*Label 611*/ 23966, // Rule ID 3829 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3829, GIR_Done, // Label 611: @23966 GIM_Try, /*On fail goto*//*Label 612*/ 23989, // Rule ID 3830 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3830, GIR_Done, // Label 612: @23989 GIM_Try, /*On fail goto*//*Label 613*/ 24021, // Rule ID 3831 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3831, GIR_Done, // Label 613: @24021 GIM_Try, /*On fail goto*//*Label 614*/ 24055, // Rule ID 3896 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3896, GIR_Done, // Label 614: @24055 GIM_Try, /*On fail goto*//*Label 615*/ 24089, // Rule ID 3897 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3897, GIR_Done, // Label 615: @24089 GIM_Try, /*On fail goto*//*Label 616*/ 24123, // Rule ID 3898 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3898, GIR_Done, // Label 616: @24123 GIM_Try, /*On fail goto*//*Label 617*/ 24157, // Rule ID 3899 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3899, GIR_Done, // Label 617: @24157 GIM_Try, /*On fail goto*//*Label 618*/ 24191, // Rule ID 3900 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3900, GIR_Done, // Label 618: @24191 GIM_Try, /*On fail goto*//*Label 619*/ 24225, // Rule ID 3901 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3901, GIR_Done, // Label 619: @24225 GIM_Try, /*On fail goto*//*Label 620*/ 24248, // Rule ID 3902 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3902, GIR_Done, // Label 620: @24248 GIM_Try, /*On fail goto*//*Label 621*/ 24271, // Rule ID 3903 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3903, GIR_Done, // Label 621: @24271 GIM_Try, /*On fail goto*//*Label 622*/ 24294, // Rule ID 3904 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3904, GIR_Done, // Label 622: @24294 GIM_Try, /*On fail goto*//*Label 623*/ 24317, // Rule ID 3905 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3905, GIR_Done, // Label 623: @24317 GIM_Try, /*On fail goto*//*Label 624*/ 24340, // Rule ID 3906 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3906, GIR_Done, // Label 624: @24340 GIM_Try, /*On fail goto*//*Label 625*/ 24363, // Rule ID 3907 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3907, GIR_Done, // Label 625: @24363 GIM_Try, /*On fail goto*//*Label 626*/ 24395, // Rule ID 3908 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3908, GIR_Done, // Label 626: @24395 GIM_Reject, // Label 520: @24396 GIM_Try, /*On fail goto*//*Label 627*/ 24430, // Rule ID 3923 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3923, GIR_Done, // Label 627: @24430 GIM_Try, /*On fail goto*//*Label 628*/ 24464, // Rule ID 3924 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3924, GIR_Done, // Label 628: @24464 GIM_Try, /*On fail goto*//*Label 629*/ 24498, // Rule ID 3925 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3925, GIR_Done, // Label 629: @24498 GIM_Try, /*On fail goto*//*Label 630*/ 24532, // Rule ID 3926 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3926, GIR_Done, // Label 630: @24532 GIM_Try, /*On fail goto*//*Label 631*/ 24566, // Rule ID 3927 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3927, GIR_Done, // Label 631: @24566 GIM_Try, /*On fail goto*//*Label 632*/ 24600, // Rule ID 3928 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3928, GIR_Done, // Label 632: @24600 GIM_Try, /*On fail goto*//*Label 633*/ 24639, // Rule ID 3929 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3929, GIR_Done, // Label 633: @24639 GIM_Try, /*On fail goto*//*Label 634*/ 24662, // Rule ID 3930 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3930, GIR_Done, // Label 634: @24662 GIM_Try, /*On fail goto*//*Label 635*/ 24685, // Rule ID 3931 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3931, GIR_Done, // Label 635: @24685 GIM_Try, /*On fail goto*//*Label 636*/ 24708, // Rule ID 3932 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3932, GIR_Done, // Label 636: @24708 GIM_Try, /*On fail goto*//*Label 637*/ 24731, // Rule ID 3933 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3933, GIR_Done, // Label 637: @24731 GIM_Try, /*On fail goto*//*Label 638*/ 24754, // Rule ID 3934 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3934, GIR_Done, // Label 638: @24754 GIM_Try, /*On fail goto*//*Label 639*/ 24786, // Rule ID 3935 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3935, GIR_Done, // Label 639: @24786 GIM_Try, /*On fail goto*//*Label 640*/ 24820, // Rule ID 3949 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3949, GIR_Done, // Label 640: @24820 GIM_Try, /*On fail goto*//*Label 641*/ 24854, // Rule ID 3950 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3950, GIR_Done, // Label 641: @24854 GIM_Try, /*On fail goto*//*Label 642*/ 24888, // Rule ID 3951 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3951, GIR_Done, // Label 642: @24888 GIM_Try, /*On fail goto*//*Label 643*/ 24922, // Rule ID 3952 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3952, GIR_Done, // Label 643: @24922 GIM_Try, /*On fail goto*//*Label 644*/ 24956, // Rule ID 3953 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3953, GIR_Done, // Label 644: @24956 GIM_Try, /*On fail goto*//*Label 645*/ 24990, // Rule ID 3954 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3954, GIR_Done, // Label 645: @24990 GIM_Try, /*On fail goto*//*Label 646*/ 25029, // Rule ID 3955 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3955, GIR_Done, // Label 646: @25029 GIM_Try, /*On fail goto*//*Label 647*/ 25052, // Rule ID 3956 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3956, GIR_Done, // Label 647: @25052 GIM_Try, /*On fail goto*//*Label 648*/ 25075, // Rule ID 3957 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3957, GIR_Done, // Label 648: @25075 GIM_Try, /*On fail goto*//*Label 649*/ 25098, // Rule ID 3958 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3958, GIR_Done, // Label 649: @25098 GIM_Try, /*On fail goto*//*Label 650*/ 25121, // Rule ID 3959 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3959, GIR_Done, // Label 650: @25121 GIM_Try, /*On fail goto*//*Label 651*/ 25144, // Rule ID 3960 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3960, GIR_Done, // Label 651: @25144 GIM_Try, /*On fail goto*//*Label 652*/ 25176, // Rule ID 3961 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3961, GIR_Done, // Label 652: @25176 GIM_Try, /*On fail goto*//*Label 653*/ 25210, // Rule ID 5192 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5192, GIR_Done, // Label 653: @25210 GIM_Try, /*On fail goto*//*Label 654*/ 25244, // Rule ID 5193 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5193, GIR_Done, // Label 654: @25244 GIM_Try, /*On fail goto*//*Label 655*/ 25278, // Rule ID 5194 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5194, GIR_Done, // Label 655: @25278 GIM_Try, /*On fail goto*//*Label 656*/ 25312, // Rule ID 5195 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5195, GIR_Done, // Label 656: @25312 GIM_Try, /*On fail goto*//*Label 657*/ 25346, // Rule ID 5196 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5196, GIR_Done, // Label 657: @25346 GIM_Try, /*On fail goto*//*Label 658*/ 25380, // Rule ID 5197 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5197, GIR_Done, // Label 658: @25380 GIM_Try, /*On fail goto*//*Label 659*/ 25414, // Rule ID 5210 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5210, GIR_Done, // Label 659: @25414 GIM_Try, /*On fail goto*//*Label 660*/ 25448, // Rule ID 5211 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5211, GIR_Done, // Label 660: @25448 GIM_Try, /*On fail goto*//*Label 661*/ 25482, // Rule ID 5212 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5212, GIR_Done, // Label 661: @25482 GIM_Try, /*On fail goto*//*Label 662*/ 25516, // Rule ID 5213 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5213, GIR_Done, // Label 662: @25516 GIM_Try, /*On fail goto*//*Label 663*/ 25550, // Rule ID 5214 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5214, GIR_Done, // Label 663: @25550 GIM_Try, /*On fail goto*//*Label 664*/ 25584, // Rule ID 5215 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5215, GIR_Done, // Label 664: @25584 GIM_Reject, // Label 521: @25585 GIM_Try, /*On fail goto*//*Label 665*/ 25610, // Rule ID 3776 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3776, GIR_Done, // Label 665: @25610 GIM_Try, /*On fail goto*//*Label 666*/ 25635, // Rule ID 3778 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3778, GIR_Done, // Label 666: @25635 GIM_Try, /*On fail goto*//*Label 667*/ 25683, // Rule ID 3787 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3787, GIR_Done, // Label 667: @25683 GIM_Try, /*On fail goto*//*Label 668*/ 25731, // Rule ID 3789 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3789, GIR_Done, // Label 668: @25731 GIM_Try, /*On fail goto*//*Label 669*/ 25765, // Rule ID 3832 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3832, GIR_Done, // Label 669: @25765 GIM_Try, /*On fail goto*//*Label 670*/ 25799, // Rule ID 3833 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3833, GIR_Done, // Label 670: @25799 GIM_Try, /*On fail goto*//*Label 671*/ 25833, // Rule ID 3834 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3834, GIR_Done, // Label 671: @25833 GIM_Try, /*On fail goto*//*Label 672*/ 25867, // Rule ID 3835 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3835, GIR_Done, // Label 672: @25867 GIM_Try, /*On fail goto*//*Label 673*/ 25901, // Rule ID 3836 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3836, GIR_Done, // Label 673: @25901 GIM_Try, /*On fail goto*//*Label 674*/ 25935, // Rule ID 3837 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3837, GIR_Done, // Label 674: @25935 GIM_Try, /*On fail goto*//*Label 675*/ 25958, // Rule ID 3838 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3838, GIR_Done, // Label 675: @25958 GIM_Try, /*On fail goto*//*Label 676*/ 25981, // Rule ID 3839 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3839, GIR_Done, // Label 676: @25981 GIM_Try, /*On fail goto*//*Label 677*/ 26004, // Rule ID 3840 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3840, GIR_Done, // Label 677: @26004 GIM_Try, /*On fail goto*//*Label 678*/ 26027, // Rule ID 3841 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3841, GIR_Done, // Label 678: @26027 GIM_Try, /*On fail goto*//*Label 679*/ 26050, // Rule ID 3842 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3842, GIR_Done, // Label 679: @26050 GIM_Try, /*On fail goto*//*Label 680*/ 26073, // Rule ID 3843 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3843, GIR_Done, // Label 680: @26073 GIM_Try, /*On fail goto*//*Label 681*/ 26105, // Rule ID 3844 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3844, GIR_Done, // Label 681: @26105 GIM_Try, /*On fail goto*//*Label 682*/ 26139, // Rule ID 3845 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3845, GIR_Done, // Label 682: @26139 GIM_Try, /*On fail goto*//*Label 683*/ 26173, // Rule ID 3846 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3846, GIR_Done, // Label 683: @26173 GIM_Try, /*On fail goto*//*Label 684*/ 26207, // Rule ID 3847 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3847, GIR_Done, // Label 684: @26207 GIM_Try, /*On fail goto*//*Label 685*/ 26241, // Rule ID 3848 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3848, GIR_Done, // Label 685: @26241 GIM_Try, /*On fail goto*//*Label 686*/ 26275, // Rule ID 3849 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3849, GIR_Done, // Label 686: @26275 GIM_Try, /*On fail goto*//*Label 687*/ 26309, // Rule ID 3850 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3850, GIR_Done, // Label 687: @26309 GIM_Try, /*On fail goto*//*Label 688*/ 26332, // Rule ID 3851 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3851, GIR_Done, // Label 688: @26332 GIM_Try, /*On fail goto*//*Label 689*/ 26355, // Rule ID 3852 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3852, GIR_Done, // Label 689: @26355 GIM_Try, /*On fail goto*//*Label 690*/ 26378, // Rule ID 3853 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3853, GIR_Done, // Label 690: @26378 GIM_Try, /*On fail goto*//*Label 691*/ 26401, // Rule ID 3854 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3854, GIR_Done, // Label 691: @26401 GIM_Try, /*On fail goto*//*Label 692*/ 26424, // Rule ID 3855 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3855, GIR_Done, // Label 692: @26424 GIM_Try, /*On fail goto*//*Label 693*/ 26447, // Rule ID 3856 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3856, GIR_Done, // Label 693: @26447 GIM_Try, /*On fail goto*//*Label 694*/ 26479, // Rule ID 3857 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3857, GIR_Done, // Label 694: @26479 GIM_Reject, // Label 522: @26480 GIM_Try, /*On fail goto*//*Label 695*/ 26514, // Rule ID 3936 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3936, GIR_Done, // Label 695: @26514 GIM_Try, /*On fail goto*//*Label 696*/ 26548, // Rule ID 3937 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3937, GIR_Done, // Label 696: @26548 GIM_Try, /*On fail goto*//*Label 697*/ 26582, // Rule ID 3938 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3938, GIR_Done, // Label 697: @26582 GIM_Try, /*On fail goto*//*Label 698*/ 26616, // Rule ID 3939 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3939, GIR_Done, // Label 698: @26616 GIM_Try, /*On fail goto*//*Label 699*/ 26650, // Rule ID 3940 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3940, GIR_Done, // Label 699: @26650 GIM_Try, /*On fail goto*//*Label 700*/ 26684, // Rule ID 3941 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3941, GIR_Done, // Label 700: @26684 GIM_Try, /*On fail goto*//*Label 701*/ 26755, // Rule ID 3942 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3942, GIR_Done, // Label 701: @26755 GIM_Try, /*On fail goto*//*Label 702*/ 26778, // Rule ID 3943 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3943, GIR_Done, // Label 702: @26778 GIM_Try, /*On fail goto*//*Label 703*/ 26801, // Rule ID 3944 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3944, GIR_Done, // Label 703: @26801 GIM_Try, /*On fail goto*//*Label 704*/ 26824, // Rule ID 3945 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3945, GIR_Done, // Label 704: @26824 GIM_Try, /*On fail goto*//*Label 705*/ 26847, // Rule ID 3946 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3946, GIR_Done, // Label 705: @26847 GIM_Try, /*On fail goto*//*Label 706*/ 26870, // Rule ID 3947 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3947, GIR_Done, // Label 706: @26870 GIM_Try, /*On fail goto*//*Label 707*/ 26902, // Rule ID 3948 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3948, GIR_Done, // Label 707: @26902 GIM_Try, /*On fail goto*//*Label 708*/ 26936, // Rule ID 3962 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3962, GIR_Done, // Label 708: @26936 GIM_Try, /*On fail goto*//*Label 709*/ 26970, // Rule ID 3963 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3963, GIR_Done, // Label 709: @26970 GIM_Try, /*On fail goto*//*Label 710*/ 27004, // Rule ID 3964 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3964, GIR_Done, // Label 710: @27004 GIM_Try, /*On fail goto*//*Label 711*/ 27038, // Rule ID 3965 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3965, GIR_Done, // Label 711: @27038 GIM_Try, /*On fail goto*//*Label 712*/ 27072, // Rule ID 3966 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3966, GIR_Done, // Label 712: @27072 GIM_Try, /*On fail goto*//*Label 713*/ 27106, // Rule ID 3967 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3967, GIR_Done, // Label 713: @27106 GIM_Try, /*On fail goto*//*Label 714*/ 27177, // Rule ID 3968 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3968, GIR_Done, // Label 714: @27177 GIM_Try, /*On fail goto*//*Label 715*/ 27200, // Rule ID 3969 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3969, GIR_Done, // Label 715: @27200 GIM_Try, /*On fail goto*//*Label 716*/ 27223, // Rule ID 3970 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3970, GIR_Done, // Label 716: @27223 GIM_Try, /*On fail goto*//*Label 717*/ 27246, // Rule ID 3971 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3971, GIR_Done, // Label 717: @27246 GIM_Try, /*On fail goto*//*Label 718*/ 27269, // Rule ID 3972 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3972, GIR_Done, // Label 718: @27269 GIM_Try, /*On fail goto*//*Label 719*/ 27292, // Rule ID 3973 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3973, GIR_Done, // Label 719: @27292 GIM_Try, /*On fail goto*//*Label 720*/ 27324, // Rule ID 3974 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3974, GIR_Done, // Label 720: @27324 GIM_Try, /*On fail goto*//*Label 721*/ 27358, // Rule ID 5186 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5186, GIR_Done, // Label 721: @27358 GIM_Try, /*On fail goto*//*Label 722*/ 27392, // Rule ID 5187 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5187, GIR_Done, // Label 722: @27392 GIM_Try, /*On fail goto*//*Label 723*/ 27426, // Rule ID 5188 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5188, GIR_Done, // Label 723: @27426 GIM_Try, /*On fail goto*//*Label 724*/ 27460, // Rule ID 5189 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5189, GIR_Done, // Label 724: @27460 GIM_Try, /*On fail goto*//*Label 725*/ 27494, // Rule ID 5190 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5190, GIR_Done, // Label 725: @27494 GIM_Try, /*On fail goto*//*Label 726*/ 27528, // Rule ID 5191 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5191, GIR_Done, // Label 726: @27528 GIM_Try, /*On fail goto*//*Label 727*/ 27562, // Rule ID 5204 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5204, GIR_Done, // Label 727: @27562 GIM_Try, /*On fail goto*//*Label 728*/ 27596, // Rule ID 5205 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5205, GIR_Done, // Label 728: @27596 GIM_Try, /*On fail goto*//*Label 729*/ 27630, // Rule ID 5206 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5206, GIR_Done, // Label 729: @27630 GIM_Try, /*On fail goto*//*Label 730*/ 27664, // Rule ID 5207 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5207, GIR_Done, // Label 730: @27664 GIM_Try, /*On fail goto*//*Label 731*/ 27698, // Rule ID 5208 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5208, GIR_Done, // Label 731: @27698 GIM_Try, /*On fail goto*//*Label 732*/ 27732, // Rule ID 5209 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5209, GIR_Done, // Label 732: @27732 GIM_Reject, // Label 523: @27733 GIM_Try, /*On fail goto*//*Label 733*/ 27758, // Rule ID 3775 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3775, GIR_Done, // Label 733: @27758 GIM_Try, /*On fail goto*//*Label 734*/ 27806, // Rule ID 3786 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3786, GIR_Done, // Label 734: @27806 GIM_Try, /*On fail goto*//*Label 735*/ 27840, // Rule ID 3858 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3858, GIR_Done, // Label 735: @27840 GIM_Try, /*On fail goto*//*Label 736*/ 27874, // Rule ID 3859 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3859, GIR_Done, // Label 736: @27874 GIM_Try, /*On fail goto*//*Label 737*/ 27908, // Rule ID 3860 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3860, GIR_Done, // Label 737: @27908 GIM_Try, /*On fail goto*//*Label 738*/ 27942, // Rule ID 3861 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3861, GIR_Done, // Label 738: @27942 GIM_Try, /*On fail goto*//*Label 739*/ 27976, // Rule ID 3862 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3862, GIR_Done, // Label 739: @27976 GIM_Try, /*On fail goto*//*Label 740*/ 28010, // Rule ID 3863 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3863, GIR_Done, // Label 740: @28010 GIM_Try, /*On fail goto*//*Label 741*/ 28044, // Rule ID 3864 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, // GIR_Coverage, 3864, GIR_Done, // Label 741: @28044 GIM_Try, /*On fail goto*//*Label 742*/ 28067, // Rule ID 3865 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3865, GIR_Done, // Label 742: @28067 GIM_Try, /*On fail goto*//*Label 743*/ 28090, // Rule ID 3866 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3866, GIR_Done, // Label 743: @28090 GIM_Try, /*On fail goto*//*Label 744*/ 28113, // Rule ID 3867 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3867, GIR_Done, // Label 744: @28113 GIM_Try, /*On fail goto*//*Label 745*/ 28136, // Rule ID 3868 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3868, GIR_Done, // Label 745: @28136 GIM_Try, /*On fail goto*//*Label 746*/ 28159, // Rule ID 3869 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3869, GIR_Done, // Label 746: @28159 GIM_Try, /*On fail goto*//*Label 747*/ 28182, // Rule ID 3870 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3870, GIR_Done, // Label 747: @28182 GIM_Try, /*On fail goto*//*Label 748*/ 28205, // Rule ID 3871 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3871, GIR_Done, // Label 748: @28205 GIM_Reject, // Label 524: @28206 GIM_Try, /*On fail goto*//*Label 749*/ 28240, // Rule ID 3975 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3975, GIR_Done, // Label 749: @28240 GIM_Try, /*On fail goto*//*Label 750*/ 28274, // Rule ID 3976 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3976, GIR_Done, // Label 750: @28274 GIM_Try, /*On fail goto*//*Label 751*/ 28308, // Rule ID 3977 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3977, GIR_Done, // Label 751: @28308 GIM_Try, /*On fail goto*//*Label 752*/ 28342, // Rule ID 3978 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3978, GIR_Done, // Label 752: @28342 GIM_Try, /*On fail goto*//*Label 753*/ 28376, // Rule ID 3979 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3979, GIR_Done, // Label 753: @28376 GIM_Try, /*On fail goto*//*Label 754*/ 28410, // Rule ID 3980 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3980, GIR_Done, // Label 754: @28410 GIM_Try, /*On fail goto*//*Label 755*/ 28481, // Rule ID 3981 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3981, GIR_Done, // Label 755: @28481 GIM_Try, /*On fail goto*//*Label 756*/ 28504, // Rule ID 3982 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3982, GIR_Done, // Label 756: @28504 GIM_Try, /*On fail goto*//*Label 757*/ 28527, // Rule ID 3983 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3983, GIR_Done, // Label 757: @28527 GIM_Try, /*On fail goto*//*Label 758*/ 28550, // Rule ID 3984 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3984, GIR_Done, // Label 758: @28550 GIM_Try, /*On fail goto*//*Label 759*/ 28573, // Rule ID 3985 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3985, GIR_Done, // Label 759: @28573 GIM_Try, /*On fail goto*//*Label 760*/ 28596, // Rule ID 3986 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3986, GIR_Done, // Label 760: @28596 GIM_Try, /*On fail goto*//*Label 761*/ 28628, // Rule ID 3987 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3987, GIR_Done, // Label 761: @28628 GIM_Try, /*On fail goto*//*Label 762*/ 28662, // Rule ID 3988 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3988, GIR_Done, // Label 762: @28662 GIM_Try, /*On fail goto*//*Label 763*/ 28696, // Rule ID 3989 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3989, GIR_Done, // Label 763: @28696 GIM_Try, /*On fail goto*//*Label 764*/ 28730, // Rule ID 3990 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3990, GIR_Done, // Label 764: @28730 GIM_Try, /*On fail goto*//*Label 765*/ 28764, // Rule ID 3991 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3991, GIR_Done, // Label 765: @28764 GIM_Try, /*On fail goto*//*Label 766*/ 28798, // Rule ID 3992 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3992, GIR_Done, // Label 766: @28798 GIM_Try, /*On fail goto*//*Label 767*/ 28832, // Rule ID 3993 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 3993, GIR_Done, // Label 767: @28832 GIM_Try, /*On fail goto*//*Label 768*/ 28903, // Rule ID 3994 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3994, GIR_Done, // Label 768: @28903 GIM_Try, /*On fail goto*//*Label 769*/ 28926, // Rule ID 3995 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3995, GIR_Done, // Label 769: @28926 GIM_Try, /*On fail goto*//*Label 770*/ 28949, // Rule ID 3996 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3996, GIR_Done, // Label 770: @28949 GIM_Try, /*On fail goto*//*Label 771*/ 28972, // Rule ID 3997 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3997, GIR_Done, // Label 771: @28972 GIM_Try, /*On fail goto*//*Label 772*/ 28995, // Rule ID 3998 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3998, GIR_Done, // Label 772: @28995 GIM_Try, /*On fail goto*//*Label 773*/ 29018, // Rule ID 3999 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3999, GIR_Done, // Label 773: @29018 GIM_Try, /*On fail goto*//*Label 774*/ 29050, // Rule ID 4000 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4000, GIR_Done, // Label 774: @29050 GIM_Try, /*On fail goto*//*Label 775*/ 29084, // Rule ID 5180 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5180, GIR_Done, // Label 775: @29084 GIM_Try, /*On fail goto*//*Label 776*/ 29118, // Rule ID 5181 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5181, GIR_Done, // Label 776: @29118 GIM_Try, /*On fail goto*//*Label 777*/ 29152, // Rule ID 5182 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5182, GIR_Done, // Label 777: @29152 GIM_Try, /*On fail goto*//*Label 778*/ 29186, // Rule ID 5183 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5183, GIR_Done, // Label 778: @29186 GIM_Try, /*On fail goto*//*Label 779*/ 29220, // Rule ID 5184 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5184, GIR_Done, // Label 779: @29220 GIM_Try, /*On fail goto*//*Label 780*/ 29254, // Rule ID 5185 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5185, GIR_Done, // Label 780: @29254 GIM_Try, /*On fail goto*//*Label 781*/ 29288, // Rule ID 5198 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5198, GIR_Done, // Label 781: @29288 GIM_Try, /*On fail goto*//*Label 782*/ 29322, // Rule ID 5199 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5199, GIR_Done, // Label 782: @29322 GIM_Try, /*On fail goto*//*Label 783*/ 29356, // Rule ID 5200 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5200, GIR_Done, // Label 783: @29356 GIM_Try, /*On fail goto*//*Label 784*/ 29390, // Rule ID 5201 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5201, GIR_Done, // Label 784: @29390 GIM_Try, /*On fail goto*//*Label 785*/ 29424, // Rule ID 5202 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5202, GIR_Done, // Label 785: @29424 GIM_Try, /*On fail goto*//*Label 786*/ 29458, // Rule ID 5203 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5203, GIR_Done, // Label 786: @29458 GIM_Reject, // Label 525: @29459 GIM_Try, /*On fail goto*//*Label 787*/ 29493, // Rule ID 4001 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4001, GIR_Done, // Label 787: @29493 GIM_Try, /*On fail goto*//*Label 788*/ 29527, // Rule ID 4002 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4002, GIR_Done, // Label 788: @29527 GIM_Try, /*On fail goto*//*Label 789*/ 29561, // Rule ID 4003 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4003, GIR_Done, // Label 789: @29561 GIM_Try, /*On fail goto*//*Label 790*/ 29595, // Rule ID 4004 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4004, GIR_Done, // Label 790: @29595 GIM_Try, /*On fail goto*//*Label 791*/ 29629, // Rule ID 4005 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4005, GIR_Done, // Label 791: @29629 GIM_Try, /*On fail goto*//*Label 792*/ 29663, // Rule ID 4006 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4006, GIR_Done, // Label 792: @29663 GIM_Try, /*On fail goto*//*Label 793*/ 29697, // Rule ID 4007 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR128*/38, // GIR_Coverage, 4007, GIR_Done, // Label 793: @29697 GIM_Try, /*On fail goto*//*Label 794*/ 29768, // Rule ID 4008 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/8, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4008, GIR_Done, // Label 794: @29768 GIM_Try, /*On fail goto*//*Label 795*/ 29791, // Rule ID 4009 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4009, GIR_Done, // Label 795: @29791 GIM_Try, /*On fail goto*//*Label 796*/ 29814, // Rule ID 4010 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4010, GIR_Done, // Label 796: @29814 GIM_Try, /*On fail goto*//*Label 797*/ 29837, // Rule ID 4011 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4011, GIR_Done, // Label 797: @29837 GIM_Try, /*On fail goto*//*Label 798*/ 29860, // Rule ID 4012 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4012, GIR_Done, // Label 798: @29860 GIM_Try, /*On fail goto*//*Label 799*/ 29883, // Rule ID 4013 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4013, GIR_Done, // Label 799: @29883 GIM_Try, /*On fail goto*//*Label 800*/ 29906, // Rule ID 4014 // GIM_CheckFeatures, GIFBS_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4014, GIR_Done, // Label 800: @29906 GIM_Try, /*On fail goto*//*Label 801*/ 29940, // Rule ID 5174 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5174, GIR_Done, // Label 801: @29940 GIM_Try, /*On fail goto*//*Label 802*/ 29974, // Rule ID 5175 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5175, GIR_Done, // Label 802: @29974 GIM_Try, /*On fail goto*//*Label 803*/ 30008, // Rule ID 5176 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5176, GIR_Done, // Label 803: @30008 GIM_Try, /*On fail goto*//*Label 804*/ 30042, // Rule ID 5177 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5177, GIR_Done, // Label 804: @30042 GIM_Try, /*On fail goto*//*Label 805*/ 30076, // Rule ID 5178 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5178, GIR_Done, // Label 805: @30076 GIM_Try, /*On fail goto*//*Label 806*/ 30110, // Rule ID 5179 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::ZPRRegClassID, // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39, // GIR_Coverage, 5179, GIR_Done, // Label 806: @30110 GIM_Reject, // Label 526: @30111 GIM_Reject, // Label 10: @30112 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 815*/ 30323, /*GILLT_s16*//*Label 807*/ 30131, /*GILLT_s32*//*Label 808*/ 30155, /*GILLT_s64*//*Label 809*/ 30179, 0, 0, /*GILLT_v2s32*//*Label 810*/ 30203, /*GILLT_v2s64*//*Label 811*/ 30227, 0, /*GILLT_v4s16*//*Label 812*/ 30251, /*GILLT_v4s32*//*Label 813*/ 30275, 0, 0, /*GILLT_v8s16*//*Label 814*/ 30299, // Label 807: @30131 GIM_Try, /*On fail goto*//*Label 816*/ 30154, // Rule ID 490 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 490, GIR_Done, // Label 816: @30154 GIM_Reject, // Label 808: @30155 GIM_Try, /*On fail goto*//*Label 817*/ 30178, // Rule ID 491 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 491, GIR_Done, // Label 817: @30178 GIM_Reject, // Label 809: @30179 GIM_Try, /*On fail goto*//*Label 818*/ 30202, // Rule ID 492 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 492, GIR_Done, // Label 818: @30202 GIM_Reject, // Label 810: @30203 GIM_Try, /*On fail goto*//*Label 819*/ 30226, // Rule ID 751 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 751, GIR_Done, // Label 819: @30226 GIM_Reject, // Label 811: @30227 GIM_Try, /*On fail goto*//*Label 820*/ 30250, // Rule ID 753 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 753, GIR_Done, // Label 820: @30250 GIM_Reject, // Label 812: @30251 GIM_Try, /*On fail goto*//*Label 821*/ 30274, // Rule ID 749 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 749, GIR_Done, // Label 821: @30274 GIM_Reject, // Label 813: @30275 GIM_Try, /*On fail goto*//*Label 822*/ 30298, // Rule ID 752 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 752, GIR_Done, // Label 822: @30298 GIM_Reject, // Label 814: @30299 GIM_Try, /*On fail goto*//*Label 823*/ 30322, // Rule ID 750 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 750, GIR_Done, // Label 823: @30322 GIM_Reject, // Label 815: @30323 GIM_Reject, // Label 11: @30324 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 832*/ 30535, /*GILLT_s16*//*Label 824*/ 30343, /*GILLT_s32*//*Label 825*/ 30367, /*GILLT_s64*//*Label 826*/ 30391, 0, 0, /*GILLT_v2s32*//*Label 827*/ 30415, /*GILLT_v2s64*//*Label 828*/ 30439, 0, /*GILLT_v4s16*//*Label 829*/ 30463, /*GILLT_v4s32*//*Label 830*/ 30487, 0, 0, /*GILLT_v8s16*//*Label 831*/ 30511, // Label 824: @30343 GIM_Try, /*On fail goto*//*Label 833*/ 30366, // Rule ID 472 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 472, GIR_Done, // Label 833: @30366 GIM_Reject, // Label 825: @30367 GIM_Try, /*On fail goto*//*Label 834*/ 30390, // Rule ID 473 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTASr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 473, GIR_Done, // Label 834: @30390 GIM_Reject, // Label 826: @30391 GIM_Try, /*On fail goto*//*Label 835*/ 30414, // Rule ID 474 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTADr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 474, GIR_Done, // Label 835: @30414 GIM_Reject, // Label 827: @30415 GIM_Try, /*On fail goto*//*Label 836*/ 30438, // Rule ID 721 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 721, GIR_Done, // Label 836: @30438 GIM_Reject, // Label 828: @30439 GIM_Try, /*On fail goto*//*Label 837*/ 30462, // Rule ID 723 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 723, GIR_Done, // Label 837: @30462 GIM_Reject, // Label 829: @30463 GIM_Try, /*On fail goto*//*Label 838*/ 30486, // Rule ID 719 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 719, GIR_Done, // Label 838: @30486 GIM_Reject, // Label 830: @30487 GIM_Try, /*On fail goto*//*Label 839*/ 30510, // Rule ID 722 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 722, GIR_Done, // Label 839: @30510 GIM_Reject, // Label 831: @30511 GIM_Try, /*On fail goto*//*Label 840*/ 30534, // Rule ID 720 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 720, GIR_Done, // Label 840: @30534 GIM_Reject, // Label 832: @30535 GIM_Reject, // Label 12: @30536 GIM_Try, /*On fail goto*//*Label 841*/ 30563, // Rule ID 2326 // GIM_CheckFeatures, GIFBS_HasPerfMon, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (readcyclecounter:{ *:[i64] }) => (MRS:{ *:[i64] } 56552:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/56552, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2326, GIR_Done, // Label 841: @30563 GIM_Reject, // Label 13: @30564 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 15, /*)*//*default:*//*Label 853*/ 36848, /*GILLT_s16*//*Label 842*/ 30585, /*GILLT_s32*//*Label 843*/ 30736, /*GILLT_s64*//*Label 844*/ 32450, /*GILLT_s128*//*Label 845*/ 34762, 0, /*GILLT_v2s32*//*Label 846*/ 34944, /*GILLT_v2s64*//*Label 847*/ 35256, 0, /*GILLT_v4s16*//*Label 848*/ 35568, /*GILLT_v4s32*//*Label 849*/ 35880, 0, /*GILLT_v8s8*//*Label 850*/ 36192, /*GILLT_v8s16*//*Label 851*/ 36364, 0, /*GILLT_v16s8*//*Label 852*/ 36676, // Label 842: @30585 GIM_Try, /*On fail goto*//*Label 854*/ 30735, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 855*/ 30637, // Rule ID 203 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 203, GIR_Done, // Label 855: @30637 GIM_Try, /*On fail goto*//*Label 856*/ 30672, // Rule ID 204 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 204, GIR_Done, // Label 856: @30672 GIM_Try, /*On fail goto*//*Label 857*/ 30703, // Rule ID 226 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 226, GIR_Done, // Label 857: @30703 GIM_Try, /*On fail goto*//*Label 858*/ 30734, // Rule ID 247 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 247, GIR_Done, // Label 858: @30734 GIM_Reject, // Label 854: @30735 GIM_Reject, // Label 843: @30736 GIM_Try, /*On fail goto*//*Label 859*/ 30786, // Rule ID 197 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 197, GIR_Done, // Label 859: @30786 GIM_Try, /*On fail goto*//*Label 860*/ 30836, // Rule ID 198 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 198, GIR_Done, // Label 860: @30836 GIM_Try, /*On fail goto*//*Label 861*/ 30886, // Rule ID 205 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 205, GIR_Done, // Label 861: @30886 GIM_Try, /*On fail goto*//*Label 862*/ 30936, // Rule ID 206 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 206, GIR_Done, // Label 862: @30936 GIM_Try, /*On fail goto*//*Label 863*/ 30990, // Rule ID 2525 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2525, GIR_Done, // Label 863: @30990 GIM_Try, /*On fail goto*//*Label 864*/ 31044, // Rule ID 2526 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2526, GIR_Done, // Label 864: @31044 GIM_Try, /*On fail goto*//*Label 865*/ 31098, // Rule ID 2527 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2527, GIR_Done, // Label 865: @31098 GIM_Try, /*On fail goto*//*Label 866*/ 31152, // Rule ID 2528 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2528, GIR_Done, // Label 866: @31152 GIM_Try, /*On fail goto*//*Label 867*/ 31206, // Rule ID 2529 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2529, GIR_Done, // Label 867: @31206 GIM_Try, /*On fail goto*//*Label 868*/ 31260, // Rule ID 2530 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2530, GIR_Done, // Label 868: @31260 GIM_Try, /*On fail goto*//*Label 869*/ 31306, // Rule ID 224 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 224, GIR_Done, // Label 869: @31306 GIM_Try, /*On fail goto*//*Label 870*/ 31352, // Rule ID 227 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 227, GIR_Done, // Label 870: @31352 GIM_Try, /*On fail goto*//*Label 871*/ 31405, // Rule ID 4074 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4074, GIR_Done, // Label 871: @31405 GIM_Try, /*On fail goto*//*Label 872*/ 31458, // Rule ID 4075 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4075, GIR_Done, // Label 872: @31458 GIM_Try, /*On fail goto*//*Label 873*/ 31511, // Rule ID 4079 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4079, GIR_Done, // Label 873: @31511 GIM_Try, /*On fail goto*//*Label 874*/ 31564, // Rule ID 4080 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4080, GIR_Done, // Label 874: @31564 GIM_Try, /*On fail goto*//*Label 875*/ 31617, // Rule ID 4084 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4084, GIR_Done, // Label 875: @31617 GIM_Try, /*On fail goto*//*Label 876*/ 31670, // Rule ID 4085 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4085, GIR_Done, // Label 876: @31670 GIM_Try, /*On fail goto*//*Label 877*/ 31716, // Rule ID 245 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 245, GIR_Done, // Label 877: @31716 GIM_Try, /*On fail goto*//*Label 878*/ 31762, // Rule ID 248 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 248, GIR_Done, // Label 878: @31762 GIM_Try, /*On fail goto*//*Label 879*/ 31811, // Rule ID 4076 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4076, GIR_Done, // Label 879: @31811 GIM_Try, /*On fail goto*//*Label 880*/ 31860, // Rule ID 4077 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4077, GIR_Done, // Label 880: @31860 GIM_Try, /*On fail goto*//*Label 881*/ 31909, // Rule ID 4081 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4081, GIR_Done, // Label 881: @31909 GIM_Try, /*On fail goto*//*Label 882*/ 31958, // Rule ID 4082 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4082, GIR_Done, // Label 882: @31958 GIM_Try, /*On fail goto*//*Label 883*/ 32007, // Rule ID 4086 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4086, GIR_Done, // Label 883: @32007 GIM_Try, /*On fail goto*//*Label 884*/ 32056, // Rule ID 4087 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4087, GIR_Done, // Label 884: @32056 GIM_Try, /*On fail goto*//*Label 885*/ 32106, // Rule ID 2560 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2560, GIR_Done, // Label 885: @32106 GIM_Try, /*On fail goto*//*Label 886*/ 32156, // Rule ID 2561 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2561, GIR_Done, // Label 886: @32156 GIM_Try, /*On fail goto*//*Label 887*/ 32206, // Rule ID 2562 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2562, GIR_Done, // Label 887: @32206 GIM_Try, /*On fail goto*//*Label 888*/ 32256, // Rule ID 2583 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2583, GIR_Done, // Label 888: @32256 GIM_Try, /*On fail goto*//*Label 889*/ 32306, // Rule ID 2584 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2584, GIR_Done, // Label 889: @32306 GIM_Try, /*On fail goto*//*Label 890*/ 32356, // Rule ID 2585 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2585, GIR_Done, // Label 890: @32356 GIM_Try, /*On fail goto*//*Label 891*/ 32387, // Rule ID 4073 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4073, GIR_Done, // Label 891: @32387 GIM_Try, /*On fail goto*//*Label 892*/ 32418, // Rule ID 4078 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4078, GIR_Done, // Label 892: @32418 GIM_Try, /*On fail goto*//*Label 893*/ 32449, // Rule ID 4083 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARW, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4083, GIR_Done, // Label 893: @32449 GIM_Reject, // Label 844: @32450 GIM_Try, /*On fail goto*//*Label 894*/ 32500, // Rule ID 199 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 199, GIR_Done, // Label 894: @32500 GIM_Try, /*On fail goto*//*Label 895*/ 32550, // Rule ID 200 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 200, GIR_Done, // Label 895: @32550 GIM_Try, /*On fail goto*//*Label 896*/ 32600, // Rule ID 207 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 207, GIR_Done, // Label 896: @32600 GIM_Try, /*On fail goto*//*Label 897*/ 32650, // Rule ID 208 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 208, GIR_Done, // Label 897: @32650 GIM_Try, /*On fail goto*//*Label 898*/ 32700, // Rule ID 2491 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2491, GIR_Done, // Label 898: @32700 GIM_Try, /*On fail goto*//*Label 899*/ 32750, // Rule ID 2492 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2492, GIR_Done, // Label 899: @32750 GIM_Try, /*On fail goto*//*Label 900*/ 32800, // Rule ID 2493 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2493, GIR_Done, // Label 900: @32800 GIM_Try, /*On fail goto*//*Label 901*/ 32850, // Rule ID 2494 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2494, GIR_Done, // Label 901: @32850 GIM_Try, /*On fail goto*//*Label 902*/ 32932, // Rule ID 2517 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2517, GIR_Done, // Label 902: @32932 GIM_Try, /*On fail goto*//*Label 903*/ 33014, // Rule ID 2518 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2518, GIR_Done, // Label 903: @33014 GIM_Try, /*On fail goto*//*Label 904*/ 33096, // Rule ID 2519 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2519, GIR_Done, // Label 904: @33096 GIM_Try, /*On fail goto*//*Label 905*/ 33178, // Rule ID 2520 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2520, GIR_Done, // Label 905: @33178 GIM_Try, /*On fail goto*//*Label 906*/ 33260, // Rule ID 2521 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2521, GIR_Done, // Label 906: @33260 GIM_Try, /*On fail goto*//*Label 907*/ 33342, // Rule ID 2522 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2522, GIR_Done, // Label 907: @33342 GIM_Try, /*On fail goto*//*Label 908*/ 33424, // Rule ID 2523 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2523, GIR_Done, // Label 908: @33424 GIM_Try, /*On fail goto*//*Label 909*/ 33506, // Rule ID 2524 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2524, GIR_Done, // Label 909: @33506 GIM_Try, /*On fail goto*//*Label 910*/ 33552, // Rule ID 223 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 223, GIR_Done, // Label 910: @33552 GIM_Try, /*On fail goto*//*Label 911*/ 33598, // Rule ID 228 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 228, GIR_Done, // Label 911: @33598 GIM_Try, /*On fail goto*//*Label 912*/ 33651, // Rule ID 4089 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4089, GIR_Done, // Label 912: @33651 GIM_Try, /*On fail goto*//*Label 913*/ 33704, // Rule ID 4090 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4090, GIR_Done, // Label 913: @33704 GIM_Try, /*On fail goto*//*Label 914*/ 33750, // Rule ID 244 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 244, GIR_Done, // Label 914: @33750 GIM_Try, /*On fail goto*//*Label 915*/ 33796, // Rule ID 249 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 249, GIR_Done, // Label 915: @33796 GIM_Try, /*On fail goto*//*Label 916*/ 33845, // Rule ID 4091 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4091, GIR_Done, // Label 916: @33845 GIM_Try, /*On fail goto*//*Label 917*/ 33894, // Rule ID 4092 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4092, GIR_Done, // Label 917: @33894 GIM_Try, /*On fail goto*//*Label 918*/ 33940, // Rule ID 2546 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2546, GIR_Done, // Label 918: @33940 GIM_Try, /*On fail goto*//*Label 919*/ 33986, // Rule ID 2547 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2547, GIR_Done, // Label 919: @33986 GIM_Try, /*On fail goto*//*Label 920*/ 34032, // Rule ID 2574 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2574, GIR_Done, // Label 920: @34032 GIM_Try, /*On fail goto*//*Label 921*/ 34078, // Rule ID 2575 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2575, GIR_Done, // Label 921: @34078 GIM_Try, /*On fail goto*//*Label 922*/ 34156, // Rule ID 2563 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2563, GIR_Done, // Label 922: @34156 GIM_Try, /*On fail goto*//*Label 923*/ 34234, // Rule ID 2564 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2564, GIR_Done, // Label 923: @34234 GIM_Try, /*On fail goto*//*Label 924*/ 34312, // Rule ID 2565 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2565, GIR_Done, // Label 924: @34312 GIM_Try, /*On fail goto*//*Label 925*/ 34390, // Rule ID 2566 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2566, GIR_Done, // Label 925: @34390 GIM_Try, /*On fail goto*//*Label 926*/ 34468, // Rule ID 2586 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2586, GIR_Done, // Label 926: @34468 GIM_Try, /*On fail goto*//*Label 927*/ 34546, // Rule ID 2587 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2587, GIR_Done, // Label 927: @34546 GIM_Try, /*On fail goto*//*Label 928*/ 34624, // Rule ID 2588 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2588, GIR_Done, // Label 928: @34624 GIM_Try, /*On fail goto*//*Label 929*/ 34702, // Rule ID 2589 // GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2589, GIR_Done, // Label 929: @34702 GIM_Try, /*On fail goto*//*Label 930*/ 34733, // Rule ID 4088 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<><> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARX, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4088, GIR_Done, // Label 930: @34733 GIM_Try, /*On fail goto*//*Label 931*/ 34761, // Rule ID 3596 // GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev1d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3596, GIR_Done, // Label 931: @34761 GIM_Reject, // Label 845: @34762 GIM_Try, /*On fail goto*//*Label 932*/ 34943, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 933*/ 34814, // Rule ID 209 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 209, GIR_Done, // Label 933: @34814 GIM_Try, /*On fail goto*//*Label 934*/ 34849, // Rule ID 210 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 210, GIR_Done, // Label 934: @34849 GIM_Try, /*On fail goto*//*Label 935*/ 34880, // Rule ID 229 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 229, GIR_Done, // Label 935: @34880 GIM_Try, /*On fail goto*//*Label 936*/ 34911, // Rule ID 250 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 250, GIR_Done, // Label 936: @34911 GIM_Try, /*On fail goto*//*Label 937*/ 34942, // Rule ID 2555 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2555, GIR_Done, // Label 937: @34942 GIM_Reject, // Label 932: @34943 GIM_Reject, // Label 846: @34944 GIM_Try, /*On fail goto*//*Label 938*/ 35255, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 939*/ 34998, // Rule ID 2481 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2481, GIR_Done, // Label 939: @34998 GIM_Try, /*On fail goto*//*Label 940*/ 35035, // Rule ID 2482 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2482, GIR_Done, // Label 940: @35035 GIM_Try, /*On fail goto*//*Label 941*/ 35072, // Rule ID 2483 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2483, GIR_Done, // Label 941: @35072 GIM_Try, /*On fail goto*//*Label 942*/ 35109, // Rule ID 2484 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2484, GIR_Done, // Label 942: @35109 GIM_Try, /*On fail goto*//*Label 943*/ 35142, // Rule ID 2541 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2541, GIR_Done, // Label 943: @35142 GIM_Try, /*On fail goto*//*Label 944*/ 35175, // Rule ID 2544 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2544, GIR_Done, // Label 944: @35175 GIM_Try, /*On fail goto*//*Label 945*/ 35208, // Rule ID 2569 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2569, GIR_Done, // Label 945: @35208 GIM_Try, /*On fail goto*//*Label 946*/ 35241, // Rule ID 2570 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2570, GIR_Done, // Label 946: @35241 GIM_Try, /*On fail goto*//*Label 947*/ 35254, // Rule ID 3595 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3595, GIR_Done, // Label 947: @35254 GIM_Reject, // Label 938: @35255 GIM_Reject, // Label 847: @35256 GIM_Try, /*On fail goto*//*Label 948*/ 35567, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 949*/ 35310, // Rule ID 2495 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2495, GIR_Done, // Label 949: @35310 GIM_Try, /*On fail goto*//*Label 950*/ 35347, // Rule ID 2496 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2496, GIR_Done, // Label 950: @35347 GIM_Try, /*On fail goto*//*Label 951*/ 35384, // Rule ID 2497 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2497, GIR_Done, // Label 951: @35384 GIM_Try, /*On fail goto*//*Label 952*/ 35421, // Rule ID 2498 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2498, GIR_Done, // Label 952: @35421 GIM_Try, /*On fail goto*//*Label 953*/ 35454, // Rule ID 2549 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2549, GIR_Done, // Label 953: @35454 GIM_Try, /*On fail goto*//*Label 954*/ 35487, // Rule ID 2553 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2553, GIR_Done, // Label 954: @35487 GIM_Try, /*On fail goto*//*Label 955*/ 35520, // Rule ID 2576 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2576, GIR_Done, // Label 955: @35520 GIM_Try, /*On fail goto*//*Label 956*/ 35553, // Rule ID 2577 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2577, GIR_Done, // Label 956: @35553 GIM_Try, /*On fail goto*//*Label 957*/ 35566, // Rule ID 3592 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3592, GIR_Done, // Label 957: @35566 GIM_Reject, // Label 948: @35567 GIM_Reject, // Label 848: @35568 GIM_Try, /*On fail goto*//*Label 958*/ 35879, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 959*/ 35622, // Rule ID 2487 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2487, GIR_Done, // Label 959: @35622 GIM_Try, /*On fail goto*//*Label 960*/ 35659, // Rule ID 2488 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2488, GIR_Done, // Label 960: @35659 GIM_Try, /*On fail goto*//*Label 961*/ 35696, // Rule ID 2489 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2489, GIR_Done, // Label 961: @35696 GIM_Try, /*On fail goto*//*Label 962*/ 35733, // Rule ID 2490 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2490, GIR_Done, // Label 962: @35733 GIM_Try, /*On fail goto*//*Label 963*/ 35766, // Rule ID 2543 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2543, GIR_Done, // Label 963: @35766 GIM_Try, /*On fail goto*//*Label 964*/ 35799, // Rule ID 2545 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2545, GIR_Done, // Label 964: @35799 GIM_Try, /*On fail goto*//*Label 965*/ 35832, // Rule ID 2571 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2571, GIR_Done, // Label 965: @35832 GIM_Try, /*On fail goto*//*Label 966*/ 35865, // Rule ID 2573 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2573, GIR_Done, // Label 966: @35865 GIM_Try, /*On fail goto*//*Label 967*/ 35878, // Rule ID 3594 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3594, GIR_Done, // Label 967: @35878 GIM_Reject, // Label 958: @35879 GIM_Reject, // Label 849: @35880 GIM_Try, /*On fail goto*//*Label 968*/ 36191, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 969*/ 35934, // Rule ID 2499 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2499, GIR_Done, // Label 969: @35934 GIM_Try, /*On fail goto*//*Label 970*/ 35971, // Rule ID 2500 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2500, GIR_Done, // Label 970: @35971 GIM_Try, /*On fail goto*//*Label 971*/ 36008, // Rule ID 2501 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2501, GIR_Done, // Label 971: @36008 GIM_Try, /*On fail goto*//*Label 972*/ 36045, // Rule ID 2502 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2502, GIR_Done, // Label 972: @36045 GIM_Try, /*On fail goto*//*Label 973*/ 36078, // Rule ID 2548 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2548, GIR_Done, // Label 973: @36078 GIM_Try, /*On fail goto*//*Label 974*/ 36111, // Rule ID 2552 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2552, GIR_Done, // Label 974: @36111 GIM_Try, /*On fail goto*//*Label 975*/ 36144, // Rule ID 2578 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2578, GIR_Done, // Label 975: @36144 GIM_Try, /*On fail goto*//*Label 976*/ 36177, // Rule ID 2579 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2579, GIR_Done, // Label 976: @36177 GIM_Try, /*On fail goto*//*Label 977*/ 36190, // Rule ID 3591 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3591, GIR_Done, // Label 977: @36190 GIM_Reject, // Label 968: @36191 GIM_Reject, // Label 850: @36192 GIM_Try, /*On fail goto*//*Label 978*/ 36363, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 979*/ 36246, // Rule ID 2485 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2485, GIR_Done, // Label 979: @36246 GIM_Try, /*On fail goto*//*Label 980*/ 36283, // Rule ID 2486 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2486, GIR_Done, // Label 980: @36283 GIM_Try, /*On fail goto*//*Label 981*/ 36316, // Rule ID 2542 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2542, GIR_Done, // Label 981: @36316 GIM_Try, /*On fail goto*//*Label 982*/ 36349, // Rule ID 2572 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2572, GIR_Done, // Label 982: @36349 GIM_Try, /*On fail goto*//*Label 983*/ 36362, // Rule ID 3593 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3593, GIR_Done, // Label 983: @36362 GIM_Reject, // Label 978: @36363 GIM_Reject, // Label 851: @36364 GIM_Try, /*On fail goto*//*Label 984*/ 36675, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 985*/ 36418, // Rule ID 2503 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2503, GIR_Done, // Label 985: @36418 GIM_Try, /*On fail goto*//*Label 986*/ 36455, // Rule ID 2504 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2504, GIR_Done, // Label 986: @36455 GIM_Try, /*On fail goto*//*Label 987*/ 36492, // Rule ID 2505 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2505, GIR_Done, // Label 987: @36492 GIM_Try, /*On fail goto*//*Label 988*/ 36529, // Rule ID 2506 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2506, GIR_Done, // Label 988: @36529 GIM_Try, /*On fail goto*//*Label 989*/ 36562, // Rule ID 2551 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2551, GIR_Done, // Label 989: @36562 GIM_Try, /*On fail goto*//*Label 990*/ 36595, // Rule ID 2554 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2554, GIR_Done, // Label 990: @36595 GIM_Try, /*On fail goto*//*Label 991*/ 36628, // Rule ID 2580 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2580, GIR_Done, // Label 991: @36628 GIM_Try, /*On fail goto*//*Label 992*/ 36661, // Rule ID 2582 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2582, GIR_Done, // Label 992: @36661 GIM_Try, /*On fail goto*//*Label 993*/ 36674, // Rule ID 3590 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3590, GIR_Done, // Label 993: @36674 GIM_Reject, // Label 984: @36675 GIM_Reject, // Label 852: @36676 GIM_Try, /*On fail goto*//*Label 994*/ 36847, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 995*/ 36730, // Rule ID 2507 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2507, GIR_Done, // Label 995: @36730 GIM_Try, /*On fail goto*//*Label 996*/ 36767, // Rule ID 2508 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2508, GIR_Done, // Label 996: @36767 GIM_Try, /*On fail goto*//*Label 997*/ 36800, // Rule ID 2550 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2550, GIR_Done, // Label 997: @36800 GIM_Try, /*On fail goto*//*Label 998*/ 36833, // Rule ID 2581 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2581, GIR_Done, // Label 998: @36833 GIM_Try, /*On fail goto*//*Label 999*/ 36846, // Rule ID 3589 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<><> => (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev16b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3589, GIR_Done, // Label 999: @36846 GIM_Reject, // Label 994: @36847 GIM_Reject, // Label 853: @36848 GIM_Reject, // Label 14: @36849 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1002*/ 37819, /*GILLT_s32*//*Label 1000*/ 36857, /*GILLT_s64*//*Label 1001*/ 37242, // Label 1000: @36857 GIM_Try, /*On fail goto*//*Label 1003*/ 36907, // Rule ID 211 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 211, GIR_Done, // Label 1003: @36907 GIM_Try, /*On fail goto*//*Label 1004*/ 36957, // Rule ID 212 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 212, GIR_Done, // Label 1004: @36957 GIM_Try, /*On fail goto*//*Label 1005*/ 37007, // Rule ID 215 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 215, GIR_Done, // Label 1005: @37007 GIM_Try, /*On fail goto*//*Label 1006*/ 37057, // Rule ID 216 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 216, GIR_Done, // Label 1006: @37057 GIM_Try, /*On fail goto*//*Label 1007*/ 37103, // Rule ID 232 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 232, GIR_Done, // Label 1007: @37103 GIM_Try, /*On fail goto*//*Label 1008*/ 37149, // Rule ID 234 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 234, GIR_Done, // Label 1008: @37149 GIM_Try, /*On fail goto*//*Label 1009*/ 37195, // Rule ID 253 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 253, GIR_Done, // Label 1009: @37195 GIM_Try, /*On fail goto*//*Label 1010*/ 37241, // Rule ID 255 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 255, GIR_Done, // Label 1010: @37241 GIM_Reject, // Label 1001: @37242 GIM_Try, /*On fail goto*//*Label 1011*/ 37292, // Rule ID 213 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 213, GIR_Done, // Label 1011: @37292 GIM_Try, /*On fail goto*//*Label 1012*/ 37342, // Rule ID 214 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 214, GIR_Done, // Label 1012: @37342 GIM_Try, /*On fail goto*//*Label 1013*/ 37392, // Rule ID 217 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 217, GIR_Done, // Label 1013: @37392 GIM_Try, /*On fail goto*//*Label 1014*/ 37442, // Rule ID 218 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 218, GIR_Done, // Label 1014: @37442 GIM_Try, /*On fail goto*//*Label 1015*/ 37492, // Rule ID 219 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 219, GIR_Done, // Label 1015: @37492 GIM_Try, /*On fail goto*//*Label 1016*/ 37542, // Rule ID 220 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 220, GIR_Done, // Label 1016: @37542 GIM_Try, /*On fail goto*//*Label 1017*/ 37588, // Rule ID 233 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 233, GIR_Done, // Label 1017: @37588 GIM_Try, /*On fail goto*//*Label 1018*/ 37634, // Rule ID 235 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 235, GIR_Done, // Label 1018: @37634 GIM_Try, /*On fail goto*//*Label 1019*/ 37680, // Rule ID 236 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 236, GIR_Done, // Label 1019: @37680 GIM_Try, /*On fail goto*//*Label 1020*/ 37726, // Rule ID 254 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 254, GIR_Done, // Label 1020: @37726 GIM_Try, /*On fail goto*//*Label 1021*/ 37772, // Rule ID 256 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 256, GIR_Done, // Label 1021: @37772 GIM_Try, /*On fail goto*//*Label 1022*/ 37818, // Rule ID 257 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 257, GIR_Done, // Label 1022: @37818 GIM_Reject, // Label 1002: @37819 GIM_Reject, // Label 15: @37820 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1025*/ 39862, /*GILLT_s32*//*Label 1023*/ 37828, /*GILLT_s64*//*Label 1024*/ 38497, // Label 1023: @37828 GIM_Try, /*On fail goto*//*Label 1026*/ 37878, // Rule ID 193 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 193, GIR_Done, // Label 1026: @37878 GIM_Try, /*On fail goto*//*Label 1027*/ 37928, // Rule ID 194 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 194, GIR_Done, // Label 1027: @37928 GIM_Try, /*On fail goto*//*Label 1028*/ 37978, // Rule ID 195 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 195, GIR_Done, // Label 1028: @37978 GIM_Try, /*On fail goto*//*Label 1029*/ 38028, // Rule ID 196 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 196, GIR_Done, // Label 1029: @38028 GIM_Try, /*On fail goto*//*Label 1030*/ 38078, // Rule ID 2531 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2531, GIR_Done, // Label 1030: @38078 GIM_Try, /*On fail goto*//*Label 1031*/ 38128, // Rule ID 2532 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2532, GIR_Done, // Label 1031: @38128 GIM_Try, /*On fail goto*//*Label 1032*/ 38174, // Rule ID 230 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 230, GIR_Done, // Label 1032: @38174 GIM_Try, /*On fail goto*//*Label 1033*/ 38220, // Rule ID 231 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 231, GIR_Done, // Label 1033: @38220 GIM_Try, /*On fail goto*//*Label 1034*/ 38266, // Rule ID 251 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 251, GIR_Done, // Label 1034: @38266 GIM_Try, /*On fail goto*//*Label 1035*/ 38312, // Rule ID 252 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 252, GIR_Done, // Label 1035: @38312 GIM_Try, /*On fail goto*//*Label 1036*/ 38358, // Rule ID 2558 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2558, GIR_Done, // Label 1036: @38358 GIM_Try, /*On fail goto*//*Label 1037*/ 38404, // Rule ID 2590 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2590, GIR_Done, // Label 1037: @38404 GIM_Try, /*On fail goto*//*Label 1038*/ 38450, // Rule ID 2591 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2591, GIR_Done, // Label 1038: @38450 GIM_Try, /*On fail goto*//*Label 1039*/ 38496, // Rule ID 2592 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2592, GIR_Done, // Label 1039: @38496 GIM_Reject, // Label 1024: @38497 GIM_Try, /*On fail goto*//*Label 1040*/ 38575, // Rule ID 2509 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2509, GIR_Done, // Label 1040: @38575 GIM_Try, /*On fail goto*//*Label 1041*/ 38653, // Rule ID 2510 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2510, GIR_Done, // Label 1041: @38653 GIM_Try, /*On fail goto*//*Label 1042*/ 38731, // Rule ID 2511 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2511, GIR_Done, // Label 1042: @38731 GIM_Try, /*On fail goto*//*Label 1043*/ 38809, // Rule ID 2512 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2512, GIR_Done, // Label 1043: @38809 GIM_Try, /*On fail goto*//*Label 1044*/ 38887, // Rule ID 2513 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2513, GIR_Done, // Label 1044: @38887 GIM_Try, /*On fail goto*//*Label 1045*/ 38965, // Rule ID 2514 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2514, GIR_Done, // Label 1045: @38965 GIM_Try, /*On fail goto*//*Label 1046*/ 39043, // Rule ID 2515 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2515, GIR_Done, // Label 1046: @39043 GIM_Try, /*On fail goto*//*Label 1047*/ 39121, // Rule ID 2516 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2516, GIR_Done, // Label 1047: @39121 GIM_Try, /*On fail goto*//*Label 1048*/ 39195, // Rule ID 2556 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2556, GIR_Done, // Label 1048: @39195 GIM_Try, /*On fail goto*//*Label 1049*/ 39269, // Rule ID 2557 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2557, GIR_Done, // Label 1049: @39269 GIM_Try, /*On fail goto*//*Label 1050*/ 39343, // Rule ID 2559 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2559, GIR_Done, // Label 1050: @39343 GIM_Try, /*On fail goto*//*Label 1051*/ 39417, // Rule ID 2567 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2567, GIR_Done, // Label 1051: @39417 GIM_Try, /*On fail goto*//*Label 1052*/ 39491, // Rule ID 2593 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2593, GIR_Done, // Label 1052: @39491 GIM_Try, /*On fail goto*//*Label 1053*/ 39565, // Rule ID 2594 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2594, GIR_Done, // Label 1053: @39565 GIM_Try, /*On fail goto*//*Label 1054*/ 39639, // Rule ID 2595 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2595, GIR_Done, // Label 1054: @39639 GIM_Try, /*On fail goto*//*Label 1055*/ 39713, // Rule ID 2596 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2596, GIR_Done, // Label 1055: @39713 GIM_Try, /*On fail goto*//*Label 1056*/ 39787, // Rule ID 2597 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2597, GIR_Done, // Label 1056: @39787 GIM_Try, /*On fail goto*//*Label 1057*/ 39861, // Rule ID 2598 // GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2598, GIR_Done, // Label 1057: @39861 GIM_Reject, // Label 1025: @39862 GIM_Reject, // Label 16: @39863 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 15, /*)*//*default:*//*Label 1069*/ 44201, /*GILLT_s16*//*Label 1058*/ 39884, /*GILLT_s32*//*Label 1059*/ 40223, /*GILLT_s64*//*Label 1060*/ 40892, /*GILLT_s128*//*Label 1061*/ 41714, 0, /*GILLT_v2s32*//*Label 1062*/ 41900, /*GILLT_v2s64*//*Label 1063*/ 42272, 0, /*GILLT_v4s16*//*Label 1064*/ 42685, /*GILLT_v4s32*//*Label 1065*/ 43057, 0, /*GILLT_v8s8*//*Label 1066*/ 43429, /*GILLT_v8s16*//*Label 1067*/ 43629, 0, /*GILLT_v16s8*//*Label 1068*/ 44001, // Label 1058: @39884 GIM_Try, /*On fail goto*//*Label 1070*/ 40222, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1071*/ 39961, // Rule ID 3637 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3637, GIR_Done, // Label 1071: @39961 GIM_Try, /*On fail goto*//*Label 1072*/ 40057, // Rule ID 3642 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3642, GIR_Done, // Label 1072: @40057 GIM_Try, /*On fail goto*//*Label 1073*/ 40100, // Rule ID 269 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><> => (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 269, GIR_Done, // Label 1073: @40100 GIM_Try, /*On fail goto*//*Label 1074*/ 40143, // Rule ID 270 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<><> => (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 270, GIR_Done, // Label 1074: @40143 GIM_Try, /*On fail goto*//*Label 1075*/ 40182, // Rule ID 278 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><> => (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 278, GIR_Done, // Label 1075: @40182 GIM_Try, /*On fail goto*//*Label 1076*/ 40221, // Rule ID 286 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 286, GIR_Done, // Label 1076: @40221 GIM_Reject, // Label 1070: @40222 GIM_Reject, // Label 1059: @40223 GIM_Try, /*On fail goto*//*Label 1077*/ 40891, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1078*/ 40300, // Rule ID 3633 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3633, GIR_Done, // Label 1078: @40300 GIM_Try, /*On fail goto*//*Label 1079*/ 40368, // Rule ID 3634 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3634, GIR_Done, // Label 1079: @40368 GIM_Try, /*On fail goto*//*Label 1080*/ 40464, // Rule ID 3640 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3640, GIR_Done, // Label 1080: @40464 GIM_Try, /*On fail goto*//*Label 1081*/ 40560, // Rule ID 3641 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3641, GIR_Done, // Label 1081: @40560 GIM_Try, /*On fail goto*//*Label 1082*/ 40603, // Rule ID 263 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 263, GIR_Done, // Label 1082: @40603 GIM_Try, /*On fail goto*//*Label 1083*/ 40646, // Rule ID 264 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 264, GIR_Done, // Label 1083: @40646 GIM_Try, /*On fail goto*//*Label 1084*/ 40689, // Rule ID 271 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><> => (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 271, GIR_Done, // Label 1084: @40689 GIM_Try, /*On fail goto*//*Label 1085*/ 40732, // Rule ID 272 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<><> => (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 272, GIR_Done, // Label 1085: @40732 GIM_Try, /*On fail goto*//*Label 1086*/ 40772, // Rule ID 276 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 276, GIR_Done, // Label 1086: @40772 GIM_Try, /*On fail goto*//*Label 1087*/ 40811, // Rule ID 279 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><> => (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 279, GIR_Done, // Label 1087: @40811 GIM_Try, /*On fail goto*//*Label 1088*/ 40851, // Rule ID 284 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 284, GIR_Done, // Label 1088: @40851 GIM_Try, /*On fail goto*//*Label 1089*/ 40890, // Rule ID 287 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 287, GIR_Done, // Label 1089: @40890 GIM_Reject, // Label 1077: @40891 GIM_Reject, // Label 1060: @40892 GIM_Try, /*On fail goto*//*Label 1090*/ 41713, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1091*/ 40969, // Rule ID 3635 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3635, GIR_Done, // Label 1091: @40969 GIM_Try, /*On fail goto*//*Label 1092*/ 41037, // Rule ID 3636 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<>:$idx), GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<>:$idx, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3636, GIR_Done, // Label 1092: @41037 GIM_Try, /*On fail goto*//*Label 1093*/ 41080, // Rule ID 265 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 265, GIR_Done, // Label 1093: @41080 GIM_Try, /*On fail goto*//*Label 1094*/ 41123, // Rule ID 266 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 266, GIR_Done, // Label 1094: @41123 GIM_Try, /*On fail goto*//*Label 1095*/ 41166, // Rule ID 273 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 273, GIR_Done, // Label 1095: @41166 GIM_Try, /*On fail goto*//*Label 1096*/ 41209, // Rule ID 274 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 274, GIR_Done, // Label 1096: @41209 GIM_Try, /*On fail goto*//*Label 1097*/ 41252, // Rule ID 2618 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2618, GIR_Done, // Label 1097: @41252 GIM_Try, /*On fail goto*//*Label 1098*/ 41295, // Rule ID 2619 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2619, GIR_Done, // Label 1098: @41295 GIM_Try, /*On fail goto*//*Label 1099*/ 41338, // Rule ID 2620 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2620, GIR_Done, // Label 1099: @41338 GIM_Try, /*On fail goto*//*Label 1100*/ 41381, // Rule ID 2621 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2621, GIR_Done, // Label 1100: @41381 GIM_Try, /*On fail goto*//*Label 1101*/ 41421, // Rule ID 275 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 275, GIR_Done, // Label 1101: @41421 GIM_Try, /*On fail goto*//*Label 1102*/ 41460, // Rule ID 280 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 280, GIR_Done, // Label 1102: @41460 GIM_Try, /*On fail goto*//*Label 1103*/ 41499, // Rule ID 2648 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2648, GIR_Done, // Label 1103: @41499 GIM_Try, /*On fail goto*//*Label 1104*/ 41538, // Rule ID 2649 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2649, GIR_Done, // Label 1104: @41538 GIM_Try, /*On fail goto*//*Label 1105*/ 41578, // Rule ID 283 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 283, GIR_Done, // Label 1105: @41578 GIM_Try, /*On fail goto*//*Label 1106*/ 41617, // Rule ID 288 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 288, GIR_Done, // Label 1106: @41617 GIM_Try, /*On fail goto*//*Label 1107*/ 41656, // Rule ID 2672 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2672, GIR_Done, // Label 1107: @41656 GIM_Try, /*On fail goto*//*Label 1108*/ 41695, // Rule ID 2673 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2673, GIR_Done, // Label 1108: @41695 GIM_Try, /*On fail goto*//*Label 1109*/ 41712, // Rule ID 3604 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev1d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3604, GIR_Done, // Label 1109: @41712 GIM_Reject, // Label 1090: @41713 GIM_Reject, // Label 1061: @41714 GIM_Try, /*On fail goto*//*Label 1110*/ 41899, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_Try, /*On fail goto*//*Label 1111*/ 41768, // Rule ID 2600 // GIM_CheckFeatures, GIFBS_UseSTRQro, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2600, GIR_Done, // Label 1111: @41768 GIM_Try, /*On fail goto*//*Label 1112*/ 41805, // Rule ID 2601 // GIM_CheckFeatures, GIFBS_UseSTRQro, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2601, GIR_Done, // Label 1112: @41805 GIM_Try, /*On fail goto*//*Label 1113*/ 41836, // Rule ID 2655 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2655, GIR_Done, // Label 1113: @41836 GIM_Try, /*On fail goto*//*Label 1114*/ 41867, // Rule ID 2679 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2679, GIR_Done, // Label 1114: @41867 GIM_Try, /*On fail goto*//*Label 1115*/ 41898, // Rule ID 289 // GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 289, GIR_Done, // Label 1115: @41898 GIM_Reject, // Label 1110: @41899 GIM_Reject, // Label 1062: @41900 GIM_Try, /*On fail goto*//*Label 1116*/ 42271, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1117*/ 41954, // Rule ID 2608 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2608, GIR_Done, // Label 1117: @41954 GIM_Try, /*On fail goto*//*Label 1118*/ 41999, // Rule ID 2609 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2609, GIR_Done, // Label 1118: @41999 GIM_Try, /*On fail goto*//*Label 1119*/ 42044, // Rule ID 2610 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2610, GIR_Done, // Label 1119: @42044 GIM_Try, /*On fail goto*//*Label 1120*/ 42089, // Rule ID 2611 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2611, GIR_Done, // Label 1120: @42089 GIM_Try, /*On fail goto*//*Label 1121*/ 42130, // Rule ID 2650 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2650, GIR_Done, // Label 1121: @42130 GIM_Try, /*On fail goto*//*Label 1122*/ 42171, // Rule ID 2653 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2653, GIR_Done, // Label 1122: @42171 GIM_Try, /*On fail goto*//*Label 1123*/ 42212, // Rule ID 2674 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2674, GIR_Done, // Label 1123: @42212 GIM_Try, /*On fail goto*//*Label 1124*/ 42253, // Rule ID 2677 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2677, GIR_Done, // Label 1124: @42253 GIM_Try, /*On fail goto*//*Label 1125*/ 42270, // Rule ID 3603 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3603, GIR_Done, // Label 1125: @42270 GIM_Reject, // Label 1116: @42271 GIM_Reject, // Label 1063: @42272 GIM_Try, /*On fail goto*//*Label 1126*/ 42684, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1127*/ 42326, // Rule ID 2622 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2622, GIR_Done, // Label 1127: @42326 GIM_Try, /*On fail goto*//*Label 1128*/ 42371, // Rule ID 2623 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2623, GIR_Done, // Label 1128: @42371 GIM_Try, /*On fail goto*//*Label 1129*/ 42416, // Rule ID 2624 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2624, GIR_Done, // Label 1129: @42416 GIM_Try, /*On fail goto*//*Label 1130*/ 42461, // Rule ID 2625 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2625, GIR_Done, // Label 1130: @42461 GIM_Try, /*On fail goto*//*Label 1131*/ 42502, // Rule ID 2657 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2657, GIR_Done, // Label 1131: @42502 GIM_Try, /*On fail goto*//*Label 1132*/ 42543, // Rule ID 2661 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2661, GIR_Done, // Label 1132: @42543 GIM_Try, /*On fail goto*//*Label 1133*/ 42584, // Rule ID 2681 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2681, GIR_Done, // Label 1133: @42584 GIM_Try, /*On fail goto*//*Label 1134*/ 42625, // Rule ID 2685 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2685, GIR_Done, // Label 1134: @42625 GIM_Try, /*On fail goto*//*Label 1135*/ 42666, // Rule ID 2686 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2686, GIR_Done, // Label 1135: @42666 GIM_Try, /*On fail goto*//*Label 1136*/ 42683, // Rule ID 3600 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2d, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3600, GIR_Done, // Label 1136: @42683 GIM_Reject, // Label 1126: @42684 GIM_Reject, // Label 1064: @42685 GIM_Try, /*On fail goto*//*Label 1137*/ 43056, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1138*/ 42739, // Rule ID 2612 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2612, GIR_Done, // Label 1138: @42739 GIM_Try, /*On fail goto*//*Label 1139*/ 42784, // Rule ID 2613 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2613, GIR_Done, // Label 1139: @42784 GIM_Try, /*On fail goto*//*Label 1140*/ 42829, // Rule ID 2616 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2616, GIR_Done, // Label 1140: @42829 GIM_Try, /*On fail goto*//*Label 1141*/ 42874, // Rule ID 2617 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2617, GIR_Done, // Label 1141: @42874 GIM_Try, /*On fail goto*//*Label 1142*/ 42915, // Rule ID 2652 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2652, GIR_Done, // Label 1142: @42915 GIM_Try, /*On fail goto*//*Label 1143*/ 42956, // Rule ID 2654 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2654, GIR_Done, // Label 1143: @42956 GIM_Try, /*On fail goto*//*Label 1144*/ 42997, // Rule ID 2676 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2676, GIR_Done, // Label 1144: @42997 GIM_Try, /*On fail goto*//*Label 1145*/ 43038, // Rule ID 2678 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2678, GIR_Done, // Label 1145: @43038 GIM_Try, /*On fail goto*//*Label 1146*/ 43055, // Rule ID 3602 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3602, GIR_Done, // Label 1146: @43055 GIM_Reject, // Label 1137: @43056 GIM_Reject, // Label 1065: @43057 GIM_Try, /*On fail goto*//*Label 1147*/ 43428, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1148*/ 43111, // Rule ID 2626 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2626, GIR_Done, // Label 1148: @43111 GIM_Try, /*On fail goto*//*Label 1149*/ 43156, // Rule ID 2627 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2627, GIR_Done, // Label 1149: @43156 GIM_Try, /*On fail goto*//*Label 1150*/ 43201, // Rule ID 2628 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2628, GIR_Done, // Label 1150: @43201 GIM_Try, /*On fail goto*//*Label 1151*/ 43246, // Rule ID 2629 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2629, GIR_Done, // Label 1151: @43246 GIM_Try, /*On fail goto*//*Label 1152*/ 43287, // Rule ID 2656 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2656, GIR_Done, // Label 1152: @43287 GIM_Try, /*On fail goto*//*Label 1153*/ 43328, // Rule ID 2660 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2660, GIR_Done, // Label 1153: @43328 GIM_Try, /*On fail goto*//*Label 1154*/ 43369, // Rule ID 2680 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2680, GIR_Done, // Label 1154: @43369 GIM_Try, /*On fail goto*//*Label 1155*/ 43410, // Rule ID 2684 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2684, GIR_Done, // Label 1155: @43410 GIM_Try, /*On fail goto*//*Label 1156*/ 43427, // Rule ID 3599 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4s, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3599, GIR_Done, // Label 1156: @43427 GIM_Reject, // Label 1147: @43428 GIM_Reject, // Label 1066: @43429 GIM_Try, /*On fail goto*//*Label 1157*/ 43628, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1158*/ 43483, // Rule ID 2614 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<><> => (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2614, GIR_Done, // Label 1158: @43483 GIM_Try, /*On fail goto*//*Label 1159*/ 43528, // Rule ID 2615 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<><> => (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2615, GIR_Done, // Label 1159: @43528 GIM_Try, /*On fail goto*//*Label 1160*/ 43569, // Rule ID 2651 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<><> => (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2651, GIR_Done, // Label 1160: @43569 GIM_Try, /*On fail goto*//*Label 1161*/ 43610, // Rule ID 2675 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2675, GIR_Done, // Label 1161: @43610 GIM_Try, /*On fail goto*//*Label 1162*/ 43627, // Rule ID 3601 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3601, GIR_Done, // Label 1162: @43627 GIM_Reject, // Label 1157: @43628 GIM_Reject, // Label 1067: @43629 GIM_Try, /*On fail goto*//*Label 1163*/ 44000, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1164*/ 43683, // Rule ID 2630 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2630, GIR_Done, // Label 1164: @43683 GIM_Try, /*On fail goto*//*Label 1165*/ 43728, // Rule ID 2631 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2631, GIR_Done, // Label 1165: @43728 GIM_Try, /*On fail goto*//*Label 1166*/ 43773, // Rule ID 2634 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2634, GIR_Done, // Label 1166: @43773 GIM_Try, /*On fail goto*//*Label 1167*/ 43818, // Rule ID 2635 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2635, GIR_Done, // Label 1167: @43818 GIM_Try, /*On fail goto*//*Label 1168*/ 43859, // Rule ID 2659 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2659, GIR_Done, // Label 1168: @43859 GIM_Try, /*On fail goto*//*Label 1169*/ 43900, // Rule ID 2662 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2662, GIR_Done, // Label 1169: @43900 GIM_Try, /*On fail goto*//*Label 1170*/ 43941, // Rule ID 2683 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2683, GIR_Done, // Label 1170: @43941 GIM_Try, /*On fail goto*//*Label 1171*/ 43982, // Rule ID 2687 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2687, GIR_Done, // Label 1171: @43982 GIM_Try, /*On fail goto*//*Label 1172*/ 43999, // Rule ID 3598 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8h, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3598, GIR_Done, // Label 1172: @43999 GIM_Reject, // Label 1163: @44000 GIM_Reject, // Label 1068: @44001 GIM_Try, /*On fail goto*//*Label 1173*/ 44200, GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_Try, /*On fail goto*//*Label 1174*/ 44055, // Rule ID 2632 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<><> => (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2632, GIR_Done, // Label 1174: @44055 GIM_Try, /*On fail goto*//*Label 1175*/ 44100, // Rule ID 2633 // GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<><> => (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2633, GIR_Done, // Label 1175: @44100 GIM_Try, /*On fail goto*//*Label 1176*/ 44141, // Rule ID 2658 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<><> => (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2658, GIR_Done, // Label 1176: @44141 GIM_Try, /*On fail goto*//*Label 1177*/ 44182, // Rule ID 2682 // GIM_CheckFeatures, GIFBS_IsLE, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><> => (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2682, GIR_Done, // Label 1177: @44182 GIM_Try, /*On fail goto*//*Label 1178*/ 44199, // Rule ID 3597 // // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<><> => (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev16b, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3597, GIR_Done, // Label 1178: @44199 GIM_Reject, // Label 1173: @44200 GIM_Reject, // Label 1069: @44201 GIM_Reject, // Label 17: @44202 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1181*/ 45398, /*GILLT_s32*//*Label 1179*/ 44210, /*GILLT_s64*//*Label 1180*/ 45107, // Label 1179: @44210 GIM_Try, /*On fail goto*//*Label 1182*/ 45106, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1183*/ 44279, // Rule ID 4323 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4323, GIR_Done, // Label 1183: @44279 GIM_Try, /*On fail goto*//*Label 1184*/ 44338, // Rule ID 4324 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4324, GIR_Done, // Label 1184: @44338 GIM_Try, /*On fail goto*//*Label 1185*/ 44397, // Rule ID 4325 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4325, GIR_Done, // Label 1185: @44397 GIM_Try, /*On fail goto*//*Label 1186*/ 44456, // Rule ID 4326 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4326, GIR_Done, // Label 1186: @44456 GIM_Try, /*On fail goto*//*Label 1187*/ 44515, // Rule ID 4327 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4327, GIR_Done, // Label 1187: @44515 GIM_Try, /*On fail goto*//*Label 1188*/ 44574, // Rule ID 4328 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4328, GIR_Done, // Label 1188: @44574 GIM_Try, /*On fail goto*//*Label 1189*/ 44633, // Rule ID 4329 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4329, GIR_Done, // Label 1189: @44633 GIM_Try, /*On fail goto*//*Label 1190*/ 44692, // Rule ID 4330 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4330, GIR_Done, // Label 1190: @44692 GIM_Try, /*On fail goto*//*Label 1191*/ 44751, // Rule ID 4331 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4331, GIR_Done, // Label 1191: @44751 GIM_Try, /*On fail goto*//*Label 1192*/ 44810, // Rule ID 4332 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4332, GIR_Done, // Label 1192: @44810 GIM_Try, /*On fail goto*//*Label 1193*/ 44869, // Rule ID 4333 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4333, GIR_Done, // Label 1193: @44869 GIM_Try, /*On fail goto*//*Label 1194*/ 44928, // Rule ID 4334 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4334, GIR_Done, // Label 1194: @44928 GIM_Try, /*On fail goto*//*Label 1195*/ 44987, // Rule ID 4335 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4335, GIR_Done, // Label 1195: @44987 GIM_Try, /*On fail goto*//*Label 1196*/ 45046, // Rule ID 4336 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4336, GIR_Done, // Label 1196: @45046 GIM_Try, /*On fail goto*//*Label 1197*/ 45105, // Rule ID 4337 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<><> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4337, GIR_Done, // Label 1197: @45105 GIM_Reject, // Label 1182: @45106 GIM_Reject, // Label 1180: @45107 GIM_Try, /*On fail goto*//*Label 1198*/ 45397, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1199*/ 45176, // Rule ID 1918 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1918, GIR_Done, // Label 1199: @45176 GIM_Try, /*On fail goto*//*Label 1200*/ 45231, // Rule ID 1919 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1919, GIR_Done, // Label 1200: @45231 GIM_Try, /*On fail goto*//*Label 1201*/ 45286, // Rule ID 1920 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1920, GIR_Done, // Label 1201: @45286 GIM_Try, /*On fail goto*//*Label 1202*/ 45341, // Rule ID 1921 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1921, GIR_Done, // Label 1202: @45341 GIM_Try, /*On fail goto*//*Label 1203*/ 45396, // Rule ID 1922 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<><> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1922, GIR_Done, // Label 1203: @45396 GIM_Reject, // Label 1198: @45397 GIM_Reject, // Label 1181: @45398 GIM_Reject, // Label 18: @45399 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1206*/ 46427, /*GILLT_s32*//*Label 1204*/ 45407, /*GILLT_s64*//*Label 1205*/ 46180, // Label 1204: @45407 GIM_Try, /*On fail goto*//*Label 1207*/ 46179, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1208*/ 45464, // Rule ID 4308 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4308, GIR_Done, // Label 1208: @45464 GIM_Try, /*On fail goto*//*Label 1209*/ 45515, // Rule ID 4309 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4309, GIR_Done, // Label 1209: @45515 GIM_Try, /*On fail goto*//*Label 1210*/ 45566, // Rule ID 4310 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4310, GIR_Done, // Label 1210: @45566 GIM_Try, /*On fail goto*//*Label 1211*/ 45617, // Rule ID 4311 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4311, GIR_Done, // Label 1211: @45617 GIM_Try, /*On fail goto*//*Label 1212*/ 45668, // Rule ID 4312 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4312, GIR_Done, // Label 1212: @45668 GIM_Try, /*On fail goto*//*Label 1213*/ 45719, // Rule ID 4313 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4313, GIR_Done, // Label 1213: @45719 GIM_Try, /*On fail goto*//*Label 1214*/ 45770, // Rule ID 4314 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4314, GIR_Done, // Label 1214: @45770 GIM_Try, /*On fail goto*//*Label 1215*/ 45821, // Rule ID 4315 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4315, GIR_Done, // Label 1215: @45821 GIM_Try, /*On fail goto*//*Label 1216*/ 45872, // Rule ID 4316 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4316, GIR_Done, // Label 1216: @45872 GIM_Try, /*On fail goto*//*Label 1217*/ 45923, // Rule ID 4317 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4317, GIR_Done, // Label 1217: @45923 GIM_Try, /*On fail goto*//*Label 1218*/ 45974, // Rule ID 4318 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4318, GIR_Done, // Label 1218: @45974 GIM_Try, /*On fail goto*//*Label 1219*/ 46025, // Rule ID 4319 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4319, GIR_Done, // Label 1219: @46025 GIM_Try, /*On fail goto*//*Label 1220*/ 46076, // Rule ID 4320 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4320, GIR_Done, // Label 1220: @46076 GIM_Try, /*On fail goto*//*Label 1221*/ 46127, // Rule ID 4321 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4321, GIR_Done, // Label 1221: @46127 GIM_Try, /*On fail goto*//*Label 1222*/ 46178, // Rule ID 4322 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4322, GIR_Done, // Label 1222: @46178 GIM_Reject, // Label 1207: @46179 GIM_Reject, // Label 1205: @46180 GIM_Try, /*On fail goto*//*Label 1223*/ 46426, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1224*/ 46237, // Rule ID 4303 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4303, GIR_Done, // Label 1224: @46237 GIM_Try, /*On fail goto*//*Label 1225*/ 46284, // Rule ID 4304 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4304, GIR_Done, // Label 1225: @46284 GIM_Try, /*On fail goto*//*Label 1226*/ 46331, // Rule ID 4305 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4305, GIR_Done, // Label 1226: @46331 GIM_Try, /*On fail goto*//*Label 1227*/ 46378, // Rule ID 4306 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4306, GIR_Done, // Label 1227: @46378 GIM_Try, /*On fail goto*//*Label 1228*/ 46425, // Rule ID 4307 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4307, GIR_Done, // Label 1228: @46425 GIM_Reject, // Label 1223: @46426 GIM_Reject, // Label 1206: @46427 GIM_Reject, // Label 19: @46428 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1231*/ 47456, /*GILLT_s32*//*Label 1229*/ 46436, /*GILLT_s64*//*Label 1230*/ 47209, // Label 1229: @46436 GIM_Try, /*On fail goto*//*Label 1232*/ 47208, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1233*/ 46493, // Rule ID 4148 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4148, GIR_Done, // Label 1233: @46493 GIM_Try, /*On fail goto*//*Label 1234*/ 46544, // Rule ID 4149 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4149, GIR_Done, // Label 1234: @46544 GIM_Try, /*On fail goto*//*Label 1235*/ 46595, // Rule ID 4150 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4150, GIR_Done, // Label 1235: @46595 GIM_Try, /*On fail goto*//*Label 1236*/ 46646, // Rule ID 4151 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4151, GIR_Done, // Label 1236: @46646 GIM_Try, /*On fail goto*//*Label 1237*/ 46697, // Rule ID 4152 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4152, GIR_Done, // Label 1237: @46697 GIM_Try, /*On fail goto*//*Label 1238*/ 46748, // Rule ID 4153 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4153, GIR_Done, // Label 1238: @46748 GIM_Try, /*On fail goto*//*Label 1239*/ 46799, // Rule ID 4154 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4154, GIR_Done, // Label 1239: @46799 GIM_Try, /*On fail goto*//*Label 1240*/ 46850, // Rule ID 4155 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4155, GIR_Done, // Label 1240: @46850 GIM_Try, /*On fail goto*//*Label 1241*/ 46901, // Rule ID 4156 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4156, GIR_Done, // Label 1241: @46901 GIM_Try, /*On fail goto*//*Label 1242*/ 46952, // Rule ID 4157 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4157, GIR_Done, // Label 1242: @46952 GIM_Try, /*On fail goto*//*Label 1243*/ 47003, // Rule ID 4158 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4158, GIR_Done, // Label 1243: @47003 GIM_Try, /*On fail goto*//*Label 1244*/ 47054, // Rule ID 4159 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4159, GIR_Done, // Label 1244: @47054 GIM_Try, /*On fail goto*//*Label 1245*/ 47105, // Rule ID 4160 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4160, GIR_Done, // Label 1245: @47105 GIM_Try, /*On fail goto*//*Label 1246*/ 47156, // Rule ID 4161 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4161, GIR_Done, // Label 1246: @47156 GIM_Try, /*On fail goto*//*Label 1247*/ 47207, // Rule ID 4162 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4162, GIR_Done, // Label 1247: @47207 GIM_Reject, // Label 1232: @47208 GIM_Reject, // Label 1230: @47209 GIM_Try, /*On fail goto*//*Label 1248*/ 47455, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1249*/ 47266, // Rule ID 1913 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1913, GIR_Done, // Label 1249: @47266 GIM_Try, /*On fail goto*//*Label 1250*/ 47313, // Rule ID 1914 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1914, GIR_Done, // Label 1250: @47313 GIM_Try, /*On fail goto*//*Label 1251*/ 47360, // Rule ID 1915 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1915, GIR_Done, // Label 1251: @47360 GIM_Try, /*On fail goto*//*Label 1252*/ 47407, // Rule ID 1916 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1916, GIR_Done, // Label 1252: @47407 GIM_Try, /*On fail goto*//*Label 1253*/ 47454, // Rule ID 1917 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1917, GIR_Done, // Label 1253: @47454 GIM_Reject, // Label 1248: @47455 GIM_Reject, // Label 1231: @47456 GIM_Reject, // Label 20: @47457 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1256*/ 48885, /*GILLT_s32*//*Label 1254*/ 47465, /*GILLT_s64*//*Label 1255*/ 48538, // Label 1254: @47465 GIM_Try, /*On fail goto*//*Label 1257*/ 48537, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1258*/ 47542, // Rule ID 4343 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4343, GIR_Done, // Label 1258: @47542 GIM_Try, /*On fail goto*//*Label 1259*/ 47613, // Rule ID 4344 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4344, GIR_Done, // Label 1259: @47613 GIM_Try, /*On fail goto*//*Label 1260*/ 47684, // Rule ID 4345 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4345, GIR_Done, // Label 1260: @47684 GIM_Try, /*On fail goto*//*Label 1261*/ 47755, // Rule ID 4346 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4346, GIR_Done, // Label 1261: @47755 GIM_Try, /*On fail goto*//*Label 1262*/ 47826, // Rule ID 4347 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4347, GIR_Done, // Label 1262: @47826 GIM_Try, /*On fail goto*//*Label 1263*/ 47897, // Rule ID 4348 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4348, GIR_Done, // Label 1263: @47897 GIM_Try, /*On fail goto*//*Label 1264*/ 47968, // Rule ID 4349 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4349, GIR_Done, // Label 1264: @47968 GIM_Try, /*On fail goto*//*Label 1265*/ 48039, // Rule ID 4350 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4350, GIR_Done, // Label 1265: @48039 GIM_Try, /*On fail goto*//*Label 1266*/ 48110, // Rule ID 4351 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4351, GIR_Done, // Label 1266: @48110 GIM_Try, /*On fail goto*//*Label 1267*/ 48181, // Rule ID 4352 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4352, GIR_Done, // Label 1267: @48181 GIM_Try, /*On fail goto*//*Label 1268*/ 48252, // Rule ID 4353 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4353, GIR_Done, // Label 1268: @48252 GIM_Try, /*On fail goto*//*Label 1269*/ 48323, // Rule ID 4354 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4354, GIR_Done, // Label 1269: @48323 GIM_Try, /*On fail goto*//*Label 1270*/ 48394, // Rule ID 4355 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4355, GIR_Done, // Label 1270: @48394 GIM_Try, /*On fail goto*//*Label 1271*/ 48465, // Rule ID 4356 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4356, GIR_Done, // Label 1271: @48465 GIM_Try, /*On fail goto*//*Label 1272*/ 48536, // Rule ID 4357 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4357, GIR_Done, // Label 1272: @48536 GIM_Reject, // Label 1257: @48537 GIM_Reject, // Label 1255: @48538 GIM_Try, /*On fail goto*//*Label 1273*/ 48884, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1274*/ 48615, // Rule ID 4338 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4338, GIR_Done, // Label 1274: @48615 GIM_Try, /*On fail goto*//*Label 1275*/ 48682, // Rule ID 4339 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4339, GIR_Done, // Label 1275: @48682 GIM_Try, /*On fail goto*//*Label 1276*/ 48749, // Rule ID 4340 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4340, GIR_Done, // Label 1276: @48749 GIM_Try, /*On fail goto*//*Label 1277*/ 48816, // Rule ID 4341 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4341, GIR_Done, // Label 1277: @48816 GIM_Try, /*On fail goto*//*Label 1278*/ 48883, // Rule ID 4342 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4342, GIR_Done, // Label 1278: @48883 GIM_Reject, // Label 1273: @48884 GIM_Reject, // Label 1256: @48885 GIM_Reject, // Label 21: @48886 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1281*/ 50314, /*GILLT_s32*//*Label 1279*/ 48894, /*GILLT_s64*//*Label 1280*/ 49967, // Label 1279: @48894 GIM_Try, /*On fail goto*//*Label 1282*/ 49966, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1283*/ 48971, // Rule ID 4363 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4363, GIR_Done, // Label 1283: @48971 GIM_Try, /*On fail goto*//*Label 1284*/ 49042, // Rule ID 4364 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4364, GIR_Done, // Label 1284: @49042 GIM_Try, /*On fail goto*//*Label 1285*/ 49113, // Rule ID 4365 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4365, GIR_Done, // Label 1285: @49113 GIM_Try, /*On fail goto*//*Label 1286*/ 49184, // Rule ID 4366 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4366, GIR_Done, // Label 1286: @49184 GIM_Try, /*On fail goto*//*Label 1287*/ 49255, // Rule ID 4367 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4367, GIR_Done, // Label 1287: @49255 GIM_Try, /*On fail goto*//*Label 1288*/ 49326, // Rule ID 4368 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4368, GIR_Done, // Label 1288: @49326 GIM_Try, /*On fail goto*//*Label 1289*/ 49397, // Rule ID 4369 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4369, GIR_Done, // Label 1289: @49397 GIM_Try, /*On fail goto*//*Label 1290*/ 49468, // Rule ID 4370 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4370, GIR_Done, // Label 1290: @49468 GIM_Try, /*On fail goto*//*Label 1291*/ 49539, // Rule ID 4371 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4371, GIR_Done, // Label 1291: @49539 GIM_Try, /*On fail goto*//*Label 1292*/ 49610, // Rule ID 4372 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4372, GIR_Done, // Label 1292: @49610 GIM_Try, /*On fail goto*//*Label 1293*/ 49681, // Rule ID 4373 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4373, GIR_Done, // Label 1293: @49681 GIM_Try, /*On fail goto*//*Label 1294*/ 49752, // Rule ID 4374 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4374, GIR_Done, // Label 1294: @49752 GIM_Try, /*On fail goto*//*Label 1295*/ 49823, // Rule ID 4375 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4375, GIR_Done, // Label 1295: @49823 GIM_Try, /*On fail goto*//*Label 1296*/ 49894, // Rule ID 4376 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4376, GIR_Done, // Label 1296: @49894 GIM_Try, /*On fail goto*//*Label 1297*/ 49965, // Rule ID 4377 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4377, GIR_Done, // Label 1297: @49965 GIM_Reject, // Label 1282: @49966 GIM_Reject, // Label 1280: @49967 GIM_Try, /*On fail goto*//*Label 1298*/ 50313, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1299*/ 50044, // Rule ID 4358 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4358, GIR_Done, // Label 1299: @50044 GIM_Try, /*On fail goto*//*Label 1300*/ 50111, // Rule ID 4359 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4359, GIR_Done, // Label 1300: @50111 GIM_Try, /*On fail goto*//*Label 1301*/ 50178, // Rule ID 4360 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4360, GIR_Done, // Label 1301: @50178 GIM_Try, /*On fail goto*//*Label 1302*/ 50245, // Rule ID 4361 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4361, GIR_Done, // Label 1302: @50245 GIM_Try, /*On fail goto*//*Label 1303*/ 50312, // Rule ID 4362 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4362, GIR_Done, // Label 1303: @50312 GIM_Reject, // Label 1298: @50313 GIM_Reject, // Label 1281: @50314 GIM_Reject, // Label 22: @50315 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1306*/ 51343, /*GILLT_s32*//*Label 1304*/ 50323, /*GILLT_s64*//*Label 1305*/ 51096, // Label 1304: @50323 GIM_Try, /*On fail goto*//*Label 1307*/ 51095, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1308*/ 50380, // Rule ID 4168 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4168, GIR_Done, // Label 1308: @50380 GIM_Try, /*On fail goto*//*Label 1309*/ 50431, // Rule ID 4169 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4169, GIR_Done, // Label 1309: @50431 GIM_Try, /*On fail goto*//*Label 1310*/ 50482, // Rule ID 4170 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4170, GIR_Done, // Label 1310: @50482 GIM_Try, /*On fail goto*//*Label 1311*/ 50533, // Rule ID 4171 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4171, GIR_Done, // Label 1311: @50533 GIM_Try, /*On fail goto*//*Label 1312*/ 50584, // Rule ID 4172 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4172, GIR_Done, // Label 1312: @50584 GIM_Try, /*On fail goto*//*Label 1313*/ 50635, // Rule ID 4173 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4173, GIR_Done, // Label 1313: @50635 GIM_Try, /*On fail goto*//*Label 1314*/ 50686, // Rule ID 4174 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4174, GIR_Done, // Label 1314: @50686 GIM_Try, /*On fail goto*//*Label 1315*/ 50737, // Rule ID 4175 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4175, GIR_Done, // Label 1315: @50737 GIM_Try, /*On fail goto*//*Label 1316*/ 50788, // Rule ID 4176 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4176, GIR_Done, // Label 1316: @50788 GIM_Try, /*On fail goto*//*Label 1317*/ 50839, // Rule ID 4177 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4177, GIR_Done, // Label 1317: @50839 GIM_Try, /*On fail goto*//*Label 1318*/ 50890, // Rule ID 4178 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4178, GIR_Done, // Label 1318: @50890 GIM_Try, /*On fail goto*//*Label 1319*/ 50941, // Rule ID 4179 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4179, GIR_Done, // Label 1319: @50941 GIM_Try, /*On fail goto*//*Label 1320*/ 50992, // Rule ID 4180 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4180, GIR_Done, // Label 1320: @50992 GIM_Try, /*On fail goto*//*Label 1321*/ 51043, // Rule ID 4181 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4181, GIR_Done, // Label 1321: @51043 GIM_Try, /*On fail goto*//*Label 1322*/ 51094, // Rule ID 4182 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4182, GIR_Done, // Label 1322: @51094 GIM_Reject, // Label 1307: @51095 GIM_Reject, // Label 1305: @51096 GIM_Try, /*On fail goto*//*Label 1323*/ 51342, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1324*/ 51153, // Rule ID 4163 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4163, GIR_Done, // Label 1324: @51153 GIM_Try, /*On fail goto*//*Label 1325*/ 51200, // Rule ID 4164 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4164, GIR_Done, // Label 1325: @51200 GIM_Try, /*On fail goto*//*Label 1326*/ 51247, // Rule ID 4165 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4165, GIR_Done, // Label 1326: @51247 GIM_Try, /*On fail goto*//*Label 1327*/ 51294, // Rule ID 4166 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4166, GIR_Done, // Label 1327: @51294 GIM_Try, /*On fail goto*//*Label 1328*/ 51341, // Rule ID 4167 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4167, GIR_Done, // Label 1328: @51341 GIM_Reject, // Label 1323: @51342 GIM_Reject, // Label 1306: @51343 GIM_Reject, // Label 23: @51344 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1331*/ 52372, /*GILLT_s32*//*Label 1329*/ 51352, /*GILLT_s64*//*Label 1330*/ 52125, // Label 1329: @51352 GIM_Try, /*On fail goto*//*Label 1332*/ 52124, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1333*/ 51409, // Rule ID 4188 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4188, GIR_Done, // Label 1333: @51409 GIM_Try, /*On fail goto*//*Label 1334*/ 51460, // Rule ID 4189 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4189, GIR_Done, // Label 1334: @51460 GIM_Try, /*On fail goto*//*Label 1335*/ 51511, // Rule ID 4190 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4190, GIR_Done, // Label 1335: @51511 GIM_Try, /*On fail goto*//*Label 1336*/ 51562, // Rule ID 4191 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4191, GIR_Done, // Label 1336: @51562 GIM_Try, /*On fail goto*//*Label 1337*/ 51613, // Rule ID 4192 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4192, GIR_Done, // Label 1337: @51613 GIM_Try, /*On fail goto*//*Label 1338*/ 51664, // Rule ID 4193 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4193, GIR_Done, // Label 1338: @51664 GIM_Try, /*On fail goto*//*Label 1339*/ 51715, // Rule ID 4194 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4194, GIR_Done, // Label 1339: @51715 GIM_Try, /*On fail goto*//*Label 1340*/ 51766, // Rule ID 4195 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4195, GIR_Done, // Label 1340: @51766 GIM_Try, /*On fail goto*//*Label 1341*/ 51817, // Rule ID 4196 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4196, GIR_Done, // Label 1341: @51817 GIM_Try, /*On fail goto*//*Label 1342*/ 51868, // Rule ID 4197 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4197, GIR_Done, // Label 1342: @51868 GIM_Try, /*On fail goto*//*Label 1343*/ 51919, // Rule ID 4198 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4198, GIR_Done, // Label 1343: @51919 GIM_Try, /*On fail goto*//*Label 1344*/ 51970, // Rule ID 4199 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4199, GIR_Done, // Label 1344: @51970 GIM_Try, /*On fail goto*//*Label 1345*/ 52021, // Rule ID 4200 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4200, GIR_Done, // Label 1345: @52021 GIM_Try, /*On fail goto*//*Label 1346*/ 52072, // Rule ID 4201 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4201, GIR_Done, // Label 1346: @52072 GIM_Try, /*On fail goto*//*Label 1347*/ 52123, // Rule ID 4202 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4202, GIR_Done, // Label 1347: @52123 GIM_Reject, // Label 1332: @52124 GIM_Reject, // Label 1330: @52125 GIM_Try, /*On fail goto*//*Label 1348*/ 52371, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1349*/ 52182, // Rule ID 4183 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4183, GIR_Done, // Label 1349: @52182 GIM_Try, /*On fail goto*//*Label 1350*/ 52229, // Rule ID 4184 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4184, GIR_Done, // Label 1350: @52229 GIM_Try, /*On fail goto*//*Label 1351*/ 52276, // Rule ID 4185 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4185, GIR_Done, // Label 1351: @52276 GIM_Try, /*On fail goto*//*Label 1352*/ 52323, // Rule ID 4186 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4186, GIR_Done, // Label 1352: @52323 GIM_Try, /*On fail goto*//*Label 1353*/ 52370, // Rule ID 4187 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4187, GIR_Done, // Label 1353: @52370 GIM_Reject, // Label 1348: @52371 GIM_Reject, // Label 1331: @52372 GIM_Reject, // Label 24: @52373 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1356*/ 53401, /*GILLT_s32*//*Label 1354*/ 52381, /*GILLT_s64*//*Label 1355*/ 53154, // Label 1354: @52381 GIM_Try, /*On fail goto*//*Label 1357*/ 53153, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1358*/ 52438, // Rule ID 4228 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4228, GIR_Done, // Label 1358: @52438 GIM_Try, /*On fail goto*//*Label 1359*/ 52489, // Rule ID 4229 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4229, GIR_Done, // Label 1359: @52489 GIM_Try, /*On fail goto*//*Label 1360*/ 52540, // Rule ID 4230 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4230, GIR_Done, // Label 1360: @52540 GIM_Try, /*On fail goto*//*Label 1361*/ 52591, // Rule ID 4231 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4231, GIR_Done, // Label 1361: @52591 GIM_Try, /*On fail goto*//*Label 1362*/ 52642, // Rule ID 4232 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4232, GIR_Done, // Label 1362: @52642 GIM_Try, /*On fail goto*//*Label 1363*/ 52693, // Rule ID 4233 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4233, GIR_Done, // Label 1363: @52693 GIM_Try, /*On fail goto*//*Label 1364*/ 52744, // Rule ID 4234 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4234, GIR_Done, // Label 1364: @52744 GIM_Try, /*On fail goto*//*Label 1365*/ 52795, // Rule ID 4235 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4235, GIR_Done, // Label 1365: @52795 GIM_Try, /*On fail goto*//*Label 1366*/ 52846, // Rule ID 4236 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4236, GIR_Done, // Label 1366: @52846 GIM_Try, /*On fail goto*//*Label 1367*/ 52897, // Rule ID 4237 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4237, GIR_Done, // Label 1367: @52897 GIM_Try, /*On fail goto*//*Label 1368*/ 52948, // Rule ID 4238 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4238, GIR_Done, // Label 1368: @52948 GIM_Try, /*On fail goto*//*Label 1369*/ 52999, // Rule ID 4239 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4239, GIR_Done, // Label 1369: @52999 GIM_Try, /*On fail goto*//*Label 1370*/ 53050, // Rule ID 4240 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4240, GIR_Done, // Label 1370: @53050 GIM_Try, /*On fail goto*//*Label 1371*/ 53101, // Rule ID 4241 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4241, GIR_Done, // Label 1371: @53101 GIM_Try, /*On fail goto*//*Label 1372*/ 53152, // Rule ID 4242 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4242, GIR_Done, // Label 1372: @53152 GIM_Reject, // Label 1357: @53153 GIM_Reject, // Label 1355: @53154 GIM_Try, /*On fail goto*//*Label 1373*/ 53400, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1374*/ 53211, // Rule ID 4223 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4223, GIR_Done, // Label 1374: @53211 GIM_Try, /*On fail goto*//*Label 1375*/ 53258, // Rule ID 4224 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4224, GIR_Done, // Label 1375: @53258 GIM_Try, /*On fail goto*//*Label 1376*/ 53305, // Rule ID 4225 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4225, GIR_Done, // Label 1376: @53305 GIM_Try, /*On fail goto*//*Label 1377*/ 53352, // Rule ID 4226 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4226, GIR_Done, // Label 1377: @53352 GIM_Try, /*On fail goto*//*Label 1378*/ 53399, // Rule ID 4227 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4227, GIR_Done, // Label 1378: @53399 GIM_Reject, // Label 1373: @53400 GIM_Reject, // Label 1356: @53401 GIM_Reject, // Label 25: @53402 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1381*/ 54430, /*GILLT_s32*//*Label 1379*/ 53410, /*GILLT_s64*//*Label 1380*/ 54183, // Label 1379: @53410 GIM_Try, /*On fail goto*//*Label 1382*/ 54182, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1383*/ 53467, // Rule ID 4248 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4248, GIR_Done, // Label 1383: @53467 GIM_Try, /*On fail goto*//*Label 1384*/ 53518, // Rule ID 4249 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4249, GIR_Done, // Label 1384: @53518 GIM_Try, /*On fail goto*//*Label 1385*/ 53569, // Rule ID 4250 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4250, GIR_Done, // Label 1385: @53569 GIM_Try, /*On fail goto*//*Label 1386*/ 53620, // Rule ID 4251 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4251, GIR_Done, // Label 1386: @53620 GIM_Try, /*On fail goto*//*Label 1387*/ 53671, // Rule ID 4252 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4252, GIR_Done, // Label 1387: @53671 GIM_Try, /*On fail goto*//*Label 1388*/ 53722, // Rule ID 4253 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4253, GIR_Done, // Label 1388: @53722 GIM_Try, /*On fail goto*//*Label 1389*/ 53773, // Rule ID 4254 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4254, GIR_Done, // Label 1389: @53773 GIM_Try, /*On fail goto*//*Label 1390*/ 53824, // Rule ID 4255 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4255, GIR_Done, // Label 1390: @53824 GIM_Try, /*On fail goto*//*Label 1391*/ 53875, // Rule ID 4256 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4256, GIR_Done, // Label 1391: @53875 GIM_Try, /*On fail goto*//*Label 1392*/ 53926, // Rule ID 4257 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4257, GIR_Done, // Label 1392: @53926 GIM_Try, /*On fail goto*//*Label 1393*/ 53977, // Rule ID 4258 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4258, GIR_Done, // Label 1393: @53977 GIM_Try, /*On fail goto*//*Label 1394*/ 54028, // Rule ID 4259 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4259, GIR_Done, // Label 1394: @54028 GIM_Try, /*On fail goto*//*Label 1395*/ 54079, // Rule ID 4260 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4260, GIR_Done, // Label 1395: @54079 GIM_Try, /*On fail goto*//*Label 1396*/ 54130, // Rule ID 4261 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4261, GIR_Done, // Label 1396: @54130 GIM_Try, /*On fail goto*//*Label 1397*/ 54181, // Rule ID 4262 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4262, GIR_Done, // Label 1397: @54181 GIM_Reject, // Label 1382: @54182 GIM_Reject, // Label 1380: @54183 GIM_Try, /*On fail goto*//*Label 1398*/ 54429, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1399*/ 54240, // Rule ID 4243 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4243, GIR_Done, // Label 1399: @54240 GIM_Try, /*On fail goto*//*Label 1400*/ 54287, // Rule ID 4244 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4244, GIR_Done, // Label 1400: @54287 GIM_Try, /*On fail goto*//*Label 1401*/ 54334, // Rule ID 4245 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4245, GIR_Done, // Label 1401: @54334 GIM_Try, /*On fail goto*//*Label 1402*/ 54381, // Rule ID 4246 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4246, GIR_Done, // Label 1402: @54381 GIM_Try, /*On fail goto*//*Label 1403*/ 54428, // Rule ID 4247 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4247, GIR_Done, // Label 1403: @54428 GIM_Reject, // Label 1398: @54429 GIM_Reject, // Label 1381: @54430 GIM_Reject, // Label 26: @54431 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1406*/ 55459, /*GILLT_s32*//*Label 1404*/ 54439, /*GILLT_s64*//*Label 1405*/ 55212, // Label 1404: @54439 GIM_Try, /*On fail goto*//*Label 1407*/ 55211, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1408*/ 54496, // Rule ID 4268 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4268, GIR_Done, // Label 1408: @54496 GIM_Try, /*On fail goto*//*Label 1409*/ 54547, // Rule ID 4269 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4269, GIR_Done, // Label 1409: @54547 GIM_Try, /*On fail goto*//*Label 1410*/ 54598, // Rule ID 4270 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4270, GIR_Done, // Label 1410: @54598 GIM_Try, /*On fail goto*//*Label 1411*/ 54649, // Rule ID 4271 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4271, GIR_Done, // Label 1411: @54649 GIM_Try, /*On fail goto*//*Label 1412*/ 54700, // Rule ID 4272 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4272, GIR_Done, // Label 1412: @54700 GIM_Try, /*On fail goto*//*Label 1413*/ 54751, // Rule ID 4273 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4273, GIR_Done, // Label 1413: @54751 GIM_Try, /*On fail goto*//*Label 1414*/ 54802, // Rule ID 4274 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4274, GIR_Done, // Label 1414: @54802 GIM_Try, /*On fail goto*//*Label 1415*/ 54853, // Rule ID 4275 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4275, GIR_Done, // Label 1415: @54853 GIM_Try, /*On fail goto*//*Label 1416*/ 54904, // Rule ID 4276 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4276, GIR_Done, // Label 1416: @54904 GIM_Try, /*On fail goto*//*Label 1417*/ 54955, // Rule ID 4277 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4277, GIR_Done, // Label 1417: @54955 GIM_Try, /*On fail goto*//*Label 1418*/ 55006, // Rule ID 4278 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4278, GIR_Done, // Label 1418: @55006 GIM_Try, /*On fail goto*//*Label 1419*/ 55057, // Rule ID 4279 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4279, GIR_Done, // Label 1419: @55057 GIM_Try, /*On fail goto*//*Label 1420*/ 55108, // Rule ID 4280 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4280, GIR_Done, // Label 1420: @55108 GIM_Try, /*On fail goto*//*Label 1421*/ 55159, // Rule ID 4281 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4281, GIR_Done, // Label 1421: @55159 GIM_Try, /*On fail goto*//*Label 1422*/ 55210, // Rule ID 4282 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4282, GIR_Done, // Label 1422: @55210 GIM_Reject, // Label 1407: @55211 GIM_Reject, // Label 1405: @55212 GIM_Try, /*On fail goto*//*Label 1423*/ 55458, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1424*/ 55269, // Rule ID 4263 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4263, GIR_Done, // Label 1424: @55269 GIM_Try, /*On fail goto*//*Label 1425*/ 55316, // Rule ID 4264 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4264, GIR_Done, // Label 1425: @55316 GIM_Try, /*On fail goto*//*Label 1426*/ 55363, // Rule ID 4265 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4265, GIR_Done, // Label 1426: @55363 GIM_Try, /*On fail goto*//*Label 1427*/ 55410, // Rule ID 4266 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4266, GIR_Done, // Label 1427: @55410 GIM_Try, /*On fail goto*//*Label 1428*/ 55457, // Rule ID 4267 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4267, GIR_Done, // Label 1428: @55457 GIM_Reject, // Label 1423: @55458 GIM_Reject, // Label 1406: @55459 GIM_Reject, // Label 27: @55460 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1431*/ 56488, /*GILLT_s32*//*Label 1429*/ 55468, /*GILLT_s64*//*Label 1430*/ 56241, // Label 1429: @55468 GIM_Try, /*On fail goto*//*Label 1432*/ 56240, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1433*/ 55525, // Rule ID 4288 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4288, GIR_Done, // Label 1433: @55525 GIM_Try, /*On fail goto*//*Label 1434*/ 55576, // Rule ID 4289 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4289, GIR_Done, // Label 1434: @55576 GIM_Try, /*On fail goto*//*Label 1435*/ 55627, // Rule ID 4290 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4290, GIR_Done, // Label 1435: @55627 GIM_Try, /*On fail goto*//*Label 1436*/ 55678, // Rule ID 4291 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4291, GIR_Done, // Label 1436: @55678 GIM_Try, /*On fail goto*//*Label 1437*/ 55729, // Rule ID 4292 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4292, GIR_Done, // Label 1437: @55729 GIM_Try, /*On fail goto*//*Label 1438*/ 55780, // Rule ID 4293 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4293, GIR_Done, // Label 1438: @55780 GIM_Try, /*On fail goto*//*Label 1439*/ 55831, // Rule ID 4294 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4294, GIR_Done, // Label 1439: @55831 GIM_Try, /*On fail goto*//*Label 1440*/ 55882, // Rule ID 4295 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4295, GIR_Done, // Label 1440: @55882 GIM_Try, /*On fail goto*//*Label 1441*/ 55933, // Rule ID 4296 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4296, GIR_Done, // Label 1441: @55933 GIM_Try, /*On fail goto*//*Label 1442*/ 55984, // Rule ID 4297 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4297, GIR_Done, // Label 1442: @55984 GIM_Try, /*On fail goto*//*Label 1443*/ 56035, // Rule ID 4298 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4298, GIR_Done, // Label 1443: @56035 GIM_Try, /*On fail goto*//*Label 1444*/ 56086, // Rule ID 4299 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4299, GIR_Done, // Label 1444: @56086 GIM_Try, /*On fail goto*//*Label 1445*/ 56137, // Rule ID 4300 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4300, GIR_Done, // Label 1445: @56137 GIM_Try, /*On fail goto*//*Label 1446*/ 56188, // Rule ID 4301 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4301, GIR_Done, // Label 1446: @56188 GIM_Try, /*On fail goto*//*Label 1447*/ 56239, // Rule ID 4302 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<><> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4302, GIR_Done, // Label 1447: @56239 GIM_Reject, // Label 1432: @56240 GIM_Reject, // Label 1430: @56241 GIM_Try, /*On fail goto*//*Label 1448*/ 56487, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, GIM_Try, /*On fail goto*//*Label 1449*/ 56298, // Rule ID 4283 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4283, GIR_Done, // Label 1449: @56298 GIM_Try, /*On fail goto*//*Label 1450*/ 56345, // Rule ID 4284 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4284, GIR_Done, // Label 1450: @56345 GIM_Try, /*On fail goto*//*Label 1451*/ 56392, // Rule ID 4285 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4285, GIR_Done, // Label 1451: @56392 GIM_Try, /*On fail goto*//*Label 1452*/ 56439, // Rule ID 4286 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4286, GIR_Done, // Label 1452: @56439 GIM_Try, /*On fail goto*//*Label 1453*/ 56486, // Rule ID 4287 // GIM_CheckFeatures, GIFBS_HasLSE, GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<><> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4287, GIR_Done, // Label 1453: @56486 GIM_Reject, // Label 1448: @56487 GIM_Reject, // Label 1431: @56488 GIM_Reject, // Label 28: @56489 GIM_Try, /*On fail goto*//*Label 1454*/ 56517, // Rule ID 4071 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (DMB 9:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_AddImm, /*InsnID*/0, /*Imm*/9, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4071, GIR_Done, // Label 1454: @56517 GIM_Try, /*On fail goto*//*Label 1455*/ 56540, // Rule ID 4072 // // MIs[0] Operand 0 GIM_CheckIsImm, /*MI*/0, /*Op*/0, // MIs[0] Operand 1 GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (DMB 11:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_AddImm, /*InsnID*/0, /*Imm*/11, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4072, GIR_Done, // Label 1455: @56540 GIM_Reject, // Label 29: @56541 GIM_Try, /*On fail goto*//*Label 1456*/ 56573, // Rule ID 2327 // GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_get_fpcr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 297:{ *:[iPTR] }) => (MRS:{ *:[i64] } 55840:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/55840, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2327, GIR_Done, // Label 1456: @56573 GIM_Try, /*On fail goto*//*Label 1457*/ 65565, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 1458*/ 56666, // Rule ID 3671 // GIM_CheckFeatures, GIFBS_HasFuseAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 283:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 281:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3671, GIR_Done, // Label 1458: @56666 GIM_Try, /*On fail goto*//*Label 1459*/ 56754, // Rule ID 3672 // GIM_CheckFeatures, GIFBS_HasFuseAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 282:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 280:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3672, GIR_Done, // Label 1459: @56754 GIM_Try, /*On fail goto*//*Label 1460*/ 56792, // Rule ID 1953 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, // (intrinsic_wo_chain:{ *:[i64] } 516:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTB_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1953, GIR_Done, // Label 1460: @56792 GIM_Try, /*On fail goto*//*Label 1461*/ 56830, // Rule ID 5002 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cnth, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, // (intrinsic_wo_chain:{ *:[i64] } 518:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTH_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5002, GIR_Done, // Label 1461: @56830 GIM_Try, /*On fail goto*//*Label 1462*/ 56868, // Rule ID 5005 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, // (intrinsic_wo_chain:{ *:[i64] } 520:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTW_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5005, GIR_Done, // Label 1462: @56868 GIM_Try, /*On fail goto*//*Label 1463*/ 56906, // Rule ID 5008 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] pattern GIM_CheckIsImm, /*MI*/0, /*Op*/2, // (intrinsic_wo_chain:{ *:[i64] } 517:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$pattern) => (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<>:$pattern, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTD_XPiI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5008, GIR_Done, // Label 1463: @56906 GIM_Try, /*On fail goto*//*Label 1464*/ 56946, // Rule ID 43 // GIM_CheckFeatures, GIFBS_HasFPARMv8_HasJS, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_fjcvtzs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 296:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FJCVTZS:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FJCVTZS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 43, GIR_Done, // Label 1464: @56946 GIM_Try, /*On fail goto*//*Label 1465*/ 56986, // Rule ID 310 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 317:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 310, GIR_Done, // Label 1465: @56986 GIM_Try, /*On fail goto*//*Label 1466*/ 57026, // Rule ID 311 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 317:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 311, GIR_Done, // Label 1466: @57026 GIM_Try, /*On fail goto*//*Label 1467*/ 57066, // Rule ID 312 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 317:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 312, GIR_Done, // Label 1467: @57066 GIM_Try, /*On fail goto*//*Label 1468*/ 57106, // Rule ID 313 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 317:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 313, GIR_Done, // Label 1468: @57106 GIM_Try, /*On fail goto*//*Label 1469*/ 57146, // Rule ID 314 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 317:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 314, GIR_Done, // Label 1469: @57146 GIM_Try, /*On fail goto*//*Label 1470*/ 57186, // Rule ID 315 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 317:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 315, GIR_Done, // Label 1470: @57186 GIM_Try, /*On fail goto*//*Label 1471*/ 57226, // Rule ID 316 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 318:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 316, GIR_Done, // Label 1471: @57226 GIM_Try, /*On fail goto*//*Label 1472*/ 57266, // Rule ID 317 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 318:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 317, GIR_Done, // Label 1472: @57266 GIM_Try, /*On fail goto*//*Label 1473*/ 57306, // Rule ID 318 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 318:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 318, GIR_Done, // Label 1473: @57306 GIM_Try, /*On fail goto*//*Label 1474*/ 57346, // Rule ID 319 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 318:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 319, GIR_Done, // Label 1474: @57346 GIM_Try, /*On fail goto*//*Label 1475*/ 57386, // Rule ID 320 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 318:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 320, GIR_Done, // Label 1475: @57386 GIM_Try, /*On fail goto*//*Label 1476*/ 57426, // Rule ID 321 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 318:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 321, GIR_Done, // Label 1476: @57426 GIM_Try, /*On fail goto*//*Label 1477*/ 57466, // Rule ID 322 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 319:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 322, GIR_Done, // Label 1477: @57466 GIM_Try, /*On fail goto*//*Label 1478*/ 57506, // Rule ID 323 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 319:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 323, GIR_Done, // Label 1478: @57506 GIM_Try, /*On fail goto*//*Label 1479*/ 57546, // Rule ID 324 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 319:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 324, GIR_Done, // Label 1479: @57546 GIM_Try, /*On fail goto*//*Label 1480*/ 57586, // Rule ID 325 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 319:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 325, GIR_Done, // Label 1480: @57586 GIM_Try, /*On fail goto*//*Label 1481*/ 57626, // Rule ID 326 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 319:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 326, GIR_Done, // Label 1481: @57626 GIM_Try, /*On fail goto*//*Label 1482*/ 57666, // Rule ID 327 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 319:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 327, GIR_Done, // Label 1482: @57666 GIM_Try, /*On fail goto*//*Label 1483*/ 57706, // Rule ID 328 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 320:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 328, GIR_Done, // Label 1483: @57706 GIM_Try, /*On fail goto*//*Label 1484*/ 57746, // Rule ID 329 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 320:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 329, GIR_Done, // Label 1484: @57746 GIM_Try, /*On fail goto*//*Label 1485*/ 57786, // Rule ID 330 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 320:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 330, GIR_Done, // Label 1485: @57786 GIM_Try, /*On fail goto*//*Label 1486*/ 57826, // Rule ID 331 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 320:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 331, GIR_Done, // Label 1486: @57826 GIM_Try, /*On fail goto*//*Label 1487*/ 57866, // Rule ID 332 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 320:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 332, GIR_Done, // Label 1487: @57866 GIM_Try, /*On fail goto*//*Label 1488*/ 57906, // Rule ID 333 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 320:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 333, GIR_Done, // Label 1488: @57906 GIM_Try, /*On fail goto*//*Label 1489*/ 57946, // Rule ID 334 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 321:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 334, GIR_Done, // Label 1489: @57946 GIM_Try, /*On fail goto*//*Label 1490*/ 57986, // Rule ID 335 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 321:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 335, GIR_Done, // Label 1490: @57986 GIM_Try, /*On fail goto*//*Label 1491*/ 58026, // Rule ID 336 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 321:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 336, GIR_Done, // Label 1491: @58026 GIM_Try, /*On fail goto*//*Label 1492*/ 58066, // Rule ID 337 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 321:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 337, GIR_Done, // Label 1492: @58066 GIM_Try, /*On fail goto*//*Label 1493*/ 58106, // Rule ID 338 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 321:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 338, GIR_Done, // Label 1493: @58106 GIM_Try, /*On fail goto*//*Label 1494*/ 58146, // Rule ID 339 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 321:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 339, GIR_Done, // Label 1494: @58146 GIM_Try, /*On fail goto*//*Label 1495*/ 58186, // Rule ID 340 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 322:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 340, GIR_Done, // Label 1495: @58186 GIM_Try, /*On fail goto*//*Label 1496*/ 58226, // Rule ID 341 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 322:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 341, GIR_Done, // Label 1496: @58226 GIM_Try, /*On fail goto*//*Label 1497*/ 58266, // Rule ID 342 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 322:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 342, GIR_Done, // Label 1497: @58266 GIM_Try, /*On fail goto*//*Label 1498*/ 58306, // Rule ID 343 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 322:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 343, GIR_Done, // Label 1498: @58306 GIM_Try, /*On fail goto*//*Label 1499*/ 58346, // Rule ID 344 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 322:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 344, GIR_Done, // Label 1499: @58346 GIM_Try, /*On fail goto*//*Label 1500*/ 58386, // Rule ID 345 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 322:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 345, GIR_Done, // Label 1500: @58386 GIM_Try, /*On fail goto*//*Label 1501*/ 58426, // Rule ID 346 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 323:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 346, GIR_Done, // Label 1501: @58426 GIM_Try, /*On fail goto*//*Label 1502*/ 58466, // Rule ID 347 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 323:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 347, GIR_Done, // Label 1502: @58466 GIM_Try, /*On fail goto*//*Label 1503*/ 58506, // Rule ID 348 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 323:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 348, GIR_Done, // Label 1503: @58506 GIM_Try, /*On fail goto*//*Label 1504*/ 58546, // Rule ID 349 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 323:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 349, GIR_Done, // Label 1504: @58546 GIM_Try, /*On fail goto*//*Label 1505*/ 58586, // Rule ID 350 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 323:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 350, GIR_Done, // Label 1505: @58586 GIM_Try, /*On fail goto*//*Label 1506*/ 58626, // Rule ID 351 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 323:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 351, GIR_Done, // Label 1506: @58626 GIM_Try, /*On fail goto*//*Label 1507*/ 58666, // Rule ID 352 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 324:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 352, GIR_Done, // Label 1507: @58666 GIM_Try, /*On fail goto*//*Label 1508*/ 58706, // Rule ID 353 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 324:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 353, GIR_Done, // Label 1508: @58706 GIM_Try, /*On fail goto*//*Label 1509*/ 58746, // Rule ID 354 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 324:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 354, GIR_Done, // Label 1509: @58746 GIM_Try, /*On fail goto*//*Label 1510*/ 58786, // Rule ID 355 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 324:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 355, GIR_Done, // Label 1510: @58786 GIM_Try, /*On fail goto*//*Label 1511*/ 58826, // Rule ID 356 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 324:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 356, GIR_Done, // Label 1511: @58826 GIM_Try, /*On fail goto*//*Label 1512*/ 58866, // Rule ID 357 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 324:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 357, GIR_Done, // Label 1512: @58866 GIM_Try, /*On fail goto*//*Label 1513*/ 58906, // Rule ID 481 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 348:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNHr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 481, GIR_Done, // Label 1513: @58906 GIM_Try, /*On fail goto*//*Label 1514*/ 58946, // Rule ID 482 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 348:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 482, GIR_Done, // Label 1514: @58946 GIM_Try, /*On fail goto*//*Label 1515*/ 58986, // Rule ID 483 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 348:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 483, GIR_Done, // Label 1515: @58986 GIM_Try, /*On fail goto*//*Label 1516*/ 59026, // Rule ID 579 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 311:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 579, GIR_Done, // Label 1516: @59026 GIM_Try, /*On fail goto*//*Label 1517*/ 59066, // Rule ID 580 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 311:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 580, GIR_Done, // Label 1517: @59066 GIM_Try, /*On fail goto*//*Label 1518*/ 59106, // Rule ID 581 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 311:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 581, GIR_Done, // Label 1518: @59106 GIM_Try, /*On fail goto*//*Label 1519*/ 59146, // Rule ID 582 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 311:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 582, GIR_Done, // Label 1519: @59146 GIM_Try, /*On fail goto*//*Label 1520*/ 59186, // Rule ID 583 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 311:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 583, GIR_Done, // Label 1520: @59186 GIM_Try, /*On fail goto*//*Label 1521*/ 59226, // Rule ID 584 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 311:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 584, GIR_Done, // Label 1521: @59226 GIM_Try, /*On fail goto*//*Label 1522*/ 59266, // Rule ID 658 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 317:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 658, GIR_Done, // Label 1522: @59266 GIM_Try, /*On fail goto*//*Label 1523*/ 59306, // Rule ID 659 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 317:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 659, GIR_Done, // Label 1523: @59306 GIM_Try, /*On fail goto*//*Label 1524*/ 59346, // Rule ID 660 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 317:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 660, GIR_Done, // Label 1524: @59346 GIM_Try, /*On fail goto*//*Label 1525*/ 59386, // Rule ID 661 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 317:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 661, GIR_Done, // Label 1525: @59386 GIM_Try, /*On fail goto*//*Label 1526*/ 59426, // Rule ID 662 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 317:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 662, GIR_Done, // Label 1526: @59426 GIM_Try, /*On fail goto*//*Label 1527*/ 59466, // Rule ID 663 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 318:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 663, GIR_Done, // Label 1527: @59466 GIM_Try, /*On fail goto*//*Label 1528*/ 59506, // Rule ID 664 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 318:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 664, GIR_Done, // Label 1528: @59506 GIM_Try, /*On fail goto*//*Label 1529*/ 59546, // Rule ID 665 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 318:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 665, GIR_Done, // Label 1529: @59546 GIM_Try, /*On fail goto*//*Label 1530*/ 59586, // Rule ID 666 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 318:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 666, GIR_Done, // Label 1530: @59586 GIM_Try, /*On fail goto*//*Label 1531*/ 59626, // Rule ID 667 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 318:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 667, GIR_Done, // Label 1531: @59626 GIM_Try, /*On fail goto*//*Label 1532*/ 59666, // Rule ID 668 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 319:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 668, GIR_Done, // Label 1532: @59666 GIM_Try, /*On fail goto*//*Label 1533*/ 59706, // Rule ID 669 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 319:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 669, GIR_Done, // Label 1533: @59706 GIM_Try, /*On fail goto*//*Label 1534*/ 59746, // Rule ID 670 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 319:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 670, GIR_Done, // Label 1534: @59746 GIM_Try, /*On fail goto*//*Label 1535*/ 59786, // Rule ID 671 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 319:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 671, GIR_Done, // Label 1535: @59786 GIM_Try, /*On fail goto*//*Label 1536*/ 59826, // Rule ID 672 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 319:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 672, GIR_Done, // Label 1536: @59826 GIM_Try, /*On fail goto*//*Label 1537*/ 59866, // Rule ID 673 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 320:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 673, GIR_Done, // Label 1537: @59866 GIM_Try, /*On fail goto*//*Label 1538*/ 59906, // Rule ID 674 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 320:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 674, GIR_Done, // Label 1538: @59906 GIM_Try, /*On fail goto*//*Label 1539*/ 59946, // Rule ID 675 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 320:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 675, GIR_Done, // Label 1539: @59946 GIM_Try, /*On fail goto*//*Label 1540*/ 59986, // Rule ID 676 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 320:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 676, GIR_Done, // Label 1540: @59986 GIM_Try, /*On fail goto*//*Label 1541*/ 60026, // Rule ID 677 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 320:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 677, GIR_Done, // Label 1541: @60026 GIM_Try, /*On fail goto*//*Label 1542*/ 60066, // Rule ID 678 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 321:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 678, GIR_Done, // Label 1542: @60066 GIM_Try, /*On fail goto*//*Label 1543*/ 60106, // Rule ID 679 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 321:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 679, GIR_Done, // Label 1543: @60106 GIM_Try, /*On fail goto*//*Label 1544*/ 60146, // Rule ID 680 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 321:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 680, GIR_Done, // Label 1544: @60146 GIM_Try, /*On fail goto*//*Label 1545*/ 60186, // Rule ID 681 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 321:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 681, GIR_Done, // Label 1545: @60186 GIM_Try, /*On fail goto*//*Label 1546*/ 60226, // Rule ID 682 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 321:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 682, GIR_Done, // Label 1546: @60226 GIM_Try, /*On fail goto*//*Label 1547*/ 60266, // Rule ID 683 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 322:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 683, GIR_Done, // Label 1547: @60266 GIM_Try, /*On fail goto*//*Label 1548*/ 60306, // Rule ID 684 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 322:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 684, GIR_Done, // Label 1548: @60306 GIM_Try, /*On fail goto*//*Label 1549*/ 60346, // Rule ID 685 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 322:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 685, GIR_Done, // Label 1549: @60346 GIM_Try, /*On fail goto*//*Label 1550*/ 60386, // Rule ID 686 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 322:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 686, GIR_Done, // Label 1550: @60386 GIM_Try, /*On fail goto*//*Label 1551*/ 60426, // Rule ID 687 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 322:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 687, GIR_Done, // Label 1551: @60426 GIM_Try, /*On fail goto*//*Label 1552*/ 60466, // Rule ID 688 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 323:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 688, GIR_Done, // Label 1552: @60466 GIM_Try, /*On fail goto*//*Label 1553*/ 60506, // Rule ID 689 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 323:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 689, GIR_Done, // Label 1553: @60506 GIM_Try, /*On fail goto*//*Label 1554*/ 60546, // Rule ID 690 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 323:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 690, GIR_Done, // Label 1554: @60546 GIM_Try, /*On fail goto*//*Label 1555*/ 60586, // Rule ID 691 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 323:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 691, GIR_Done, // Label 1555: @60586 GIM_Try, /*On fail goto*//*Label 1556*/ 60626, // Rule ID 692 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 323:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 692, GIR_Done, // Label 1556: @60626 GIM_Try, /*On fail goto*//*Label 1557*/ 60666, // Rule ID 693 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 324:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 693, GIR_Done, // Label 1557: @60666 GIM_Try, /*On fail goto*//*Label 1558*/ 60706, // Rule ID 694 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 324:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 694, GIR_Done, // Label 1558: @60706 GIM_Try, /*On fail goto*//*Label 1559*/ 60746, // Rule ID 695 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 324:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 695, GIR_Done, // Label 1559: @60746 GIM_Try, /*On fail goto*//*Label 1560*/ 60786, // Rule ID 696 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 324:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 696, GIR_Done, // Label 1560: @60786 GIM_Try, /*On fail goto*//*Label 1561*/ 60826, // Rule ID 697 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 324:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 697, GIR_Done, // Label 1561: @60826 GIM_Try, /*On fail goto*//*Label 1562*/ 60866, // Rule ID 698 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 325:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 698, GIR_Done, // Label 1562: @60866 GIM_Try, /*On fail goto*//*Label 1563*/ 60906, // Rule ID 714 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 345:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 714, GIR_Done, // Label 1563: @60906 GIM_Try, /*On fail goto*//*Label 1564*/ 60946, // Rule ID 715 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 345:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 715, GIR_Done, // Label 1564: @60946 GIM_Try, /*On fail goto*//*Label 1565*/ 60986, // Rule ID 716 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 345:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 716, GIR_Done, // Label 1565: @60986 GIM_Try, /*On fail goto*//*Label 1566*/ 61026, // Rule ID 717 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 345:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 717, GIR_Done, // Label 1566: @61026 GIM_Try, /*On fail goto*//*Label 1567*/ 61066, // Rule ID 718 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 345:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 718, GIR_Done, // Label 1567: @61066 GIM_Try, /*On fail goto*//*Label 1568*/ 61106, // Rule ID 734 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 348:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 734, GIR_Done, // Label 1568: @61106 GIM_Try, /*On fail goto*//*Label 1569*/ 61146, // Rule ID 735 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 348:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 735, GIR_Done, // Label 1569: @61146 GIM_Try, /*On fail goto*//*Label 1570*/ 61186, // Rule ID 736 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 348:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 736, GIR_Done, // Label 1570: @61186 GIM_Try, /*On fail goto*//*Label 1571*/ 61226, // Rule ID 737 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 348:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 737, GIR_Done, // Label 1571: @61226 GIM_Try, /*On fail goto*//*Label 1572*/ 61266, // Rule ID 738 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 348:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 738, GIR_Done, // Label 1572: @61266 GIM_Try, /*On fail goto*//*Label 1573*/ 61306, // Rule ID 754 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 349:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 754, GIR_Done, // Label 1573: @61306 GIM_Try, /*On fail goto*//*Label 1574*/ 61346, // Rule ID 755 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 349:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 755, GIR_Done, // Label 1574: @61346 GIM_Try, /*On fail goto*//*Label 1575*/ 61386, // Rule ID 756 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 349:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 756, GIR_Done, // Label 1575: @61386 GIM_Try, /*On fail goto*//*Label 1576*/ 61426, // Rule ID 757 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 349:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 757, GIR_Done, // Label 1576: @61426 GIM_Try, /*On fail goto*//*Label 1577*/ 61466, // Rule ID 758 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 349:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 758, GIR_Done, // Label 1577: @61466 GIM_Try, /*On fail goto*//*Label 1578*/ 61506, // Rule ID 773 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 367:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 773, GIR_Done, // Label 1578: @61506 GIM_Try, /*On fail goto*//*Label 1579*/ 61546, // Rule ID 774 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 367:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 774, GIR_Done, // Label 1579: @61546 GIM_Try, /*On fail goto*//*Label 1580*/ 61586, // Rule ID 793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 371:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 793, GIR_Done, // Label 1580: @61586 GIM_Try, /*On fail goto*//*Label 1581*/ 61626, // Rule ID 794 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 371:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 794, GIR_Done, // Label 1581: @61626 GIM_Try, /*On fail goto*//*Label 1582*/ 61666, // Rule ID 795 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 371:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 795, GIR_Done, // Label 1582: @61666 GIM_Try, /*On fail goto*//*Label 1583*/ 61706, // Rule ID 796 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 371:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 796, GIR_Done, // Label 1583: @61706 GIM_Try, /*On fail goto*//*Label 1584*/ 61746, // Rule ID 797 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 371:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 797, GIR_Done, // Label 1584: @61746 GIM_Try, /*On fail goto*//*Label 1585*/ 61786, // Rule ID 798 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 371:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 798, GIR_Done, // Label 1585: @61786 GIM_Try, /*On fail goto*//*Label 1586*/ 61826, // Rule ID 804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 388:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 804, GIR_Done, // Label 1586: @61826 GIM_Try, /*On fail goto*//*Label 1587*/ 61866, // Rule ID 805 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 388:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 805, GIR_Done, // Label 1587: @61866 GIM_Try, /*On fail goto*//*Label 1588*/ 61906, // Rule ID 806 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 388:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 806, GIR_Done, // Label 1588: @61906 GIM_Try, /*On fail goto*//*Label 1589*/ 61946, // Rule ID 807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 388:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 807, GIR_Done, // Label 1589: @61946 GIM_Try, /*On fail goto*//*Label 1590*/ 61986, // Rule ID 808 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 388:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 808, GIR_Done, // Label 1590: @61986 GIM_Try, /*On fail goto*//*Label 1591*/ 62026, // Rule ID 809 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 388:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 809, GIR_Done, // Label 1591: @62026 GIM_Try, /*On fail goto*//*Label 1592*/ 62066, // Rule ID 810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 388:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 810, GIR_Done, // Label 1592: @62066 GIM_Try, /*On fail goto*//*Label 1593*/ 62106, // Rule ID 811 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 393:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 811, GIR_Done, // Label 1593: @62106 GIM_Try, /*On fail goto*//*Label 1594*/ 62146, // Rule ID 812 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 393:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 812, GIR_Done, // Label 1594: @62146 GIM_Try, /*On fail goto*//*Label 1595*/ 62186, // Rule ID 813 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 393:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 813, GIR_Done, // Label 1595: @62186 GIM_Try, /*On fail goto*//*Label 1596*/ 62226, // Rule ID 814 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 393:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 814, GIR_Done, // Label 1596: @62226 GIM_Try, /*On fail goto*//*Label 1597*/ 62266, // Rule ID 815 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 393:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 815, GIR_Done, // Label 1597: @62266 GIM_Try, /*On fail goto*//*Label 1598*/ 62306, // Rule ID 816 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 393:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 816, GIR_Done, // Label 1598: @62306 GIM_Try, /*On fail goto*//*Label 1599*/ 62346, // Rule ID 817 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 393:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 817, GIR_Done, // Label 1599: @62346 GIM_Try, /*On fail goto*//*Label 1600*/ 62386, // Rule ID 818 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 403:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 818, GIR_Done, // Label 1600: @62386 GIM_Try, /*On fail goto*//*Label 1601*/ 62426, // Rule ID 819 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 403:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 819, GIR_Done, // Label 1601: @62426 GIM_Try, /*On fail goto*//*Label 1602*/ 62466, // Rule ID 820 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 403:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 820, GIR_Done, // Label 1602: @62466 GIM_Try, /*On fail goto*//*Label 1603*/ 62506, // Rule ID 821 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 404:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 821, GIR_Done, // Label 1603: @62506 GIM_Try, /*On fail goto*//*Label 1604*/ 62546, // Rule ID 822 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 404:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 822, GIR_Done, // Label 1604: @62546 GIM_Try, /*On fail goto*//*Label 1605*/ 62586, // Rule ID 823 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 404:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 823, GIR_Done, // Label 1605: @62586 GIM_Try, /*On fail goto*//*Label 1606*/ 62626, // Rule ID 837 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 429:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i8_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 837, GIR_Done, // Label 1606: @62626 GIM_Try, /*On fail goto*//*Label 1607*/ 62666, // Rule ID 838 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 429:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv16i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 838, GIR_Done, // Label 1607: @62666 GIM_Try, /*On fail goto*//*Label 1608*/ 62706, // Rule ID 839 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 429:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i16_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 839, GIR_Done, // Label 1608: @62706 GIM_Try, /*On fail goto*//*Label 1609*/ 62746, // Rule ID 840 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 429:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 840, GIR_Done, // Label 1609: @62746 GIM_Try, /*On fail goto*//*Label 1610*/ 62786, // Rule ID 841 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 429:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv2i32_v1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 841, GIR_Done, // Label 1610: @62786 GIM_Try, /*On fail goto*//*Label 1611*/ 62826, // Rule ID 842 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 429:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 842, GIR_Done, // Label 1611: @62826 GIM_Try, /*On fail goto*//*Label 1612*/ 62866, // Rule ID 848 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 448:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 848, GIR_Done, // Label 1612: @62866 GIM_Try, /*On fail goto*//*Label 1613*/ 62906, // Rule ID 849 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 448:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 849, GIR_Done, // Label 1613: @62906 GIM_Try, /*On fail goto*//*Label 1614*/ 62946, // Rule ID 850 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 448:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 850, GIR_Done, // Label 1614: @62946 GIM_Try, /*On fail goto*//*Label 1615*/ 62986, // Rule ID 851 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 449:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 851, GIR_Done, // Label 1615: @62986 GIM_Try, /*On fail goto*//*Label 1616*/ 63026, // Rule ID 852 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 449:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 852, GIR_Done, // Label 1616: @63026 GIM_Try, /*On fail goto*//*Label 1617*/ 63066, // Rule ID 853 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 452:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 853, GIR_Done, // Label 1617: @63066 GIM_Try, /*On fail goto*//*Label 1618*/ 63106, // Rule ID 854 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 452:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 854, GIR_Done, // Label 1618: @63106 GIM_Try, /*On fail goto*//*Label 1619*/ 63146, // Rule ID 1324 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fcvtxn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 471:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1324, GIR_Done, // Label 1619: @63146 GIM_Try, /*On fail goto*//*Label 1620*/ 63186, // Rule ID 1329 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 388:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1329, GIR_Done, // Label 1620: @63186 GIM_Try, /*On fail goto*//*Label 1621*/ 63226, // Rule ID 1330 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 388:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1330, GIR_Done, // Label 1621: @63226 GIM_Try, /*On fail goto*//*Label 1622*/ 63266, // Rule ID 1331 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 393:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1331, GIR_Done, // Label 1622: @63266 GIM_Try, /*On fail goto*//*Label 1623*/ 63306, // Rule ID 1332 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 393:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1332, GIR_Done, // Label 1623: @63306 GIM_Try, /*On fail goto*//*Label 1624*/ 63346, // Rule ID 1333 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1333, GIR_Done, // Label 1624: @63346 GIM_Try, /*On fail goto*//*Label 1625*/ 63386, // Rule ID 1334 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 375:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTUNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1334, GIR_Done, // Label 1625: @63386 GIM_Try, /*On fail goto*//*Label 1626*/ 63426, // Rule ID 1340 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_uqxtn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 376:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (UQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1340, GIR_Done, // Label 1626: @63426 GIM_Try, /*On fail goto*//*Label 1627*/ 63466, // Rule ID 1540 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 331:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1540, GIR_Done, // Label 1627: @63466 GIM_Try, /*On fail goto*//*Label 1628*/ 63506, // Rule ID 1541 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 331:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1541, GIR_Done, // Label 1628: @63506 GIM_Try, /*On fail goto*//*Label 1629*/ 63546, // Rule ID 1542 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 331:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1542, GIR_Done, // Label 1629: @63546 GIM_Try, /*On fail goto*//*Label 1630*/ 63586, // Rule ID 1543 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 333:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1543, GIR_Done, // Label 1630: @63586 GIM_Try, /*On fail goto*//*Label 1631*/ 63626, // Rule ID 1544 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 333:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1544, GIR_Done, // Label 1631: @63626 GIM_Try, /*On fail goto*//*Label 1632*/ 63666, // Rule ID 1545 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 333:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1545, GIR_Done, // Label 1632: @63666 GIM_Try, /*On fail goto*//*Label 1633*/ 63706, // Rule ID 1546 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 337:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1546, GIR_Done, // Label 1633: @63706 GIM_Try, /*On fail goto*//*Label 1634*/ 63746, // Rule ID 1547 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 337:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1547, GIR_Done, // Label 1634: @63746 GIM_Try, /*On fail goto*//*Label 1635*/ 63786, // Rule ID 1548 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 337:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1548, GIR_Done, // Label 1635: @63786 GIM_Try, /*On fail goto*//*Label 1636*/ 63826, // Rule ID 1549 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 339:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1549, GIR_Done, // Label 1636: @63826 GIM_Try, /*On fail goto*//*Label 1637*/ 63866, // Rule ID 1550 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 339:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv8i16v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1550, GIR_Done, // Label 1637: @63866 GIM_Try, /*On fail goto*//*Label 1638*/ 63906, // Rule ID 1551 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 339:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i32v, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1551, GIR_Done, // Label 1638: @63906 GIM_Try, /*On fail goto*//*Label 1639*/ 63946, // Rule ID 1828 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 283:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1828, GIR_Done, // Label 1639: @63946 GIM_Try, /*On fail goto*//*Label 1640*/ 63986, // Rule ID 1829 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 282:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1829, GIR_Done, // Label 1640: @63986 GIM_Try, /*On fail goto*//*Label 1641*/ 64026, // Rule ID 1837 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 285:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Hrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1837, GIR_Done, // Label 1641: @64026 GIM_Try, /*On fail goto*//*Label 1642*/ 64066, // Rule ID 1893 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 388:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1893, GIR_Done, // Label 1642: @64066 GIM_Try, /*On fail goto*//*Label 1643*/ 64104, // Rule ID 2410 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_cls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 270:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2410, GIR_Done, // Label 1643: @64104 GIM_Try, /*On fail goto*//*Label 1644*/ 64142, // Rule ID 2796 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 348:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINTNDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2796, GIR_Done, // Label 1644: @64142 GIM_Try, /*On fail goto*//*Label 1645*/ 64180, // Rule ID 2827 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvthf2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 464:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2827, GIR_Done, // Label 1645: @64180 GIM_Try, /*On fail goto*//*Label 1646*/ 64218, // Rule ID 2831 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 461:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2831, GIR_Done, // Label 1646: @64218 GIM_Try, /*On fail goto*//*Label 1647*/ 64258, // Rule ID 3004 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 393:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3004, GIR_Done, // Label 1647: @64258 GIM_Try, /*On fail goto*//*Label 1648*/ 64296, // Rule ID 3007 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 317:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3007, GIR_Done, // Label 1648: @64296 GIM_Try, /*On fail goto*//*Label 1649*/ 64334, // Rule ID 3008 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 318:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3008, GIR_Done, // Label 1649: @64334 GIM_Try, /*On fail goto*//*Label 1650*/ 64372, // Rule ID 3009 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 319:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3009, GIR_Done, // Label 1650: @64372 GIM_Try, /*On fail goto*//*Label 1651*/ 64410, // Rule ID 3010 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 320:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3010, GIR_Done, // Label 1651: @64410 GIM_Try, /*On fail goto*//*Label 1652*/ 64448, // Rule ID 3011 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 321:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3011, GIR_Done, // Label 1652: @64448 GIM_Try, /*On fail goto*//*Label 1653*/ 64486, // Rule ID 3012 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 322:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3012, GIR_Done, // Label 1653: @64486 GIM_Try, /*On fail goto*//*Label 1654*/ 64524, // Rule ID 3013 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 323:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3013, GIR_Done, // Label 1654: @64524 GIM_Try, /*On fail goto*//*Label 1655*/ 64562, // Rule ID 3014 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 324:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3014, GIR_Done, // Label 1655: @64562 GIM_Try, /*On fail goto*//*Label 1656*/ 64600, // Rule ID 3015 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 345:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3015, GIR_Done, // Label 1656: @64600 GIM_Try, /*On fail goto*//*Label 1657*/ 64638, // Rule ID 3016 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 345:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3016, GIR_Done, // Label 1657: @64638 GIM_Try, /*On fail goto*//*Label 1658*/ 64676, // Rule ID 3017 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 345:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3017, GIR_Done, // Label 1658: @64676 GIM_Try, /*On fail goto*//*Label 1659*/ 64714, // Rule ID 3018 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 345:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3018, GIR_Done, // Label 1659: @64714 GIM_Try, /*On fail goto*//*Label 1660*/ 64752, // Rule ID 3030 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 347:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3030, GIR_Done, // Label 1660: @64752 GIM_Try, /*On fail goto*//*Label 1661*/ 64790, // Rule ID 3031 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 347:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3031, GIR_Done, // Label 1661: @64790 GIM_Try, /*On fail goto*//*Label 1662*/ 64828, // Rule ID 3032 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 347:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3032, GIR_Done, // Label 1662: @64828 GIM_Try, /*On fail goto*//*Label 1663*/ 64866, // Rule ID 3033 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 349:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3033, GIR_Done, // Label 1663: @64866 GIM_Try, /*On fail goto*//*Label 1664*/ 64904, // Rule ID 3034 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 349:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3034, GIR_Done, // Label 1664: @64904 GIM_Try, /*On fail goto*//*Label 1665*/ 64942, // Rule ID 3035 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 349:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3035, GIR_Done, // Label 1665: @64942 GIM_Try, /*On fail goto*//*Label 1666*/ 64980, // Rule ID 3036 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 349:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3036, GIR_Done, // Label 1666: @64980 GIM_Try, /*On fail goto*//*Label 1667*/ 65018, // Rule ID 3181 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 316:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3181, GIR_Done, // Label 1667: @65018 GIM_Try, /*On fail goto*//*Label 1668*/ 65056, // Rule ID 3183 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 316:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3183, GIR_Done, // Label 1668: @65056 GIM_Try, /*On fail goto*//*Label 1669*/ 65094, // Rule ID 3184 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 331:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3184, GIR_Done, // Label 1669: @65094 GIM_Try, /*On fail goto*//*Label 1670*/ 65132, // Rule ID 3185 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 331:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3185, GIR_Done, // Label 1670: @65132 GIM_Try, /*On fail goto*//*Label 1671*/ 65170, // Rule ID 3186 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 333:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3186, GIR_Done, // Label 1671: @65170 GIM_Try, /*On fail goto*//*Label 1672*/ 65208, // Rule ID 3187 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 333:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3187, GIR_Done, // Label 1672: @65208 GIM_Try, /*On fail goto*//*Label 1673*/ 65246, // Rule ID 3188 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 337:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3188, GIR_Done, // Label 1673: @65246 GIM_Try, /*On fail goto*//*Label 1674*/ 65284, // Rule ID 3189 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 337:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3189, GIR_Done, // Label 1674: @65284 GIM_Try, /*On fail goto*//*Label 1675*/ 65322, // Rule ID 3190 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 339:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3190, GIR_Done, // Label 1675: @65322 GIM_Try, /*On fail goto*//*Label 1676*/ 65360, // Rule ID 3191 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 339:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3191, GIR_Done, // Label 1676: @65360 GIM_Try, /*On fail goto*//*Label 1677*/ 65462, // Rule ID 3382 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 372:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i8v:{ *:[f16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3382, GIR_Done, // Label 1677: @65462 GIM_Try, /*On fail goto*//*Label 1678*/ 65564, // Rule ID 3383 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 372:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv16i8v:{ *:[f16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv16i8v, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3383, GIR_Done, // Label 1678: @65564 GIM_Reject, // Label 1457: @65565 GIM_Try, /*On fail goto*//*Label 1679*/ 91167, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 1680*/ 65686, // Rule ID 1619 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i64] } 389:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLALv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1619, GIR_Done, // Label 1680: @65686 GIM_Try, /*On fail goto*//*Label 1681*/ 65802, // Rule ID 1624 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i64] } 402:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQDMLSLv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1624, GIR_Done, // Label 1681: @65802 GIM_Try, /*On fail goto*//*Label 1682*/ 65918, // Rule ID 1629 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i32] } 389:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQRDMLAHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHi32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1629, GIR_Done, // Label 1682: @65918 GIM_Try, /*On fail goto*//*Label 1683*/ 66034, // Rule ID 1634 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (intrinsic_wo_chain:{ *:[i32] } 402:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx))) => (SQRDMLSHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHi32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1634, GIR_Done, // Label 1683: @66034 GIM_Try, /*On fail goto*//*Label 1684*/ 66135, // Rule ID 3508 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 463:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR16*/1, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3508, GIR_Done, // Label 1684: @66135 GIM_Try, /*On fail goto*//*Label 1685*/ 66219, // Rule ID 1256 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 389:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 394:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1256, GIR_Done, // Label 1685: @66219 GIM_Try, /*On fail goto*//*Label 1686*/ 66303, // Rule ID 1257 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 389:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 394:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1257, GIR_Done, // Label 1686: @66303 GIM_Try, /*On fail goto*//*Label 1687*/ 66387, // Rule ID 1258 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 389:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 394:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1258, GIR_Done, // Label 1687: @66387 GIM_Try, /*On fail goto*//*Label 1688*/ 66471, // Rule ID 1259 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 389:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 394:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1259, GIR_Done, // Label 1688: @66471 GIM_Try, /*On fail goto*//*Label 1689*/ 66555, // Rule ID 1260 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 402:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 394:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1260, GIR_Done, // Label 1689: @66555 GIM_Try, /*On fail goto*//*Label 1690*/ 66639, // Rule ID 1261 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 402:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 394:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1261, GIR_Done, // Label 1690: @66639 GIM_Try, /*On fail goto*//*Label 1691*/ 66723, // Rule ID 1262 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 402:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 394:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1262, GIR_Done, // Label 1691: @66723 GIM_Try, /*On fail goto*//*Label 1692*/ 66807, // Rule ID 1263 // GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 402:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 394:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1263, GIR_Done, // Label 1692: @66807 GIM_Try, /*On fail goto*//*Label 1693*/ 66891, // Rule ID 1398 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 389:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1398, GIR_Done, // Label 1693: @66891 GIM_Try, /*On fail goto*//*Label 1694*/ 66975, // Rule ID 1400 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 389:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1400, GIR_Done, // Label 1694: @66975 GIM_Try, /*On fail goto*//*Label 1695*/ 67059, // Rule ID 1402 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 402:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1402, GIR_Done, // Label 1695: @67059 GIM_Try, /*On fail goto*//*Label 1696*/ 67143, // Rule ID 1404 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 402:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1404, GIR_Done, // Label 1696: @67143 GIM_Try, /*On fail goto*//*Label 1697*/ 67227, // Rule ID 2991 // GIM_CheckFeatures, GIFBS_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 389:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2991, GIR_Done, // Label 1697: @67227 GIM_Try, /*On fail goto*//*Label 1698*/ 67311, // Rule ID 2992 // GIM_CheckFeatures, GIFBS_HasRDM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 402:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2992, GIR_Done, // Label 1698: @67311 GIM_Try, /*On fail goto*//*Label 1699*/ 67393, // Rule ID 2993 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 389:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2993, GIR_Done, // Label 1699: @67393 GIM_Try, /*On fail goto*//*Label 1700*/ 67475, // Rule ID 2994 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 402:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2994, GIR_Done, // Label 1700: @67475 GIM_Try, /*On fail goto*//*Label 1701*/ 67559, // Rule ID 5565 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 344:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5565, GIR_Done, // Label 1701: @67559 GIM_Try, /*On fail goto*//*Label 1702*/ 67643, // Rule ID 5566 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f32] } 344:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5566, GIR_Done, // Label 1702: @67643 GIM_Try, /*On fail goto*//*Label 1703*/ 67727, // Rule ID 5567 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f64] } 344:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5567, GIR_Done, // Label 1703: @67727 GIM_Try, /*On fail goto*//*Label 1704*/ 67811, // Rule ID 1578 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f16] } 344:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1578, GIR_Done, // Label 1704: @67811 GIM_Try, /*On fail goto*//*Label 1705*/ 67895, // Rule ID 1579 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f32] } 344:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1579, GIR_Done, // Label 1705: @67895 GIM_Try, /*On fail goto*//*Label 1706*/ 67979, // Rule ID 1580 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[f64] } 344:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1580, GIR_Done, // Label 1706: @67979 GIM_Try, /*On fail goto*//*Label 1707*/ 68063, // Rule ID 1593 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 390:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1593, GIR_Done, // Label 1707: @68063 GIM_Try, /*On fail goto*//*Label 1708*/ 68147, // Rule ID 1598 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1598, GIR_Done, // Label 1708: @68147 GIM_Try, /*On fail goto*//*Label 1709*/ 68229, // Rule ID 3492 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<>:$idx)) => (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3492, GIR_Done, // Label 1709: @68229 GIM_Try, /*On fail goto*//*Label 1710*/ 68288, // Rule ID 1652 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 396:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1652, GIR_Done, // Label 1710: @68288 GIM_Try, /*On fail goto*//*Label 1711*/ 68347, // Rule ID 1653 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 397:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1653, GIR_Done, // Label 1711: @68347 GIM_Try, /*On fail goto*//*Label 1712*/ 68406, // Rule ID 1658 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 400:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1658, GIR_Done, // Label 1712: @68406 GIM_Try, /*On fail goto*//*Label 1713*/ 68465, // Rule ID 1659 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 401:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1659, GIR_Done, // Label 1713: @68465 GIM_Try, /*On fail goto*//*Label 1714*/ 68524, // Rule ID 1664 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 444:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1664, GIR_Done, // Label 1714: @68524 GIM_Try, /*On fail goto*//*Label 1715*/ 68583, // Rule ID 1667 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1667, GIR_Done, // Label 1715: @68583 GIM_Try, /*On fail goto*//*Label 1716*/ 68642, // Rule ID 1687 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 368:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1687, GIR_Done, // Label 1716: @68642 GIM_Try, /*On fail goto*//*Label 1717*/ 68701, // Rule ID 1688 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 368:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1688, GIR_Done, // Label 1717: @68701 GIM_Try, /*On fail goto*//*Label 1718*/ 68760, // Rule ID 1689 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 368:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1689, GIR_Done, // Label 1718: @68760 GIM_Try, /*On fail goto*//*Label 1719*/ 68819, // Rule ID 1707 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 396:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1707, GIR_Done, // Label 1719: @68819 GIM_Try, /*On fail goto*//*Label 1720*/ 68878, // Rule ID 1708 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 396:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1708, GIR_Done, // Label 1720: @68878 GIM_Try, /*On fail goto*//*Label 1721*/ 68937, // Rule ID 1709 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 396:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1709, GIR_Done, // Label 1721: @68937 GIM_Try, /*On fail goto*//*Label 1722*/ 68996, // Rule ID 1710 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 397:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1710, GIR_Done, // Label 1722: @68996 GIM_Try, /*On fail goto*//*Label 1723*/ 69055, // Rule ID 1711 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 397:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1711, GIR_Done, // Label 1723: @69055 GIM_Try, /*On fail goto*//*Label 1724*/ 69114, // Rule ID 1712 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 397:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1712, GIR_Done, // Label 1724: @69114 GIM_Try, /*On fail goto*//*Label 1725*/ 69173, // Rule ID 1727 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 400:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1727, GIR_Done, // Label 1725: @69173 GIM_Try, /*On fail goto*//*Label 1726*/ 69232, // Rule ID 1728 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 400:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1728, GIR_Done, // Label 1726: @69232 GIM_Try, /*On fail goto*//*Label 1727*/ 69291, // Rule ID 1729 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 400:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1729, GIR_Done, // Label 1727: @69291 GIM_Try, /*On fail goto*//*Label 1728*/ 69350, // Rule ID 1730 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 401:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1730, GIR_Done, // Label 1728: @69350 GIM_Try, /*On fail goto*//*Label 1729*/ 69409, // Rule ID 1731 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 401:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1731, GIR_Done, // Label 1729: @69409 GIM_Try, /*On fail goto*//*Label 1730*/ 69468, // Rule ID 1732 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 401:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1732, GIR_Done, // Label 1730: @69468 GIM_Try, /*On fail goto*//*Label 1731*/ 69527, // Rule ID 1779 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 444:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1779, GIR_Done, // Label 1731: @69527 GIM_Try, /*On fail goto*//*Label 1732*/ 69586, // Rule ID 1780 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 444:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1780, GIR_Done, // Label 1732: @69586 GIM_Try, /*On fail goto*//*Label 1733*/ 69645, // Rule ID 1781 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 444:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1781, GIR_Done, // Label 1733: @69645 GIM_Try, /*On fail goto*//*Label 1734*/ 69704, // Rule ID 1789 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 446:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1789, GIR_Done, // Label 1734: @69704 GIM_Try, /*On fail goto*//*Label 1735*/ 69763, // Rule ID 1790 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1790, GIR_Done, // Label 1735: @69763 GIM_Try, /*On fail goto*//*Label 1736*/ 69822, // Rule ID 1791 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1791, GIR_Done, // Label 1736: @69822 GIM_Try, /*On fail goto*//*Label 1737*/ 69879, // Rule ID 3493 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 459:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3493, GIR_Done, // Label 1737: @69879 GIM_Try, /*On fail goto*//*Label 1738*/ 69936, // Rule ID 3494 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 460:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3494, GIR_Done, // Label 1738: @69936 GIM_Try, /*On fail goto*//*Label 1739*/ 69993, // Rule ID 3495 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 459:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3495, GIR_Done, // Label 1739: @69993 GIM_Try, /*On fail goto*//*Label 1740*/ 70050, // Rule ID 3496 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 460:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3496, GIR_Done, // Label 1740: @70050 GIM_Try, /*On fail goto*//*Label 1741*/ 70107, // Rule ID 3497 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 459:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3497, GIR_Done, // Label 1741: @70107 GIM_Try, /*On fail goto*//*Label 1742*/ 70164, // Rule ID 3498 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 460:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3498, GIR_Done, // Label 1742: @70164 GIM_Try, /*On fail goto*//*Label 1743*/ 70221, // Rule ID 3499 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f32] } 463:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3499, GIR_Done, // Label 1743: @70221 GIM_Try, /*On fail goto*//*Label 1744*/ 70278, // Rule ID 3500 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f64] } 463:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3500, GIR_Done, // Label 1744: @70278 GIM_Try, /*On fail goto*//*Label 1745*/ 70335, // Rule ID 3501 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1f64] } 462:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3501, GIR_Done, // Label 1745: @70335 GIM_Try, /*On fail goto*//*Label 1746*/ 70392, // Rule ID 3502 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f64] } 462:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3502, GIR_Done, // Label 1746: @70392 GIM_Try, /*On fail goto*//*Label 1747*/ 70449, // Rule ID 3503 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1f64] } 463:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3503, GIR_Done, // Label 1747: @70449 GIM_Try, /*On fail goto*//*Label 1748*/ 70506, // Rule ID 3504 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f32] } 462:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3504, GIR_Done, // Label 1748: @70506 GIM_Try, /*On fail goto*//*Label 1749*/ 70586, // Rule ID 3506 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 462:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR16*/1, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3506, GIR_Done, // Label 1749: @70586 GIM_Try, /*On fail goto*//*Label 1750*/ 70666, // Rule ID 3507 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 462:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR16*/1, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3507, GIR_Done, // Label 1750: @70666 GIM_Try, /*On fail goto*//*Label 1751*/ 70746, // Rule ID 3509 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 463:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR16*/1, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3509, GIR_Done, // Label 1751: @70746 GIM_Try, /*On fail goto*//*Label 1752*/ 70826, // Rule ID 3510 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[f16] } 463:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR16*/1, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3510, GIR_Done, // Label 1752: @70826 GIM_Try, /*On fail goto*//*Label 1753*/ 70928, // Rule ID 3511 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 459:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3511, GIR_Done, // Label 1753: @70928 GIM_Try, /*On fail goto*//*Label 1754*/ 71030, // Rule ID 3512 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 459:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3512, GIR_Done, // Label 1754: @71030 GIM_Try, /*On fail goto*//*Label 1755*/ 71132, // Rule ID 3513 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 460:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3513, GIR_Done, // Label 1755: @71132 GIM_Try, /*On fail goto*//*Label 1756*/ 71234, // Rule ID 3514 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i64] } 460:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<>:$imm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3514, GIR_Done, // Label 1756: @71234 GIM_Try, /*On fail goto*//*Label 1757*/ 71290, // Rule ID 1672 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 459:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1672, GIR_Done, // Label 1757: @71290 GIM_Try, /*On fail goto*//*Label 1758*/ 71346, // Rule ID 1673 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 459:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1673, GIR_Done, // Label 1758: @71346 GIM_Try, /*On fail goto*//*Label 1759*/ 71402, // Rule ID 1674 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 459:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1674, GIR_Done, // Label 1759: @71402 GIM_Try, /*On fail goto*//*Label 1760*/ 71458, // Rule ID 1675 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 459:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1675, GIR_Done, // Label 1760: @71458 GIM_Try, /*On fail goto*//*Label 1761*/ 71514, // Rule ID 1676 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 459:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1676, GIR_Done, // Label 1761: @71514 GIM_Try, /*On fail goto*//*Label 1762*/ 71570, // Rule ID 1677 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 460:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1677, GIR_Done, // Label 1762: @71570 GIM_Try, /*On fail goto*//*Label 1763*/ 71626, // Rule ID 1678 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 460:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1678, GIR_Done, // Label 1763: @71626 GIM_Try, /*On fail goto*//*Label 1764*/ 71682, // Rule ID 1679 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 460:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1679, GIR_Done, // Label 1764: @71682 GIM_Try, /*On fail goto*//*Label 1765*/ 71738, // Rule ID 1680 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 460:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1680, GIR_Done, // Label 1765: @71738 GIM_Try, /*On fail goto*//*Label 1766*/ 71794, // Rule ID 1681 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 460:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1681, GIR_Done, // Label 1766: @71794 GIM_Try, /*On fail goto*//*Label 1767*/ 71850, // Rule ID 1682 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 462:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1682, GIR_Done, // Label 1767: @71850 GIM_Try, /*On fail goto*//*Label 1768*/ 71906, // Rule ID 1683 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 462:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1683, GIR_Done, // Label 1768: @71906 GIM_Try, /*On fail goto*//*Label 1769*/ 71962, // Rule ID 1684 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 462:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1684, GIR_Done, // Label 1769: @71962 GIM_Try, /*On fail goto*//*Label 1770*/ 72018, // Rule ID 1685 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 462:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1685, GIR_Done, // Label 1770: @72018 GIM_Try, /*On fail goto*//*Label 1771*/ 72074, // Rule ID 1686 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f64] } 462:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1686, GIR_Done, // Label 1771: @72074 GIM_Try, /*On fail goto*//*Label 1772*/ 72130, // Rule ID 1774 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 463:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1774, GIR_Done, // Label 1772: @72130 GIM_Try, /*On fail goto*//*Label 1773*/ 72186, // Rule ID 1775 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 463:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1775, GIR_Done, // Label 1773: @72186 GIM_Try, /*On fail goto*//*Label 1774*/ 72242, // Rule ID 1776 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 463:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1776, GIR_Done, // Label 1774: @72242 GIM_Try, /*On fail goto*//*Label 1775*/ 72298, // Rule ID 1777 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1777, GIR_Done, // Label 1775: @72298 GIM_Try, /*On fail goto*//*Label 1776*/ 72354, // Rule ID 1778 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f64] } 463:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1778, GIR_Done, // Label 1776: @72354 GIM_Try, /*On fail goto*//*Label 1777*/ 72406, // Rule ID 99 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 272:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Brr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 99, GIR_Done, // Label 1777: @72406 GIM_Try, /*On fail goto*//*Label 1778*/ 72458, // Rule ID 100 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 277:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Hrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 100, GIR_Done, // Label 1778: @72458 GIM_Try, /*On fail goto*//*Label 1779*/ 72510, // Rule ID 101 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32w, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 278:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Wrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 101, GIR_Done, // Label 1779: @72510 GIM_Try, /*On fail goto*//*Label 1780*/ 72562, // Rule ID 102 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 279:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Xrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 102, GIR_Done, // Label 1780: @72562 GIM_Try, /*On fail goto*//*Label 1781*/ 72614, // Rule ID 103 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 273:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CBrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 103, GIR_Done, // Label 1781: @72614 GIM_Try, /*On fail goto*//*Label 1782*/ 72666, // Rule ID 104 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32ch, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 274:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 104, GIR_Done, // Label 1782: @72666 GIM_Try, /*On fail goto*//*Label 1783*/ 72718, // Rule ID 105 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 275:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CWrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 105, GIR_Done, // Label 1783: @72718 GIM_Try, /*On fail goto*//*Label 1784*/ 72770, // Rule ID 106 // GIM_CheckFeatures, GIFBS_HasCRC, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 276:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CXrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 106, GIR_Done, // Label 1784: @72770 GIM_Try, /*On fail goto*//*Label 1785*/ 72822, // Rule ID 824 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 419:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 824, GIR_Done, // Label 1785: @72822 GIM_Try, /*On fail goto*//*Label 1786*/ 72874, // Rule ID 825 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 419:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 825, GIR_Done, // Label 1786: @72874 GIM_Try, /*On fail goto*//*Label 1787*/ 72926, // Rule ID 826 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 419:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 826, GIR_Done, // Label 1787: @72926 GIM_Try, /*On fail goto*//*Label 1788*/ 72978, // Rule ID 827 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 419:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 827, GIR_Done, // Label 1788: @72978 GIM_Try, /*On fail goto*//*Label 1789*/ 73030, // Rule ID 828 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 419:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 828, GIR_Done, // Label 1789: @73030 GIM_Try, /*On fail goto*//*Label 1790*/ 73082, // Rule ID 829 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 419:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 829, GIR_Done, // Label 1790: @73082 GIM_Try, /*On fail goto*//*Label 1791*/ 73134, // Rule ID 830 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 419:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 830, GIR_Done, // Label 1791: @73134 GIM_Try, /*On fail goto*//*Label 1792*/ 73186, // Rule ID 855 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 455:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 855, GIR_Done, // Label 1792: @73186 GIM_Try, /*On fail goto*//*Label 1793*/ 73238, // Rule ID 856 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 455:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 856, GIR_Done, // Label 1793: @73238 GIM_Try, /*On fail goto*//*Label 1794*/ 73290, // Rule ID 857 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 455:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 857, GIR_Done, // Label 1794: @73290 GIM_Try, /*On fail goto*//*Label 1795*/ 73342, // Rule ID 858 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 455:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 858, GIR_Done, // Label 1795: @73342 GIM_Try, /*On fail goto*//*Label 1796*/ 73394, // Rule ID 859 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 455:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 859, GIR_Done, // Label 1796: @73394 GIM_Try, /*On fail goto*//*Label 1797*/ 73446, // Rule ID 860 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 455:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 860, GIR_Done, // Label 1797: @73446 GIM_Try, /*On fail goto*//*Label 1798*/ 73498, // Rule ID 861 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 455:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 861, GIR_Done, // Label 1798: @73498 GIM_Try, /*On fail goto*//*Label 1799*/ 73550, // Rule ID 872 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 310:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 872, GIR_Done, // Label 1799: @73550 GIM_Try, /*On fail goto*//*Label 1800*/ 73602, // Rule ID 873 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 310:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 873, GIR_Done, // Label 1800: @73602 GIM_Try, /*On fail goto*//*Label 1801*/ 73654, // Rule ID 874 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 310:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 874, GIR_Done, // Label 1801: @73654 GIM_Try, /*On fail goto*//*Label 1802*/ 73706, // Rule ID 875 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 310:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 875, GIR_Done, // Label 1802: @73706 GIM_Try, /*On fail goto*//*Label 1803*/ 73758, // Rule ID 876 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 310:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 876, GIR_Done, // Label 1803: @73758 GIM_Try, /*On fail goto*//*Label 1804*/ 73810, // Rule ID 877 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 310:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 877, GIR_Done, // Label 1804: @73810 GIM_Try, /*On fail goto*//*Label 1805*/ 73862, // Rule ID 878 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 310:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 878, GIR_Done, // Label 1805: @73862 GIM_Try, /*On fail goto*//*Label 1806*/ 73914, // Rule ID 921 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 312:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 921, GIR_Done, // Label 1806: @73914 GIM_Try, /*On fail goto*//*Label 1807*/ 73966, // Rule ID 922 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 312:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 922, GIR_Done, // Label 1807: @73966 GIM_Try, /*On fail goto*//*Label 1808*/ 74018, // Rule ID 923 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 312:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 923, GIR_Done, // Label 1808: @74018 GIM_Try, /*On fail goto*//*Label 1809*/ 74070, // Rule ID 924 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 312:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 924, GIR_Done, // Label 1809: @74070 GIM_Try, /*On fail goto*//*Label 1810*/ 74122, // Rule ID 925 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 312:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 925, GIR_Done, // Label 1810: @74122 GIM_Try, /*On fail goto*//*Label 1811*/ 74174, // Rule ID 926 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 313:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 926, GIR_Done, // Label 1811: @74174 GIM_Try, /*On fail goto*//*Label 1812*/ 74226, // Rule ID 927 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 313:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 927, GIR_Done, // Label 1812: @74226 GIM_Try, /*On fail goto*//*Label 1813*/ 74278, // Rule ID 928 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 313:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 928, GIR_Done, // Label 1813: @74278 GIM_Try, /*On fail goto*//*Label 1814*/ 74330, // Rule ID 929 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 313:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 929, GIR_Done, // Label 1814: @74330 GIM_Try, /*On fail goto*//*Label 1815*/ 74382, // Rule ID 930 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 313:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 930, GIR_Done, // Label 1815: @74382 GIM_Try, /*On fail goto*//*Label 1816*/ 74434, // Rule ID 931 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 314:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 931, GIR_Done, // Label 1816: @74434 GIM_Try, /*On fail goto*//*Label 1817*/ 74486, // Rule ID 932 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 314:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 932, GIR_Done, // Label 1817: @74486 GIM_Try, /*On fail goto*//*Label 1818*/ 74538, // Rule ID 933 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 314:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 933, GIR_Done, // Label 1818: @74538 GIM_Try, /*On fail goto*//*Label 1819*/ 74590, // Rule ID 934 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 314:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 934, GIR_Done, // Label 1819: @74590 GIM_Try, /*On fail goto*//*Label 1820*/ 74642, // Rule ID 935 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 314:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 935, GIR_Done, // Label 1820: @74642 GIM_Try, /*On fail goto*//*Label 1821*/ 74694, // Rule ID 936 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 315:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 936, GIR_Done, // Label 1821: @74694 GIM_Try, /*On fail goto*//*Label 1822*/ 74746, // Rule ID 937 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 315:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 937, GIR_Done, // Label 1822: @74746 GIM_Try, /*On fail goto*//*Label 1823*/ 74798, // Rule ID 938 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 315:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 938, GIR_Done, // Label 1823: @74798 GIM_Try, /*On fail goto*//*Label 1824*/ 74850, // Rule ID 939 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 315:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 939, GIR_Done, // Label 1824: @74850 GIM_Try, /*On fail goto*//*Label 1825*/ 74902, // Rule ID 940 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 315:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 940, GIR_Done, // Label 1825: @74902 GIM_Try, /*On fail goto*//*Label 1826*/ 74954, // Rule ID 966 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 330:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 966, GIR_Done, // Label 1826: @74954 GIM_Try, /*On fail goto*//*Label 1827*/ 75006, // Rule ID 967 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 330:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 967, GIR_Done, // Label 1827: @75006 GIM_Try, /*On fail goto*//*Label 1828*/ 75058, // Rule ID 968 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 330:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 968, GIR_Done, // Label 1828: @75058 GIM_Try, /*On fail goto*//*Label 1829*/ 75110, // Rule ID 969 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 330:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 969, GIR_Done, // Label 1829: @75110 GIM_Try, /*On fail goto*//*Label 1830*/ 75162, // Rule ID 970 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 330:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 970, GIR_Done, // Label 1830: @75162 GIM_Try, /*On fail goto*//*Label 1831*/ 75214, // Rule ID 976 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 332:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 976, GIR_Done, // Label 1831: @75214 GIM_Try, /*On fail goto*//*Label 1832*/ 75266, // Rule ID 977 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 332:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 977, GIR_Done, // Label 1832: @75266 GIM_Try, /*On fail goto*//*Label 1833*/ 75318, // Rule ID 978 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 332:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 978, GIR_Done, // Label 1833: @75318 GIM_Try, /*On fail goto*//*Label 1834*/ 75370, // Rule ID 979 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 332:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 979, GIR_Done, // Label 1834: @75370 GIM_Try, /*On fail goto*//*Label 1835*/ 75422, // Rule ID 980 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 332:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 980, GIR_Done, // Label 1835: @75422 GIM_Try, /*On fail goto*//*Label 1836*/ 75474, // Rule ID 986 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 336:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 986, GIR_Done, // Label 1836: @75474 GIM_Try, /*On fail goto*//*Label 1837*/ 75526, // Rule ID 987 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 336:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 987, GIR_Done, // Label 1837: @75526 GIM_Try, /*On fail goto*//*Label 1838*/ 75578, // Rule ID 988 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 336:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 988, GIR_Done, // Label 1838: @75578 GIM_Try, /*On fail goto*//*Label 1839*/ 75630, // Rule ID 989 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 336:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 989, GIR_Done, // Label 1839: @75630 GIM_Try, /*On fail goto*//*Label 1840*/ 75682, // Rule ID 990 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 336:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 990, GIR_Done, // Label 1840: @75682 GIM_Try, /*On fail goto*//*Label 1841*/ 75734, // Rule ID 996 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 338:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 996, GIR_Done, // Label 1841: @75734 GIM_Try, /*On fail goto*//*Label 1842*/ 75786, // Rule ID 997 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 338:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 997, GIR_Done, // Label 1842: @75786 GIM_Try, /*On fail goto*//*Label 1843*/ 75838, // Rule ID 998 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 338:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 998, GIR_Done, // Label 1843: @75838 GIM_Try, /*On fail goto*//*Label 1844*/ 75890, // Rule ID 999 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 338:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 999, GIR_Done, // Label 1844: @75890 GIM_Try, /*On fail goto*//*Label 1845*/ 75942, // Rule ID 1000 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 338:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1000, GIR_Done, // Label 1845: @75942 GIM_Try, /*On fail goto*//*Label 1846*/ 75994, // Rule ID 1016 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 344:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1016, GIR_Done, // Label 1846: @75994 GIM_Try, /*On fail goto*//*Label 1847*/ 76046, // Rule ID 1017 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 344:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1017, GIR_Done, // Label 1847: @76046 GIM_Try, /*On fail goto*//*Label 1848*/ 76098, // Rule ID 1018 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 344:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1018, GIR_Done, // Label 1848: @76098 GIM_Try, /*On fail goto*//*Label 1849*/ 76150, // Rule ID 1019 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 344:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1019, GIR_Done, // Label 1849: @76150 GIM_Try, /*On fail goto*//*Label 1850*/ 76202, // Rule ID 1020 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 344:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1020, GIR_Done, // Label 1850: @76202 GIM_Try, /*On fail goto*//*Label 1851*/ 76254, // Rule ID 1026 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 346:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1026, GIR_Done, // Label 1851: @76254 GIM_Try, /*On fail goto*//*Label 1852*/ 76306, // Rule ID 1027 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 346:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1027, GIR_Done, // Label 1852: @76306 GIM_Try, /*On fail goto*//*Label 1853*/ 76358, // Rule ID 1028 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 346:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1028, GIR_Done, // Label 1853: @76358 GIM_Try, /*On fail goto*//*Label 1854*/ 76410, // Rule ID 1029 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 346:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1029, GIR_Done, // Label 1854: @76410 GIM_Try, /*On fail goto*//*Label 1855*/ 76462, // Rule ID 1030 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 346:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1030, GIR_Done, // Label 1855: @76462 GIM_Try, /*On fail goto*//*Label 1856*/ 76514, // Rule ID 1031 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 350:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1031, GIR_Done, // Label 1856: @76514 GIM_Try, /*On fail goto*//*Label 1857*/ 76566, // Rule ID 1032 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 350:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1032, GIR_Done, // Label 1857: @76566 GIM_Try, /*On fail goto*//*Label 1858*/ 76618, // Rule ID 1033 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 350:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1033, GIR_Done, // Label 1858: @76618 GIM_Try, /*On fail goto*//*Label 1859*/ 76670, // Rule ID 1034 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 350:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1034, GIR_Done, // Label 1859: @76670 GIM_Try, /*On fail goto*//*Label 1860*/ 76722, // Rule ID 1035 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 350:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1035, GIR_Done, // Label 1860: @76722 GIM_Try, /*On fail goto*//*Label 1861*/ 76774, // Rule ID 1047 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 363:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1047, GIR_Done, // Label 1861: @76774 GIM_Try, /*On fail goto*//*Label 1862*/ 76826, // Rule ID 1048 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 363:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1048, GIR_Done, // Label 1862: @76826 GIM_Try, /*On fail goto*//*Label 1863*/ 76878, // Rule ID 1055 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1055, GIR_Done, // Label 1863: @76878 GIM_Try, /*On fail goto*//*Label 1864*/ 76930, // Rule ID 1056 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 370:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1056, GIR_Done, // Label 1864: @76930 GIM_Try, /*On fail goto*//*Label 1865*/ 76982, // Rule ID 1057 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1057, GIR_Done, // Label 1865: @76982 GIM_Try, /*On fail goto*//*Label 1866*/ 77034, // Rule ID 1058 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 370:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1058, GIR_Done, // Label 1866: @77034 GIM_Try, /*On fail goto*//*Label 1867*/ 77086, // Rule ID 1059 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1059, GIR_Done, // Label 1867: @77086 GIM_Try, /*On fail goto*//*Label 1868*/ 77138, // Rule ID 1060 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 370:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1060, GIR_Done, // Label 1868: @77138 GIM_Try, /*On fail goto*//*Label 1869*/ 77190, // Rule ID 1061 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 378:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1061, GIR_Done, // Label 1869: @77190 GIM_Try, /*On fail goto*//*Label 1870*/ 77242, // Rule ID 1062 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 378:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1062, GIR_Done, // Label 1870: @77242 GIM_Try, /*On fail goto*//*Label 1871*/ 77294, // Rule ID 1063 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1063, GIR_Done, // Label 1871: @77294 GIM_Try, /*On fail goto*//*Label 1872*/ 77346, // Rule ID 1064 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 378:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1064, GIR_Done, // Label 1872: @77346 GIM_Try, /*On fail goto*//*Label 1873*/ 77398, // Rule ID 1065 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1065, GIR_Done, // Label 1873: @77398 GIM_Try, /*On fail goto*//*Label 1874*/ 77450, // Rule ID 1066 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 378:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1066, GIR_Done, // Label 1874: @77450 GIM_Try, /*On fail goto*//*Label 1875*/ 77502, // Rule ID 1067 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 380:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1067, GIR_Done, // Label 1875: @77502 GIM_Try, /*On fail goto*//*Label 1876*/ 77554, // Rule ID 1068 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 380:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1068, GIR_Done, // Label 1876: @77554 GIM_Try, /*On fail goto*//*Label 1877*/ 77606, // Rule ID 1069 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 380:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1069, GIR_Done, // Label 1877: @77606 GIM_Try, /*On fail goto*//*Label 1878*/ 77658, // Rule ID 1070 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 380:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1070, GIR_Done, // Label 1878: @77658 GIM_Try, /*On fail goto*//*Label 1879*/ 77710, // Rule ID 1071 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 380:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1071, GIR_Done, // Label 1879: @77710 GIM_Try, /*On fail goto*//*Label 1880*/ 77762, // Rule ID 1072 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 380:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1072, GIR_Done, // Label 1880: @77762 GIM_Try, /*On fail goto*//*Label 1881*/ 77814, // Rule ID 1073 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 382:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1073, GIR_Done, // Label 1881: @77814 GIM_Try, /*On fail goto*//*Label 1882*/ 77866, // Rule ID 1074 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 382:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1074, GIR_Done, // Label 1882: @77866 GIM_Try, /*On fail goto*//*Label 1883*/ 77918, // Rule ID 1075 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 382:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1075, GIR_Done, // Label 1883: @77918 GIM_Try, /*On fail goto*//*Label 1884*/ 77970, // Rule ID 1076 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 382:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1076, GIR_Done, // Label 1884: @77970 GIM_Try, /*On fail goto*//*Label 1885*/ 78022, // Rule ID 1077 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 382:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1077, GIR_Done, // Label 1885: @78022 GIM_Try, /*On fail goto*//*Label 1886*/ 78074, // Rule ID 1078 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 382:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1078, GIR_Done, // Label 1886: @78074 GIM_Try, /*On fail goto*//*Label 1887*/ 78126, // Rule ID 1085 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 385:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1085, GIR_Done, // Label 1887: @78126 GIM_Try, /*On fail goto*//*Label 1888*/ 78178, // Rule ID 1086 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 385:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1086, GIR_Done, // Label 1888: @78178 GIM_Try, /*On fail goto*//*Label 1889*/ 78230, // Rule ID 1087 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 385:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1087, GIR_Done, // Label 1889: @78230 GIM_Try, /*On fail goto*//*Label 1890*/ 78282, // Rule ID 1088 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 385:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1088, GIR_Done, // Label 1890: @78282 GIM_Try, /*On fail goto*//*Label 1891*/ 78334, // Rule ID 1089 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 385:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1089, GIR_Done, // Label 1891: @78334 GIM_Try, /*On fail goto*//*Label 1892*/ 78386, // Rule ID 1090 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 385:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1090, GIR_Done, // Label 1892: @78386 GIM_Try, /*On fail goto*//*Label 1893*/ 78438, // Rule ID 1097 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 389:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1097, GIR_Done, // Label 1893: @78438 GIM_Try, /*On fail goto*//*Label 1894*/ 78490, // Rule ID 1098 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 389:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1098, GIR_Done, // Label 1894: @78490 GIM_Try, /*On fail goto*//*Label 1895*/ 78542, // Rule ID 1099 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 389:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1099, GIR_Done, // Label 1895: @78542 GIM_Try, /*On fail goto*//*Label 1896*/ 78594, // Rule ID 1100 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 389:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1100, GIR_Done, // Label 1896: @78594 GIM_Try, /*On fail goto*//*Label 1897*/ 78646, // Rule ID 1101 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 389:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1101, GIR_Done, // Label 1897: @78646 GIM_Try, /*On fail goto*//*Label 1898*/ 78698, // Rule ID 1102 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 389:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1102, GIR_Done, // Label 1898: @78698 GIM_Try, /*On fail goto*//*Label 1899*/ 78750, // Rule ID 1103 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 389:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1103, GIR_Done, // Label 1899: @78750 GIM_Try, /*On fail goto*//*Label 1900*/ 78802, // Rule ID 1104 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 390:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1104, GIR_Done, // Label 1900: @78802 GIM_Try, /*On fail goto*//*Label 1901*/ 78854, // Rule ID 1105 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 390:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1105, GIR_Done, // Label 1901: @78854 GIM_Try, /*On fail goto*//*Label 1902*/ 78906, // Rule ID 1106 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 390:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1106, GIR_Done, // Label 1902: @78906 GIM_Try, /*On fail goto*//*Label 1903*/ 78958, // Rule ID 1107 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 390:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1107, GIR_Done, // Label 1903: @78958 GIM_Try, /*On fail goto*//*Label 1904*/ 79010, // Rule ID 1108 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 394:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1108, GIR_Done, // Label 1904: @79010 GIM_Try, /*On fail goto*//*Label 1905*/ 79062, // Rule ID 1109 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 394:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1109, GIR_Done, // Label 1905: @79062 GIM_Try, /*On fail goto*//*Label 1906*/ 79114, // Rule ID 1110 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 394:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1110, GIR_Done, // Label 1906: @79114 GIM_Try, /*On fail goto*//*Label 1907*/ 79166, // Rule ID 1111 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 394:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1111, GIR_Done, // Label 1907: @79166 GIM_Try, /*On fail goto*//*Label 1908*/ 79218, // Rule ID 1112 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 395:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1112, GIR_Done, // Label 1908: @79218 GIM_Try, /*On fail goto*//*Label 1909*/ 79270, // Rule ID 1113 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 395:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1113, GIR_Done, // Label 1909: @79270 GIM_Try, /*On fail goto*//*Label 1910*/ 79322, // Rule ID 1114 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 395:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1114, GIR_Done, // Label 1910: @79322 GIM_Try, /*On fail goto*//*Label 1911*/ 79374, // Rule ID 1115 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 395:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1115, GIR_Done, // Label 1911: @79374 GIM_Try, /*On fail goto*//*Label 1912*/ 79426, // Rule ID 1116 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 395:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1116, GIR_Done, // Label 1912: @79426 GIM_Try, /*On fail goto*//*Label 1913*/ 79478, // Rule ID 1117 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 395:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1117, GIR_Done, // Label 1913: @79478 GIM_Try, /*On fail goto*//*Label 1914*/ 79530, // Rule ID 1118 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 395:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1118, GIR_Done, // Label 1914: @79530 GIM_Try, /*On fail goto*//*Label 1915*/ 79582, // Rule ID 1119 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 398:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1119, GIR_Done, // Label 1915: @79582 GIM_Try, /*On fail goto*//*Label 1916*/ 79634, // Rule ID 1120 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 398:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1120, GIR_Done, // Label 1916: @79634 GIM_Try, /*On fail goto*//*Label 1917*/ 79686, // Rule ID 1121 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 398:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1121, GIR_Done, // Label 1917: @79686 GIM_Try, /*On fail goto*//*Label 1918*/ 79738, // Rule ID 1122 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 398:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1122, GIR_Done, // Label 1918: @79738 GIM_Try, /*On fail goto*//*Label 1919*/ 79790, // Rule ID 1123 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 398:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1123, GIR_Done, // Label 1919: @79790 GIM_Try, /*On fail goto*//*Label 1920*/ 79842, // Rule ID 1124 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 398:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1124, GIR_Done, // Label 1920: @79842 GIM_Try, /*On fail goto*//*Label 1921*/ 79894, // Rule ID 1125 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 398:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1125, GIR_Done, // Label 1921: @79894 GIM_Try, /*On fail goto*//*Label 1922*/ 79946, // Rule ID 1126 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 402:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1126, GIR_Done, // Label 1922: @79946 GIM_Try, /*On fail goto*//*Label 1923*/ 79998, // Rule ID 1127 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 402:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1127, GIR_Done, // Label 1923: @79998 GIM_Try, /*On fail goto*//*Label 1924*/ 80050, // Rule ID 1128 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 402:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1128, GIR_Done, // Label 1924: @80050 GIM_Try, /*On fail goto*//*Label 1925*/ 80102, // Rule ID 1129 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 402:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1129, GIR_Done, // Label 1925: @80102 GIM_Try, /*On fail goto*//*Label 1926*/ 80154, // Rule ID 1130 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 402:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1130, GIR_Done, // Label 1926: @80154 GIM_Try, /*On fail goto*//*Label 1927*/ 80206, // Rule ID 1131 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 402:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1131, GIR_Done, // Label 1927: @80206 GIM_Try, /*On fail goto*//*Label 1928*/ 80258, // Rule ID 1132 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 402:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1132, GIR_Done, // Label 1928: @80258 GIM_Try, /*On fail goto*//*Label 1929*/ 80310, // Rule ID 1133 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 405:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1133, GIR_Done, // Label 1929: @80310 GIM_Try, /*On fail goto*//*Label 1930*/ 80362, // Rule ID 1134 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 405:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1134, GIR_Done, // Label 1930: @80362 GIM_Try, /*On fail goto*//*Label 1931*/ 80414, // Rule ID 1135 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 405:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1135, GIR_Done, // Label 1931: @80414 GIM_Try, /*On fail goto*//*Label 1932*/ 80466, // Rule ID 1136 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 405:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1136, GIR_Done, // Label 1932: @80466 GIM_Try, /*On fail goto*//*Label 1933*/ 80518, // Rule ID 1137 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 405:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1137, GIR_Done, // Label 1933: @80518 GIM_Try, /*On fail goto*//*Label 1934*/ 80570, // Rule ID 1138 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 405:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRHADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1138, GIR_Done, // Label 1934: @80570 GIM_Try, /*On fail goto*//*Label 1935*/ 80622, // Rule ID 1139 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 406:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1139, GIR_Done, // Label 1935: @80622 GIM_Try, /*On fail goto*//*Label 1936*/ 80674, // Rule ID 1140 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 406:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1140, GIR_Done, // Label 1936: @80674 GIM_Try, /*On fail goto*//*Label 1937*/ 80726, // Rule ID 1141 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 406:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1141, GIR_Done, // Label 1937: @80726 GIM_Try, /*On fail goto*//*Label 1938*/ 80778, // Rule ID 1142 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 406:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1142, GIR_Done, // Label 1938: @80778 GIM_Try, /*On fail goto*//*Label 1939*/ 80830, // Rule ID 1143 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 406:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1143, GIR_Done, // Label 1939: @80830 GIM_Try, /*On fail goto*//*Label 1940*/ 80882, // Rule ID 1144 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 406:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1144, GIR_Done, // Label 1940: @80882 GIM_Try, /*On fail goto*//*Label 1941*/ 80934, // Rule ID 1145 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 406:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1145, GIR_Done, // Label 1941: @80934 GIM_Try, /*On fail goto*//*Label 1942*/ 80986, // Rule ID 1146 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 407:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1146, GIR_Done, // Label 1942: @80986 GIM_Try, /*On fail goto*//*Label 1943*/ 81038, // Rule ID 1147 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 407:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1147, GIR_Done, // Label 1943: @81038 GIM_Try, /*On fail goto*//*Label 1944*/ 81090, // Rule ID 1148 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 407:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1148, GIR_Done, // Label 1944: @81090 GIM_Try, /*On fail goto*//*Label 1945*/ 81142, // Rule ID 1149 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 407:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1149, GIR_Done, // Label 1945: @81142 GIM_Try, /*On fail goto*//*Label 1946*/ 81194, // Rule ID 1150 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 407:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1150, GIR_Done, // Label 1946: @81194 GIM_Try, /*On fail goto*//*Label 1947*/ 81246, // Rule ID 1151 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 407:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1151, GIR_Done, // Label 1947: @81246 GIM_Try, /*On fail goto*//*Label 1948*/ 81298, // Rule ID 1152 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 407:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1152, GIR_Done, // Label 1948: @81298 GIM_Try, /*On fail goto*//*Label 1949*/ 81350, // Rule ID 1166 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1166, GIR_Done, // Label 1949: @81350 GIM_Try, /*On fail goto*//*Label 1950*/ 81402, // Rule ID 1167 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 428:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1167, GIR_Done, // Label 1950: @81402 GIM_Try, /*On fail goto*//*Label 1951*/ 81454, // Rule ID 1168 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1168, GIR_Done, // Label 1951: @81454 GIM_Try, /*On fail goto*//*Label 1952*/ 81506, // Rule ID 1169 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 428:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1169, GIR_Done, // Label 1952: @81506 GIM_Try, /*On fail goto*//*Label 1953*/ 81558, // Rule ID 1170 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1170, GIR_Done, // Label 1953: @81558 GIM_Try, /*On fail goto*//*Label 1954*/ 81610, // Rule ID 1171 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 428:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1171, GIR_Done, // Label 1954: @81610 GIM_Try, /*On fail goto*//*Label 1955*/ 81662, // Rule ID 1172 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 433:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1172, GIR_Done, // Label 1955: @81662 GIM_Try, /*On fail goto*//*Label 1956*/ 81714, // Rule ID 1173 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 433:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1173, GIR_Done, // Label 1956: @81714 GIM_Try, /*On fail goto*//*Label 1957*/ 81766, // Rule ID 1174 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 433:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1174, GIR_Done, // Label 1957: @81766 GIM_Try, /*On fail goto*//*Label 1958*/ 81818, // Rule ID 1175 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 433:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1175, GIR_Done, // Label 1958: @81818 GIM_Try, /*On fail goto*//*Label 1959*/ 81870, // Rule ID 1176 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 433:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1176, GIR_Done, // Label 1959: @81870 GIM_Try, /*On fail goto*//*Label 1960*/ 81922, // Rule ID 1177 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 433:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1177, GIR_Done, // Label 1960: @81922 GIM_Try, /*On fail goto*//*Label 1961*/ 81974, // Rule ID 1178 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 434:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1178, GIR_Done, // Label 1961: @81974 GIM_Try, /*On fail goto*//*Label 1962*/ 82026, // Rule ID 1179 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 434:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1179, GIR_Done, // Label 1962: @82026 GIM_Try, /*On fail goto*//*Label 1963*/ 82078, // Rule ID 1180 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 434:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1180, GIR_Done, // Label 1963: @82078 GIM_Try, /*On fail goto*//*Label 1964*/ 82130, // Rule ID 1181 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 434:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1181, GIR_Done, // Label 1964: @82130 GIM_Try, /*On fail goto*//*Label 1965*/ 82182, // Rule ID 1182 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 434:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1182, GIR_Done, // Label 1965: @82182 GIM_Try, /*On fail goto*//*Label 1966*/ 82234, // Rule ID 1183 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 434:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1183, GIR_Done, // Label 1966: @82234 GIM_Try, /*On fail goto*//*Label 1967*/ 82286, // Rule ID 1184 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 436:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1184, GIR_Done, // Label 1967: @82286 GIM_Try, /*On fail goto*//*Label 1968*/ 82338, // Rule ID 1185 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 436:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1185, GIR_Done, // Label 1968: @82338 GIM_Try, /*On fail goto*//*Label 1969*/ 82390, // Rule ID 1186 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 436:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1186, GIR_Done, // Label 1969: @82390 GIM_Try, /*On fail goto*//*Label 1970*/ 82442, // Rule ID 1187 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 436:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1187, GIR_Done, // Label 1970: @82442 GIM_Try, /*On fail goto*//*Label 1971*/ 82494, // Rule ID 1188 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 436:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1188, GIR_Done, // Label 1971: @82494 GIM_Try, /*On fail goto*//*Label 1972*/ 82546, // Rule ID 1189 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 436:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1189, GIR_Done, // Label 1972: @82546 GIM_Try, /*On fail goto*//*Label 1973*/ 82598, // Rule ID 1196 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 439:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1196, GIR_Done, // Label 1973: @82598 GIM_Try, /*On fail goto*//*Label 1974*/ 82650, // Rule ID 1197 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 439:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1197, GIR_Done, // Label 1974: @82650 GIM_Try, /*On fail goto*//*Label 1975*/ 82702, // Rule ID 1198 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 439:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1198, GIR_Done, // Label 1975: @82702 GIM_Try, /*On fail goto*//*Label 1976*/ 82754, // Rule ID 1199 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 439:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1199, GIR_Done, // Label 1976: @82754 GIM_Try, /*On fail goto*//*Label 1977*/ 82806, // Rule ID 1200 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 439:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1200, GIR_Done, // Label 1977: @82806 GIM_Try, /*On fail goto*//*Label 1978*/ 82858, // Rule ID 1201 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 439:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1201, GIR_Done, // Label 1978: @82858 GIM_Try, /*On fail goto*//*Label 1979*/ 82910, // Rule ID 1208 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 442:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1208, GIR_Done, // Label 1979: @82910 GIM_Try, /*On fail goto*//*Label 1980*/ 82962, // Rule ID 1209 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 442:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1209, GIR_Done, // Label 1980: @82962 GIM_Try, /*On fail goto*//*Label 1981*/ 83014, // Rule ID 1210 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 442:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1210, GIR_Done, // Label 1981: @83014 GIM_Try, /*On fail goto*//*Label 1982*/ 83066, // Rule ID 1211 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 442:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1211, GIR_Done, // Label 1982: @83066 GIM_Try, /*On fail goto*//*Label 1983*/ 83118, // Rule ID 1212 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 442:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1212, GIR_Done, // Label 1983: @83118 GIM_Try, /*On fail goto*//*Label 1984*/ 83170, // Rule ID 1213 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 442:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1213, GIR_Done, // Label 1984: @83170 GIM_Try, /*On fail goto*//*Label 1985*/ 83222, // Rule ID 1214 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 442:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1214, GIR_Done, // Label 1985: @83222 GIM_Try, /*On fail goto*//*Label 1986*/ 83274, // Rule ID 1215 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 443:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1215, GIR_Done, // Label 1986: @83274 GIM_Try, /*On fail goto*//*Label 1987*/ 83326, // Rule ID 1216 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 443:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1216, GIR_Done, // Label 1987: @83326 GIM_Try, /*On fail goto*//*Label 1988*/ 83378, // Rule ID 1217 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 443:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1217, GIR_Done, // Label 1988: @83378 GIM_Try, /*On fail goto*//*Label 1989*/ 83430, // Rule ID 1218 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 443:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1218, GIR_Done, // Label 1989: @83430 GIM_Try, /*On fail goto*//*Label 1990*/ 83482, // Rule ID 1219 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 443:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1219, GIR_Done, // Label 1990: @83482 GIM_Try, /*On fail goto*//*Label 1991*/ 83534, // Rule ID 1220 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 443:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1220, GIR_Done, // Label 1991: @83534 GIM_Try, /*On fail goto*//*Label 1992*/ 83586, // Rule ID 1221 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 443:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1221, GIR_Done, // Label 1992: @83586 GIM_Try, /*On fail goto*//*Label 1993*/ 83638, // Rule ID 1222 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 445:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1222, GIR_Done, // Label 1993: @83638 GIM_Try, /*On fail goto*//*Label 1994*/ 83690, // Rule ID 1223 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 445:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1223, GIR_Done, // Label 1994: @83690 GIM_Try, /*On fail goto*//*Label 1995*/ 83742, // Rule ID 1224 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 445:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1224, GIR_Done, // Label 1995: @83742 GIM_Try, /*On fail goto*//*Label 1996*/ 83794, // Rule ID 1225 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 445:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1225, GIR_Done, // Label 1996: @83794 GIM_Try, /*On fail goto*//*Label 1997*/ 83846, // Rule ID 1226 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 445:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1226, GIR_Done, // Label 1997: @83846 GIM_Try, /*On fail goto*//*Label 1998*/ 83898, // Rule ID 1227 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 445:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1227, GIR_Done, // Label 1998: @83898 GIM_Try, /*On fail goto*//*Label 1999*/ 83950, // Rule ID 1228 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 445:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1228, GIR_Done, // Label 1999: @83950 GIM_Try, /*On fail goto*//*Label 2000*/ 84002, // Rule ID 1229 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 447:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1229, GIR_Done, // Label 2000: @84002 GIM_Try, /*On fail goto*//*Label 2001*/ 84054, // Rule ID 1230 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 447:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1230, GIR_Done, // Label 2001: @84054 GIM_Try, /*On fail goto*//*Label 2002*/ 84106, // Rule ID 1231 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 447:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1231, GIR_Done, // Label 2002: @84106 GIM_Try, /*On fail goto*//*Label 2003*/ 84158, // Rule ID 1232 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 447:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1232, GIR_Done, // Label 2003: @84158 GIM_Try, /*On fail goto*//*Label 2004*/ 84210, // Rule ID 1233 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 447:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1233, GIR_Done, // Label 2004: @84210 GIM_Try, /*On fail goto*//*Label 2005*/ 84262, // Rule ID 1234 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 447:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1234, GIR_Done, // Label 2005: @84262 GIM_Try, /*On fail goto*//*Label 2006*/ 84314, // Rule ID 1235 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 447:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1235, GIR_Done, // Label 2006: @84314 GIM_Try, /*On fail goto*//*Label 2007*/ 84366, // Rule ID 1236 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 450:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1236, GIR_Done, // Label 2007: @84366 GIM_Try, /*On fail goto*//*Label 2008*/ 84418, // Rule ID 1237 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 450:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1237, GIR_Done, // Label 2008: @84418 GIM_Try, /*On fail goto*//*Label 2009*/ 84470, // Rule ID 1238 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1238, GIR_Done, // Label 2009: @84470 GIM_Try, /*On fail goto*//*Label 2010*/ 84522, // Rule ID 1239 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 450:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1239, GIR_Done, // Label 2010: @84522 GIM_Try, /*On fail goto*//*Label 2011*/ 84574, // Rule ID 1240 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1240, GIR_Done, // Label 2011: @84574 GIM_Try, /*On fail goto*//*Label 2012*/ 84626, // Rule ID 1241 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URHADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1241, GIR_Done, // Label 2012: @84626 GIM_Try, /*On fail goto*//*Label 2013*/ 84678, // Rule ID 1242 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 451:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1242, GIR_Done, // Label 2013: @84678 GIM_Try, /*On fail goto*//*Label 2014*/ 84730, // Rule ID 1243 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 451:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1243, GIR_Done, // Label 2014: @84730 GIM_Try, /*On fail goto*//*Label 2015*/ 84782, // Rule ID 1244 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 451:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1244, GIR_Done, // Label 2015: @84782 GIM_Try, /*On fail goto*//*Label 2016*/ 84834, // Rule ID 1245 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 451:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1245, GIR_Done, // Label 2016: @84834 GIM_Try, /*On fail goto*//*Label 2017*/ 84886, // Rule ID 1246 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 451:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1246, GIR_Done, // Label 2017: @84886 GIM_Try, /*On fail goto*//*Label 2018*/ 84938, // Rule ID 1247 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 451:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1247, GIR_Done, // Label 2018: @84938 GIM_Try, /*On fail goto*//*Label 2019*/ 84990, // Rule ID 1248 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 451:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1248, GIR_Done, // Label 2019: @84990 GIM_Try, /*On fail goto*//*Label 2020*/ 85042, // Rule ID 1249 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 453:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1249, GIR_Done, // Label 2020: @85042 GIM_Try, /*On fail goto*//*Label 2021*/ 85094, // Rule ID 1250 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 453:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1250, GIR_Done, // Label 2021: @85094 GIM_Try, /*On fail goto*//*Label 2022*/ 85146, // Rule ID 1251 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1251, GIR_Done, // Label 2022: @85146 GIM_Try, /*On fail goto*//*Label 2023*/ 85198, // Rule ID 1252 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1252, GIR_Done, // Label 2023: @85198 GIM_Try, /*On fail goto*//*Label 2024*/ 85250, // Rule ID 1253 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1253, GIR_Done, // Label 2024: @85250 GIM_Try, /*On fail goto*//*Label 2025*/ 85302, // Rule ID 1254 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1254, GIR_Done, // Label 2025: @85302 GIM_Try, /*On fail goto*//*Label 2026*/ 85354, // Rule ID 1255 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 453:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1255, GIR_Done, // Label 2026: @85354 GIM_Try, /*On fail goto*//*Label 2027*/ 85406, // Rule ID 1285 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 470:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1285, GIR_Done, // Label 2027: @85406 GIM_Try, /*On fail goto*//*Label 2028*/ 85458, // Rule ID 1286 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 470:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1286, GIR_Done, // Label 2028: @85458 GIM_Try, /*On fail goto*//*Label 2029*/ 85510, // Rule ID 1287 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 470:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1287, GIR_Done, // Label 2029: @85510 GIM_Try, /*On fail goto*//*Label 2030*/ 85562, // Rule ID 1288 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 313:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1288, GIR_Done, // Label 2030: @85562 GIM_Try, /*On fail goto*//*Label 2031*/ 85614, // Rule ID 1289 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 313:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1289, GIR_Done, // Label 2031: @85614 GIM_Try, /*On fail goto*//*Label 2032*/ 85666, // Rule ID 1290 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 314:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1290, GIR_Done, // Label 2032: @85666 GIM_Try, /*On fail goto*//*Label 2033*/ 85718, // Rule ID 1291 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 314:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1291, GIR_Done, // Label 2033: @85718 GIM_Try, /*On fail goto*//*Label 2034*/ 85770, // Rule ID 1298 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 344:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1298, GIR_Done, // Label 2034: @85770 GIM_Try, /*On fail goto*//*Label 2035*/ 85822, // Rule ID 1299 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 344:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1299, GIR_Done, // Label 2035: @85822 GIM_Try, /*On fail goto*//*Label 2036*/ 85874, // Rule ID 1300 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 344:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1300, GIR_Done, // Label 2036: @85874 GIM_Try, /*On fail goto*//*Label 2037*/ 85926, // Rule ID 1301 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 346:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1301, GIR_Done, // Label 2037: @85926 GIM_Try, /*On fail goto*//*Label 2038*/ 85978, // Rule ID 1302 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 346:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1302, GIR_Done, // Label 2038: @85978 GIM_Try, /*On fail goto*//*Label 2039*/ 86030, // Rule ID 1303 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 346:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1303, GIR_Done, // Label 2039: @86030 GIM_Try, /*On fail goto*//*Label 2040*/ 86082, // Rule ID 1304 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[f64] } 350:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1304, GIR_Done, // Label 2040: @86082 GIM_Try, /*On fail goto*//*Label 2041*/ 86134, // Rule ID 1305 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[f32] } 350:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1305, GIR_Done, // Label 2041: @86134 GIM_Try, /*On fail goto*//*Label 2042*/ 86186, // Rule ID 1306 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[f16] } 350:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1306, GIR_Done, // Label 2042: @86186 GIM_Try, /*On fail goto*//*Label 2043*/ 86238, // Rule ID 1307 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 389:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1307, GIR_Done, // Label 2043: @86238 GIM_Try, /*On fail goto*//*Label 2044*/ 86290, // Rule ID 1308 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 390:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1308, GIR_Done, // Label 2044: @86290 GIM_Try, /*On fail goto*//*Label 2045*/ 86342, // Rule ID 1309 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 394:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1309, GIR_Done, // Label 2045: @86342 GIM_Try, /*On fail goto*//*Label 2046*/ 86394, // Rule ID 1310 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 395:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1310, GIR_Done, // Label 2046: @86394 GIM_Try, /*On fail goto*//*Label 2047*/ 86446, // Rule ID 1311 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 398:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1311, GIR_Done, // Label 2047: @86446 GIM_Try, /*On fail goto*//*Label 2048*/ 86498, // Rule ID 1312 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 402:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1312, GIR_Done, // Label 2048: @86498 GIM_Try, /*On fail goto*//*Label 2049*/ 86550, // Rule ID 1313 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 406:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1313, GIR_Done, // Label 2049: @86550 GIM_Try, /*On fail goto*//*Label 2050*/ 86602, // Rule ID 1314 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 407:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1314, GIR_Done, // Label 2050: @86602 GIM_Try, /*On fail goto*//*Label 2051*/ 86654, // Rule ID 1316 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 442:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1316, GIR_Done, // Label 2051: @86654 GIM_Try, /*On fail goto*//*Label 2052*/ 86706, // Rule ID 1317 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 443:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1317, GIR_Done, // Label 2052: @86706 GIM_Try, /*On fail goto*//*Label 2053*/ 86758, // Rule ID 1318 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 445:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1318, GIR_Done, // Label 2053: @86758 GIM_Try, /*On fail goto*//*Label 2054*/ 86810, // Rule ID 1319 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 447:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1319, GIR_Done, // Label 2054: @86810 GIM_Try, /*On fail goto*//*Label 2055*/ 86862, // Rule ID 1320 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 451:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1320, GIR_Done, // Label 2055: @86862 GIM_Try, /*On fail goto*//*Label 2056*/ 86914, // Rule ID 1321 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 453:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1321, GIR_Done, // Label 2056: @86914 GIM_Try, /*On fail goto*//*Label 2057*/ 86966, // Rule ID 1322 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 392:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1322, GIR_Done, // Label 2057: @86966 GIM_Try, /*On fail goto*//*Label 2058*/ 87018, // Rule ID 1335 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 419:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1335, GIR_Done, // Label 2058: @87018 GIM_Try, /*On fail goto*//*Label 2059*/ 87070, // Rule ID 1336 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 419:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1336, GIR_Done, // Label 2059: @87070 GIM_Try, /*On fail goto*//*Label 2060*/ 87122, // Rule ID 1341 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 455:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1341, GIR_Done, // Label 2060: @87122 GIM_Try, /*On fail goto*//*Label 2061*/ 87174, // Rule ID 1342 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 455:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1342, GIR_Done, // Label 2061: @87174 GIM_Try, /*On fail goto*//*Label 2062*/ 87226, // Rule ID 1343 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 309:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1343, GIR_Done, // Label 2062: @87226 GIM_Try, /*On fail goto*//*Label 2063*/ 87278, // Rule ID 1344 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 309:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1344, GIR_Done, // Label 2063: @87278 GIM_Try, /*On fail goto*//*Label 2064*/ 87330, // Rule ID 1345 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 309:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1345, GIR_Done, // Label 2064: @87330 GIM_Try, /*On fail goto*//*Label 2065*/ 87382, // Rule ID 1346 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 418:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1346, GIR_Done, // Label 2065: @87382 GIM_Try, /*On fail goto*//*Label 2066*/ 87434, // Rule ID 1347 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 418:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1347, GIR_Done, // Label 2066: @87434 GIM_Try, /*On fail goto*//*Label 2067*/ 87486, // Rule ID 1348 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 418:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1348, GIR_Done, // Label 2067: @87486 GIM_Try, /*On fail goto*//*Label 2068*/ 87538, // Rule ID 1349 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 366:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1349, GIR_Done, // Label 2068: @87538 GIM_Try, /*On fail goto*//*Label 2069*/ 87590, // Rule ID 1350 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 366:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1350, GIR_Done, // Label 2069: @87590 GIM_Try, /*On fail goto*//*Label 2070*/ 87642, // Rule ID 1351 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 366:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1351, GIR_Done, // Label 2070: @87642 GIM_Try, /*On fail goto*//*Label 2071*/ 87694, // Rule ID 1352 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 369:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1352, GIR_Done, // Label 2071: @87694 GIM_Try, /*On fail goto*//*Label 2072*/ 87746, // Rule ID 1353 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 369:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1353, GIR_Done, // Label 2072: @87746 GIM_Try, /*On fail goto*//*Label 2073*/ 87798, // Rule ID 1354 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 369:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1354, GIR_Done, // Label 2073: @87798 GIM_Try, /*On fail goto*//*Label 2074*/ 87850, // Rule ID 1355 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 364:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULLv8i8:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1355, GIR_Done, // Label 2074: @87850 GIM_Try, /*On fail goto*//*Label 2075*/ 87902, // Rule ID 1392 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 387:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1392, GIR_Done, // Label 2075: @87902 GIM_Try, /*On fail goto*//*Label 2076*/ 87954, // Rule ID 1394 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 387:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1394, GIR_Done, // Label 2076: @87954 GIM_Try, /*On fail goto*//*Label 2077*/ 88006, // Rule ID 1396 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 387:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1396, GIR_Done, // Label 2077: @88006 GIM_Try, /*On fail goto*//*Label 2078*/ 88058, // Rule ID 1406 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 391:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1406, GIR_Done, // Label 2078: @88058 GIM_Try, /*On fail goto*//*Label 2079*/ 88110, // Rule ID 1408 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 391:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1408, GIR_Done, // Label 2079: @88110 GIM_Try, /*On fail goto*//*Label 2080*/ 88162, // Rule ID 1452 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 441:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1452, GIR_Done, // Label 2080: @88162 GIM_Try, /*On fail goto*//*Label 2081*/ 88214, // Rule ID 1454 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1454, GIR_Done, // Label 2081: @88214 GIM_Try, /*On fail goto*//*Label 2082*/ 88266, // Rule ID 1456 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1456, GIR_Done, // Label 2082: @88266 GIM_Try, /*On fail goto*//*Label 2083*/ 88318, // Rule ID 1826 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aese, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 281:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESErr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1826, GIR_Done, // Label 2083: @88318 GIM_Try, /*On fail goto*//*Label 2084*/ 88370, // Rule ID 1827 // GIM_CheckFeatures, GIFBS_HasAES, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 280:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1827, GIR_Done, // Label 2084: @88370 GIM_Try, /*On fail goto*//*Label 2085*/ 88422, // Rule ID 1838 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 289:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU1rr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1838, GIR_Done, // Label 2085: @88422 GIM_Try, /*On fail goto*//*Label 2086*/ 88474, // Rule ID 1839 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 292:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU0rr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1839, GIR_Done, // Label 2086: @88474 GIM_Try, /*On fail goto*//*Label 2087*/ 88526, // Rule ID 1886 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 389:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1886, GIR_Done, // Label 2087: @88526 GIM_Try, /*On fail goto*//*Label 2088*/ 88578, // Rule ID 1887 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 389:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1887, GIR_Done, // Label 2088: @88578 GIM_Try, /*On fail goto*//*Label 2089*/ 88630, // Rule ID 1888 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 470:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1888, GIR_Done, // Label 2089: @88630 GIM_Try, /*On fail goto*//*Label 2090*/ 88682, // Rule ID 1889 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 313:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1889, GIR_Done, // Label 2090: @88682 GIM_Try, /*On fail goto*//*Label 2091*/ 88734, // Rule ID 1894 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 419:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1894, GIR_Done, // Label 2091: @88734 GIM_Try, /*On fail goto*//*Label 2092*/ 88789, // Rule ID 2316 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 457:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2316, GIR_Done, // Label 2092: @88789 GIM_Try, /*On fail goto*//*Label 2093*/ 88844, // Rule ID 2317 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 456:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2317, GIR_Done, // Label 2093: @88844 GIM_Try, /*On fail goto*//*Label 2094*/ 88899, // Rule ID 2318 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 457:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2318, GIR_Done, // Label 2094: @88899 GIM_Try, /*On fail goto*//*Label 2095*/ 88954, // Rule ID 2319 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 456:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2319, GIR_Done, // Label 2095: @88954 GIM_Try, /*On fail goto*//*Label 2096*/ 89009, // Rule ID 2320 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 457:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2320, GIR_Done, // Label 2096: @89009 GIM_Try, /*On fail goto*//*Label 2097*/ 89064, // Rule ID 2321 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 456:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2321, GIR_Done, // Label 2097: @89064 GIM_Try, /*On fail goto*//*Label 2098*/ 89119, // Rule ID 2322 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 457:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2322, GIR_Done, // Label 2098: @89119 GIM_Try, /*On fail goto*//*Label 2099*/ 89174, // Rule ID 2323 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 456:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2323, GIR_Done, // Label 2099: @89174 GIM_Try, /*On fail goto*//*Label 2100*/ 89229, // Rule ID 2324 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 457:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2324, GIR_Done, // Label 2100: @89229 GIM_Try, /*On fail goto*//*Label 2101*/ 89284, // Rule ID 2325 // GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v2f64] } 456:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2325, GIR_Done, // Label 2101: @89284 GIM_Try, /*On fail goto*//*Label 2102*/ 89334, // Rule ID 2351 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 820:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2351, GIR_Done, // Label 2102: @89334 GIM_Try, /*On fail goto*//*Label 2103*/ 89384, // Rule ID 2352 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 820:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2352, GIR_Done, // Label 2103: @89384 GIM_Try, /*On fail goto*//*Label 2104*/ 89434, // Rule ID 2353 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 467:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2353, GIR_Done, // Label 2104: @89434 GIM_Try, /*On fail goto*//*Label 2105*/ 89484, // Rule ID 2354 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 467:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2354, GIR_Done, // Label 2105: @89484 GIM_Try, /*On fail goto*//*Label 2106*/ 89534, // Rule ID 2966 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 312:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2966, GIR_Done, // Label 2106: @89534 GIM_Try, /*On fail goto*//*Label 2107*/ 89586, // Rule ID 2970 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 314:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2970, GIR_Done, // Label 2107: @89586 GIM_Try, /*On fail goto*//*Label 2108*/ 89638, // Rule ID 2974 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 344:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2974, GIR_Done, // Label 2108: @89638 GIM_Try, /*On fail goto*//*Label 2109*/ 89690, // Rule ID 2975 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 346:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2975, GIR_Done, // Label 2109: @89690 GIM_Try, /*On fail goto*//*Label 2110*/ 89742, // Rule ID 2976 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1f64] } 350:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2976, GIR_Done, // Label 2110: @89742 GIM_Try, /*On fail goto*//*Label 2111*/ 89794, // Rule ID 2977 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 395:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2977, GIR_Done, // Label 2111: @89794 GIM_Try, /*On fail goto*//*Label 2112*/ 89846, // Rule ID 2978 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 395:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2978, GIR_Done, // Label 2112: @89846 GIM_Try, /*On fail goto*//*Label 2113*/ 89898, // Rule ID 2979 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 398:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2979, GIR_Done, // Label 2113: @89898 GIM_Try, /*On fail goto*//*Label 2114*/ 89950, // Rule ID 2980 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 398:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2980, GIR_Done, // Label 2114: @89950 GIM_Try, /*On fail goto*//*Label 2115*/ 90002, // Rule ID 2981 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 402:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2981, GIR_Done, // Label 2115: @90002 GIM_Try, /*On fail goto*//*Label 2116*/ 90054, // Rule ID 2982 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 402:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2982, GIR_Done, // Label 2116: @90054 GIM_Try, /*On fail goto*//*Label 2117*/ 90106, // Rule ID 2983 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 442:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2983, GIR_Done, // Label 2117: @90106 GIM_Try, /*On fail goto*//*Label 2118*/ 90158, // Rule ID 2984 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 442:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2984, GIR_Done, // Label 2118: @90158 GIM_Try, /*On fail goto*//*Label 2119*/ 90210, // Rule ID 2985 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 443:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2985, GIR_Done, // Label 2119: @90210 GIM_Try, /*On fail goto*//*Label 2120*/ 90262, // Rule ID 2986 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 443:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2986, GIR_Done, // Label 2120: @90262 GIM_Try, /*On fail goto*//*Label 2121*/ 90314, // Rule ID 2987 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 445:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2987, GIR_Done, // Label 2121: @90314 GIM_Try, /*On fail goto*//*Label 2122*/ 90366, // Rule ID 2988 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 445:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2988, GIR_Done, // Label 2122: @90366 GIM_Try, /*On fail goto*//*Label 2123*/ 90418, // Rule ID 2989 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 447:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2989, GIR_Done, // Label 2123: @90418 GIM_Try, /*On fail goto*//*Label 2124*/ 90470, // Rule ID 2990 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 447:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2990, GIR_Done, // Label 2124: @90470 GIM_Try, /*On fail goto*//*Label 2125*/ 90522, // Rule ID 3005 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 455:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3005, GIR_Done, // Label 2125: @90522 GIM_Try, /*On fail goto*//*Label 2126*/ 90572, // Rule ID 3101 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 365:{ *:[iPTR] }, V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) => (PMULLv1i64:{ *:[v16i8] } V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3101, GIR_Done, // Label 2126: @90572 GIM_Try, /*On fail goto*//*Label 2127*/ 90622, // Rule ID 3175 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 420:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv8i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3175, GIR_Done, // Label 2127: @90622 GIM_Try, /*On fail goto*//*Label 2128*/ 90672, // Rule ID 3176 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 420:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv16i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ri GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3176, GIR_Done, // Label 2128: @90672 GIM_Try, /*On fail goto*//*Label 2129*/ 90767, // Rule ID 3515 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 313:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGE16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3515, GIR_Done, // Label 2129: @90767 GIM_Try, /*On fail goto*//*Label 2130*/ 90862, // Rule ID 3516 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (intrinsic_wo_chain:{ *:[i32] } 314:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGT16, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/7, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC FPR16*/1, // GIR_Coverage, 3516, GIR_Done, // Label 2130: @90862 GIM_Try, /*On fail goto*//*Label 2131*/ 90912, // Rule ID 4043 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 407:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4043, GIR_Done, // Label 2131: @90912 GIM_Try, /*On fail goto*//*Label 2132*/ 90962, // Rule ID 4044 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 453:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4044, GIR_Done, // Label 2132: @90962 GIM_Try, /*On fail goto*//*Label 2133*/ 91012, // Rule ID 4045 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 406:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4045, GIR_Done, // Label 2133: @91012 GIM_Try, /*On fail goto*//*Label 2134*/ 91062, // Rule ID 4046 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4046, GIR_Done, // Label 2134: @91062 GIM_Try, /*On fail goto*//*Label 2135*/ 91114, // Rule ID 108 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_gmi, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_wo_chain:{ *:[i64] } 298:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::GMI, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 108, GIR_Done, // Label 2135: @91114 GIM_Try, /*On fail goto*//*Label 2136*/ 91166, // Rule ID 109 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_subp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // MIs[0] Rm GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_wo_chain:{ *:[i64] } 479:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 109, GIR_Done, // Label 2136: @91166 GIM_Reject, // Label 1679: @91167 GIM_Try, /*On fail goto*//*Label 2137*/ 93858, GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_Try, /*On fail goto*//*Label 2138*/ 91243, // Rule ID 1700 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 465:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1700, GIR_Done, // Label 2138: @91243 GIM_Try, /*On fail goto*//*Label 2139*/ 91314, // Rule ID 1701 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 465:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1701, GIR_Done, // Label 2139: @91314 GIM_Try, /*On fail goto*//*Label 2140*/ 91385, // Rule ID 1702 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 465:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1702, GIR_Done, // Label 2140: @91385 GIM_Try, /*On fail goto*//*Label 2141*/ 91456, // Rule ID 1703 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 465:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1703, GIR_Done, // Label 2141: @91456 GIM_Try, /*On fail goto*//*Label 2142*/ 91527, // Rule ID 1704 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 465:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1704, GIR_Done, // Label 2142: @91527 GIM_Try, /*On fail goto*//*Label 2143*/ 91598, // Rule ID 1705 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 465:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1705, GIR_Done, // Label 2143: @91598 GIM_Try, /*On fail goto*//*Label 2144*/ 91669, // Rule ID 1706 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 465:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLIv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1706, GIR_Done, // Label 2144: @91669 GIM_Try, /*On fail goto*//*Label 2145*/ 91740, // Rule ID 1733 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i8] } 466:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1733, GIR_Done, // Label 2145: @91740 GIM_Try, /*On fail goto*//*Label 2146*/ 91811, // Rule ID 1734 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 466:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv16i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1734, GIR_Done, // Label 2146: @91811 GIM_Try, /*On fail goto*//*Label 2147*/ 91882, // Rule ID 1735 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 466:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1735, GIR_Done, // Label 2147: @91882 GIM_Try, /*On fail goto*//*Label 2148*/ 91953, // Rule ID 1736 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 466:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv8i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1736, GIR_Done, // Label 2148: @91953 GIM_Try, /*On fail goto*//*Label 2149*/ 92024, // Rule ID 1737 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 466:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1737, GIR_Done, // Label 2149: @92024 GIM_Try, /*On fail goto*//*Label 2150*/ 92095, // Rule ID 1738 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 466:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv4i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1738, GIR_Done, // Label 2150: @92095 GIM_Try, /*On fail goto*//*Label 2151*/ 92166, // Rule ID 1739 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i64] } 466:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRIv2i64_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1739, GIR_Done, // Label 2151: @92166 GIM_Try, /*On fail goto*//*Label 2152*/ 92237, // Rule ID 2014 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[nxv8f16] } 619:{ *:[iPTR] }, ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (imm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_H:{ *:[nxv8f16] } ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2014, GIR_Done, // Label 2152: @92237 GIM_Try, /*On fail goto*//*Label 2153*/ 92308, // Rule ID 2015 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[nxv4f32] } 619:{ *:[iPTR] }, ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (imm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_S:{ *:[nxv4f32] } ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_S, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2015, GIR_Done, // Label 2153: @92308 GIM_Try, /*On fail goto*//*Label 2154*/ 92379, // Rule ID 2016 // GIM_CheckFeatures, GIFBS_HasSVE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_ftmad_x, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::ZPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::ZPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[nxv2f64] } 619:{ *:[iPTR] }, ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (imm:{ *:[i32] })<>:$imm) => (FTMAD_ZZI_D:{ *:[nxv2f64] } ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FTMAD_ZZI_D, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Zdn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Zn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Zm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2016, GIR_Done, // Label 2154: @92379 GIM_Try, /*On fail goto*//*Label 2155*/ 92448, // Rule ID 3529 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftL64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 465:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SLId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SLId, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3529, GIR_Done, // Label 2155: @92448 GIM_Try, /*On fail goto*//*Label 2156*/ 92517, // Rule ID 3542 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v1i64] } 466:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SRId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRId, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3542, GIR_Done, // Label 2156: @92517 GIM_Try, /*On fail goto*//*Label 2157*/ 92581, // Rule ID 19 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 377:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 19, GIR_Done, // Label 2157: @92581 GIM_Try, /*On fail goto*//*Label 2158*/ 92645, // Rule ID 20 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 377:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 20, GIR_Done, // Label 2158: @92645 GIM_Try, /*On fail goto*//*Label 2159*/ 92709, // Rule ID 21 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 432:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 21, GIR_Done, // Label 2159: @92709 GIM_Try, /*On fail goto*//*Label 2160*/ 92773, // Rule ID 22 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 432:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 22, GIR_Done, // Label 2160: @92773 GIM_Try, /*On fail goto*//*Label 2161*/ 92837, // Rule ID 27 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 340:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 27, GIR_Done, // Label 2161: @92837 GIM_Try, /*On fail goto*//*Label 2162*/ 92901, // Rule ID 28 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 340:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 28, GIR_Done, // Label 2162: @92901 GIM_Try, /*On fail goto*//*Label 2163*/ 92965, // Rule ID 29 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 342:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 29, GIR_Done, // Label 2163: @92965 GIM_Try, /*On fail goto*//*Label 2164*/ 93029, // Rule ID 30 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 342:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 30, GIR_Done, // Label 2164: @93029 GIM_Try, /*On fail goto*//*Label 2165*/ 93093, // Rule ID 31 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 341:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 31, GIR_Done, // Label 2165: @93093 GIM_Try, /*On fail goto*//*Label 2166*/ 93157, // Rule ID 32 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 341:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 32, GIR_Done, // Label 2166: @93157 GIM_Try, /*On fail goto*//*Label 2167*/ 93221, // Rule ID 33 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 343:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 33, GIR_Done, // Label 2167: @93221 GIM_Try, /*On fail goto*//*Label 2168*/ 93285, // Rule ID 34 // GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 343:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 34, GIR_Done, // Label 2168: @93285 GIM_Try, /*On fail goto*//*Label 2169*/ 93349, // Rule ID 1830 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1c, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 284:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Crrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1830, GIR_Done, // Label 2169: @93349 GIM_Try, /*On fail goto*//*Label 2170*/ 93413, // Rule ID 1831 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1p, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 287:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Prrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1831, GIR_Done, // Label 2170: @93413 GIM_Try, /*On fail goto*//*Label 2171*/ 93477, // Rule ID 1832 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1m, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 286:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Mrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1832, GIR_Done, // Label 2171: @93477 GIM_Try, /*On fail goto*//*Label 2172*/ 93541, // Rule ID 1833 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 288:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU0rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1833, GIR_Done, // Label 2172: @93541 GIM_Try, /*On fail goto*//*Label 2173*/ 93605, // Rule ID 1834 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 290:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256Hrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1834, GIR_Done, // Label 2173: @93605 GIM_Try, /*On fail goto*//*Label 2174*/ 93669, // Rule ID 1835 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 291:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256H2rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1835, GIR_Done, // Label 2174: @93669 GIM_Try, /*On fail goto*//*Label 2175*/ 93733, // Rule ID 1836 // GIM_CheckFeatures, GIFBS_HasSHA2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 293:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU1rrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1836, GIR_Done, // Label 2175: @93733 GIM_Try, /*On fail goto*//*Label 2176*/ 93795, // Rule ID 3177 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 424:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv8i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ri GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3177, GIR_Done, // Label 2176: @93795 GIM_Try, /*On fail goto*//*Label 2177*/ 93857, // Rule ID 3178 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 424:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv16i8One, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3178, GIR_Done, // Label 2177: @93857 GIM_Reject, // Label 2137: @93858 GIM_Try, /*On fail goto*//*Label 2178*/ 94204, GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, GIM_Try, /*On fail goto*//*Label 2179*/ 93951, // Rule ID 3257 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v16i8] } 458:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3257, GIR_Done, // Label 2179: @93951 GIM_Try, /*On fail goto*//*Label 2180*/ 94035, // Rule ID 3258 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v8i16] } 458:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3258, GIR_Done, // Label 2180: @94035 GIM_Try, /*On fail goto*//*Label 2181*/ 94119, // Rule ID 3259 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v4i32] } 458:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3259, GIR_Done, // Label 2181: @94119 GIM_Try, /*On fail goto*//*Label 2182*/ 94203, // Rule ID 3260 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_wo_chain:{ *:[v2i64] } 458:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<>:$idx2) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<>:$idx2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3260, GIR_Done, // Label 2182: @94203 GIM_Reject, // Label 2178: @94204 GIM_Reject, // Label 30: @94205 GIM_Try, /*On fail goto*//*Label 2183*/ 94252, GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, GIM_Try, /*On fail goto*//*Label 2184*/ 94230, // Rule ID 48 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcommit, // (intrinsic_void 817:{ *:[iPTR] }) => (TCOMMIT) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCOMMIT, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 48, GIR_Done, // Label 2184: @94230 GIM_Try, /*On fail goto*//*Label 2185*/ 94251, // Rule ID 4147 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_clrex, // (intrinsic_void 269:{ *:[iPTR] }) => (CLREX 15:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLREX, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4147, GIR_Done, // Label 2185: @94251 GIM_Reject, // Label 2183: @94252 GIM_Try, /*On fail goto*//*Label 2186*/ 94497, GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, GIM_Try, /*On fail goto*//*Label 2187*/ 94295, // Rule ID 15 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 299:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (HINT (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 15, GIR_Done, // Label 2187: @94295 GIM_Try, /*On fail goto*//*Label 2188*/ 94333, // Rule ID 16 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 294:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (DMB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 16, GIR_Done, // Label 2188: @94333 GIM_Try, /*On fail goto*//*Label 2189*/ 94371, // Rule ID 17 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 295:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (DSB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 17, GIR_Done, // Label 2189: @94371 GIM_Try, /*On fail goto*//*Label 2190*/ 94409, // Rule ID 18 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 302:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$CRm) => (ISB (imm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 18, GIR_Done, // Label 2190: @94409 GIM_Try, /*On fail goto*//*Label 2191*/ 94436, // Rule ID 49 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcancel, // MIs[0] imm GIM_CheckIsImm, /*MI*/0, /*Op*/1, // (intrinsic_void 816:{ *:[iPTR] }, (timm:{ *:[i64] })<>:$imm) => (TCANCEL (timm:{ *:[i64] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCANCEL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 49, GIR_Done, // Label 2191: @94436 GIM_Try, /*On fail goto*//*Label 2192*/ 94468, // Rule ID 47 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_tstart, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 818:{ *:[iPTR] }) => (TSTART:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TSTART, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 47, GIR_Done, // Label 2192: @94468 GIM_Try, /*On fail goto*//*Label 2193*/ 94496, // Rule ID 50 // GIM_CheckFeatures, GIFBS_HasTME, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ttest, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 819:{ *:[iPTR] }) => (TTEST:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TTEST, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 50, GIR_Done, // Label 2193: @94496 GIM_Reject, // Label 2186: @94497 GIM_Try, /*On fail goto*//*Label 2194*/ 95071, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 2195*/ 94575, // Rule ID 4113 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4113, GIR_Done, // Label 2195: @94575 GIM_Try, /*On fail goto*//*Label 2196*/ 94648, // Rule ID 4114 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4114, GIR_Done, // Label 2196: @94648 GIM_Try, /*On fail goto*//*Label 2197*/ 94721, // Rule ID 4115 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4115, GIR_Done, // Label 2197: @94721 GIM_Try, /*On fail goto*//*Label 2198*/ 94766, // Rule ID 4116 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 307:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4116, GIR_Done, // Label 2198: @94766 GIM_Try, /*On fail goto*//*Label 2199*/ 94839, // Rule ID 4120 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4120, GIR_Done, // Label 2199: @94839 GIM_Try, /*On fail goto*//*Label 2200*/ 94912, // Rule ID 4121 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4121, GIR_Done, // Label 2200: @94912 GIM_Try, /*On fail goto*//*Label 2201*/ 94985, // Rule ID 4122 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 4122, GIR_Done, // Label 2201: @94985 GIM_Try, /*On fail goto*//*Label 2202*/ 95030, // Rule ID 4123 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 304:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<> => (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDAXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4123, GIR_Done, // Label 2202: @95030 GIM_Try, /*On fail goto*//*Label 2203*/ 95070, // Rule ID 2403 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg_sp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i64] } 301:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm) => (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRGstack, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddRegister, /*InsnID*/0, AArch64::SP, /*AddRegisterRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2403, GIR_Done, // Label 2203: @95070 GIM_Reject, // Label 2194: @95071 GIM_Try, /*On fail goto*//*Label 2204*/ 97020, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 2205*/ 95169, // Rule ID 4131 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4131, GIR_Done, // Label 2205: @95169 GIM_Try, /*On fail goto*//*Label 2206*/ 95262, // Rule ID 4132 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4132, GIR_Done, // Label 2206: @95262 GIM_Try, /*On fail goto*//*Label 2207*/ 95355, // Rule ID 4141 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4141, GIR_Done, // Label 2207: @95355 GIM_Try, /*On fail goto*//*Label 2208*/ 95448, // Rule ID 4142 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4142, GIR_Done, // Label 2208: @95448 GIM_Try, /*On fail goto*//*Label 2209*/ 95550, // Rule ID 4134 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4134, GIR_Done, // Label 2209: @95550 GIM_Try, /*On fail goto*//*Label 2210*/ 95652, // Rule ID 4135 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4135, GIR_Done, // Label 2210: @95652 GIM_Try, /*On fail goto*//*Label 2211*/ 95754, // Rule ID 4136 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4136, GIR_Done, // Label 2211: @95754 GIM_Try, /*On fail goto*//*Label 2212*/ 95856, // Rule ID 4144 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4144, GIR_Done, // Label 2212: @95856 GIM_Try, /*On fail goto*//*Label 2213*/ 95958, // Rule ID 4145 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4145, GIR_Done, // Label 2213: @95958 GIM_Try, /*On fail goto*//*Label 2214*/ 96060, // Rule ID 4146 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4146, GIR_Done, // Label 2214: @96060 GIM_Try, /*On fail goto*//*Label 2215*/ 96131, // Rule ID 4133 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4133, GIR_Done, // Label 2215: @96131 GIM_Try, /*On fail goto*//*Label 2216*/ 96202, // Rule ID 4143 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4143, GIR_Done, // Label 2216: @96202 GIM_Try, /*On fail goto*//*Label 2217*/ 96261, // Rule ID 14 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_space, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[i64] } 472:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) => (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SPACE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 14, GIR_Done, // Label 2217: @96261 GIM_Try, /*On fail goto*//*Label 2218*/ 96317, // Rule ID 45 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess, // MIs[0] Operand 1 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64noip_and_tcGPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, // MIs[0] accessinfo GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_void 136:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddRegister, /*InsnID*/1, AArch64::X9, /*AddRegisterRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 45, GIR_Done, // Label 2218: @96317 GIM_Try, /*On fail goto*//*Label 2219*/ 96373, // Rule ID 46 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess_shortgranules, // MIs[0] Operand 1 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64noip_and_tcGPR64RegClassID, // MIs[0] ptr GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, // MIs[0] accessinfo GIM_CheckIsImm, /*MI*/0, /*Op*/3, // (intrinsic_void 137:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddRegister, /*InsnID*/1, AArch64::X9, /*AddRegisterRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 46, GIR_Done, // Label 2219: @96373 GIM_Try, /*On fail goto*//*Label 2220*/ 96453, // Rule ID 4127 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4127, GIR_Done, // Label 2220: @96453 GIM_Try, /*On fail goto*//*Label 2221*/ 96533, // Rule ID 4128 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4128, GIR_Done, // Label 2221: @96533 GIM_Try, /*On fail goto*//*Label 2222*/ 96613, // Rule ID 4129 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4129, GIR_Done, // Label 2222: @96613 GIM_Try, /*On fail goto*//*Label 2223*/ 96670, // Rule ID 4130 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 478:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4130, GIR_Done, // Label 2223: @96670 GIM_Try, /*On fail goto*//*Label 2224*/ 96750, // Rule ID 4137 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4137, GIR_Done, // Label 2224: @96750 GIM_Try, /*On fail goto*//*Label 2225*/ 96830, // Rule ID 4138 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4138, GIR_Done, // Label 2225: @96830 GIM_Try, /*On fail goto*//*Label 2226*/ 96910, // Rule ID 4139 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR32*/6, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64*/17, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4139, GIR_Done, // Label 2226: @96910 GIM_Try, /*On fail goto*//*Label 2227*/ 96967, // Rule ID 4140 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // MIs[0] addr GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, // (intrinsic_w_chain:{ *:[i32] } 476:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<> => (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4140, GIR_Done, // Label 2227: @96967 GIM_Try, /*On fail goto*//*Label 2228*/ 97019, // Rule ID 107 // GIM_CheckFeatures, GIFBS_HasMTE, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, // (intrinsic_w_chain:{ *:[i64] } 300:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 107, GIR_Done, // Label 2228: @97019 GIM_Reject, // Label 2204: @97020 GIM_Reject, // Label 31: @97021 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 13, /*)*//*default:*//*Label 2233*/ 97200, /*GILLT_s64*//*Label 2229*/ 97038, 0, 0, 0, /*GILLT_v2s64*//*Label 2230*/ 97098, 0, 0, /*GILLT_v4s32*//*Label 2231*/ 97132, 0, 0, /*GILLT_v8s16*//*Label 2232*/ 97166, // Label 2229: @97038 GIM_Try, /*On fail goto*//*Label 2234*/ 97097, // Rule ID 3674 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 3674, GIR_Done, // Label 2234: @97097 GIM_Reject, // Label 2230: @97098 GIM_Try, /*On fail goto*//*Label 2235*/ 97131, // Rule ID 3563 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3563, GIR_Done, // Label 2235: @97131 GIM_Reject, // Label 2231: @97132 GIM_Try, /*On fail goto*//*Label 2236*/ 97165, // Rule ID 3560 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3560, GIR_Done, // Label 2236: @97165 GIM_Reject, // Label 2232: @97166 GIM_Try, /*On fail goto*//*Label 2237*/ 97199, // Rule ID 3557 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3557, GIR_Done, // Label 2237: @97199 GIM_Reject, // Label 2233: @97200 GIM_Reject, // Label 32: @97201 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2242*/ 97328, /*GILLT_s32*//*Label 2238*/ 97218, 0, 0, 0, /*GILLT_v2s32*//*Label 2239*/ 97256, 0, 0, /*GILLT_v4s16*//*Label 2240*/ 97280, 0, 0, /*GILLT_v8s8*//*Label 2241*/ 97304, // Label 2238: @97218 GIM_Try, /*On fail goto*//*Label 2243*/ 97255, // Rule ID 3694 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/15, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32sp*/7, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GPR64sp*/18, // GIR_Coverage, 3694, GIR_Done, // Label 2243: @97255 GIM_Reject, // Label 2239: @97256 GIM_Try, /*On fail goto*//*Label 2244*/ 97279, // Rule ID 864 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) => (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 864, GIR_Done, // Label 2244: @97279 GIM_Reject, // Label 2240: @97280 GIM_Try, /*On fail goto*//*Label 2245*/ 97303, // Rule ID 863 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) => (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 863, GIR_Done, // Label 2245: @97303 GIM_Reject, // Label 2241: @97304 GIM_Try, /*On fail goto*//*Label 2246*/ 97327, // Rule ID 862 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) => (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 862, GIR_Done, // Label 2246: @97327 GIM_Reject, // Label 2242: @97328 GIM_Reject, // Label 33: @97329 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2249*/ 97436, /*GILLT_s32*//*Label 2247*/ 97337, /*GILLT_s64*//*Label 2248*/ 97359, // Label 2247: @97337 GIM_Try, /*On fail goto*//*Label 2250*/ 97358, // Rule ID 51 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] }):$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi32imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 51, GIR_Done, // Label 2250: @97358 GIM_Reject, // Label 2248: @97359 GIM_Try, /*On fail goto*//*Label 2251*/ 97414, // Rule ID 2328 // GIM_CheckFeatures, GIFBS_OptimizedGISelOrOtherSelector, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i64] })<>:$src => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GICR_renderTruncImm, // src GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/15, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GPR32*/6, // GIR_Coverage, 2328, GIR_Done, // Label 2251: @97414 GIM_Try, /*On fail goto*//*Label 2252*/ 97435, // Rule ID 52 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i64] }):$src => (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi64imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 52, GIR_Done, // Label 2252: @97435 GIM_Reject, // Label 2249: @97436 GIM_Reject, // Label 34: @97437 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2256*/ 97514, /*GILLT_s16*//*Label 2253*/ 97446, /*GILLT_s32*//*Label 2254*/ 97470, /*GILLT_s64*//*Label 2255*/ 97492, // Label 2253: @97446 GIM_Try, /*On fail goto*//*Label 2257*/ 97469, // Rule ID 454 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f16] })<> => (FMOVH0:{ *:[f16] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVH0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 454, GIR_Done, // Label 2257: @97469 GIM_Reject, // Label 2254: @97470 GIM_Try, /*On fail goto*//*Label 2258*/ 97491, // Rule ID 455 // GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f32] })<> => (FMOVS0:{ *:[f32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVS0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 455, GIR_Done, // Label 2258: @97491 GIM_Reject, // Label 2255: @97492 GIM_Try, /*On fail goto*//*Label 2259*/ 97513, // Rule ID 456 // GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f64] })<> => (FMOVD0:{ *:[f64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVD0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 456, GIR_Done, // Label 2259: @97513 GIM_Reject, // Label 2256: @97514 GIM_Reject, // Label 35: @97515 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 13, /*)*//*default:*//*Label 2264*/ 97773, /*GILLT_s64*//*Label 2260*/ 97532, 0, 0, 0, /*GILLT_v2s64*//*Label 2261*/ 97671, 0, 0, /*GILLT_v4s32*//*Label 2262*/ 97705, 0, 0, /*GILLT_v8s16*//*Label 2263*/ 97739, // Label 2260: @97532 GIM_Try, /*On fail goto*//*Label 2265*/ 97670, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2266*/ 97596, // Rule ID 3233 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx)) => (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi32to64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3233, GIR_Done, // Label 2266: @97596 GIM_Try, /*On fail goto*//*Label 2267*/ 97669, // Rule ID 3676 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3676, GIR_Done, // Label 2267: @97669 GIM_Reject, // Label 2265: @97670 GIM_Reject, // Label 2261: @97671 GIM_Try, /*On fail goto*//*Label 2268*/ 97704, // Rule ID 3561 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3561, GIR_Done, // Label 2268: @97704 GIM_Reject, // Label 2262: @97705 GIM_Try, /*On fail goto*//*Label 2269*/ 97738, // Rule ID 3558 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3558, GIR_Done, // Label 2269: @97738 GIM_Reject, // Label 2263: @97739 GIM_Try, /*On fail goto*//*Label 2270*/ 97772, // Rule ID 3555 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3555, GIR_Done, // Label 2270: @97772 GIM_Reject, // Label 2264: @97773 GIM_Reject, // Label 36: @97774 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 13, /*)*//*default:*//*Label 2274*/ 98234, /*GILLT_v2s64*//*Label 2271*/ 97787, 0, 0, /*GILLT_v4s32*//*Label 2272*/ 97936, 0, 0, /*GILLT_v8s16*//*Label 2273*/ 98085, // Label 2271: @97787 GIM_Try, /*On fail goto*//*Label 2275*/ 97935, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2276*/ 97853, // Rule ID 570 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 570, GIR_Done, // Label 2276: @97853 GIM_Try, /*On fail goto*//*Label 2277*/ 97909, // Rule ID 1366 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv2i32_v2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1366, GIR_Done, // Label 2277: @97909 GIM_Try, /*On fail goto*//*Label 2278*/ 97934, // Rule ID 3562 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3562, GIR_Done, // Label 2278: @97934 GIM_Reject, // Label 2275: @97935 GIM_Reject, // Label 2272: @97936 GIM_Try, /*On fail goto*//*Label 2279*/ 98084, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2280*/ 98002, // Rule ID 568 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 568, GIR_Done, // Label 2280: @98002 GIM_Try, /*On fail goto*//*Label 2281*/ 98058, // Rule ID 1364 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv4i16_v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1364, GIR_Done, // Label 2281: @98058 GIM_Try, /*On fail goto*//*Label 2282*/ 98083, // Rule ID 3559 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3559, GIR_Done, // Label 2282: @98083 GIM_Reject, // Label 2279: @98084 GIM_Reject, // Label 2273: @98085 GIM_Try, /*On fail goto*//*Label 2283*/ 98233, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2284*/ 98151, // Rule ID 566 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 566, GIR_Done, // Label 2284: @98151 GIM_Try, /*On fail goto*//*Label 2285*/ 98207, // Rule ID 1362 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 370:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv8i8_v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1362, GIR_Done, // Label 2285: @98207 GIM_Try, /*On fail goto*//*Label 2286*/ 98232, // Rule ID 3556 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3556, GIR_Done, // Label 2286: @98232 GIM_Reject, // Label 2283: @98233 GIM_Reject, // Label 2274: @98234 GIM_Reject, // Label 37: @98235 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2289*/ 98547, /*GILLT_s32*//*Label 2287*/ 98243, /*GILLT_s64*//*Label 2288*/ 98380, // Label 2287: @98243 GIM_Try, /*On fail goto*//*Label 2290*/ 98379, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2291*/ 98300, // Rule ID 2357 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2357, GIR_Done, // Label 2291: @98300 GIM_Try, /*On fail goto*//*Label 2292*/ 98339, // Rule ID 2358 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2358, GIR_Done, // Label 2292: @98339 GIM_Try, /*On fail goto*//*Label 2293*/ 98378, // Rule ID 2356 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2356, GIR_Done, // Label 2293: @98378 GIM_Reject, // Label 2290: @98379 GIM_Reject, // Label 2288: @98380 GIM_Try, /*On fail goto*//*Label 2294*/ 98546, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2295*/ 98465, // Rule ID 2359 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2359, GIR_Done, // Label 2295: @98465 GIM_Try, /*On fail goto*//*Label 2296*/ 98532, // Rule ID 2360 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2360, GIR_Done, // Label 2296: @98532 GIM_Try, /*On fail goto*//*Label 2297*/ 98545, // Rule ID 90 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSLVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 90, GIR_Done, // Label 2297: @98545 GIM_Reject, // Label 2294: @98546 GIM_Reject, // Label 2289: @98547 GIM_Reject, // Label 38: @98548 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2300*/ 98932, /*GILLT_s32*//*Label 2298*/ 98556, /*GILLT_s64*//*Label 2299*/ 98729, // Label 2298: @98556 GIM_Try, /*On fail goto*//*Label 2301*/ 98728, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2302*/ 98610, // Rule ID 2420 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2420, GIR_Done, // Label 2302: @98610 GIM_Try, /*On fail goto*//*Label 2303*/ 98649, // Rule ID 2363 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2363, GIR_Done, // Label 2303: @98649 GIM_Try, /*On fail goto*//*Label 2304*/ 98688, // Rule ID 2364 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2364, GIR_Done, // Label 2304: @98688 GIM_Try, /*On fail goto*//*Label 2305*/ 98727, // Rule ID 2362 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2362, GIR_Done, // Label 2305: @98727 GIM_Reject, // Label 2301: @98728 GIM_Reject, // Label 2299: @98729 GIM_Try, /*On fail goto*//*Label 2306*/ 98931, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2307*/ 98783, // Rule ID 2421 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm, 63:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/63, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2421, GIR_Done, // Label 2307: @98783 GIM_Try, /*On fail goto*//*Label 2308*/ 98850, // Rule ID 2365 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2365, GIR_Done, // Label 2308: @98850 GIM_Try, /*On fail goto*//*Label 2309*/ 98917, // Rule ID 2366 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2366, GIR_Done, // Label 2309: @98917 GIM_Try, /*On fail goto*//*Label 2310*/ 98930, // Rule ID 91 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSRVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 91, GIR_Done, // Label 2310: @98930 GIM_Reject, // Label 2306: @98931 GIM_Reject, // Label 2300: @98932 GIM_Reject, // Label 39: @98933 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2313*/ 99427, /*GILLT_s32*//*Label 2311*/ 98941, /*GILLT_s64*//*Label 2312*/ 99114, // Label 2311: @98941 GIM_Try, /*On fail goto*//*Label 2314*/ 99113, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2315*/ 98995, // Rule ID 2418 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2418, GIR_Done, // Label 2315: @98995 GIM_Try, /*On fail goto*//*Label 2316*/ 99034, // Rule ID 1848 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1848, GIR_Done, // Label 2316: @99034 GIM_Try, /*On fail goto*//*Label 2317*/ 99073, // Rule ID 1849 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1849, GIR_Done, // Label 2317: @99073 GIM_Try, /*On fail goto*//*Label 2318*/ 99112, // Rule ID 1847 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1847, GIR_Done, // Label 2318: @99112 GIM_Reject, // Label 2314: @99113 GIM_Reject, // Label 2312: @99114 GIM_Try, /*On fail goto*//*Label 2319*/ 99426, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2320*/ 99226, // Rule ID 3693 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<>:$imm) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<>:$imm, 31:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/31, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3693, GIR_Done, // Label 2320: @99226 GIM_Try, /*On fail goto*//*Label 2321*/ 99266, // Rule ID 2419 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm) => (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$imm, 63:{ *:[i64] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/63, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2419, GIR_Done, // Label 2321: @99266 GIM_Try, /*On fail goto*//*Label 2322*/ 99337, // Rule ID 1850 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1850, GIR_Done, // Label 2322: @99337 GIM_Try, /*On fail goto*//*Label 2323*/ 99408, // Rule ID 1851 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GPR64all*/15, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GPR32*/6, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1851, GIR_Done, // Label 2323: @99408 GIM_Try, /*On fail goto*//*Label 2324*/ 99425, // Rule ID 89 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ASRVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 89, GIR_Done, // Label 2324: @99425 GIM_Reject, // Label 2319: @99426 GIM_Reject, // Label 2313: @99427 GIM_Reject, // Label 40: @99428 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 15, /*)*//*default:*//*Label 2329*/ 99864, /*GILLT_s64*//*Label 2325*/ 99447, 0, 0, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2326*/ 99477, 0, 0, /*GILLT_v8s16*//*Label 2327*/ 99606, 0, /*GILLT_v16s8*//*Label 2328*/ 99735, // Label 2325: @99447 GIM_Try, /*On fail goto*//*Label 2330*/ 99476, // Rule ID 98 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMULHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 98, GIR_Done, // Label 2330: @99476 GIM_Reject, // Label 2326: @99477 GIM_Try, /*On fail goto*//*Label 2331*/ 99605, // Rule ID 3702 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv4i32_v2i64, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv2i32_v2i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3702, GIR_Done, // Label 2331: @99605 GIM_Reject, // Label 2327: @99606 GIM_Try, /*On fail goto*//*Label 2332*/ 99734, // Rule ID 3701 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv8i16_v4i32, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv4i16_v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3701, GIR_Done, // Label 2332: @99734 GIM_Reject, // Label 2328: @99735 GIM_Try, /*On fail goto*//*Label 2333*/ 99863, // Rule ID 3700 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv16i8_v8i16, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv8i8_v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3700, GIR_Done, // Label 2333: @99863 GIM_Reject, // Label 2329: @99864 GIM_Reject, // Label 41: @99865 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 15, /*)*//*default:*//*Label 2338*/ 100301, /*GILLT_s64*//*Label 2334*/ 99884, 0, 0, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2335*/ 99914, 0, 0, /*GILLT_v8s16*//*Label 2336*/ 100043, 0, /*GILLT_v16s8*//*Label 2337*/ 100172, // Label 2334: @99884 GIM_Try, /*On fail goto*//*Label 2339*/ 99913, // Rule ID 97 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMULHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 97, GIR_Done, // Label 2339: @99913 GIM_Reject, // Label 2335: @99914 GIM_Try, /*On fail goto*//*Label 2340*/ 100042, // Rule ID 3699 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv4i32_v2i64, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv2i32_v2i64, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3699, GIR_Done, // Label 2340: @100042 GIM_Reject, // Label 2336: @100043 GIM_Try, /*On fail goto*//*Label 2341*/ 100171, // Rule ID 3698 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv8i16_v4i32, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv4i16_v4i32, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3698, GIR_Done, // Label 2341: @100171 GIM_Reject, // Label 2337: @100172 GIM_Try, /*On fail goto*//*Label 2342*/ 100300, // Rule ID 3697 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv16i8_v8i16, GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_ConstrainSelectedInstOperands, /*InsnID*/4, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv8i8_v8i16, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3697, GIR_Done, // Label 2342: @100300 GIM_Reject, // Label 2338: @100301 GIM_Reject, // Label 42: @100302 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2351*/ 100889, /*GILLT_s16*//*Label 2343*/ 100321, /*GILLT_s32*//*Label 2344*/ 100353, /*GILLT_s64*//*Label 2345*/ 100564, 0, 0, /*GILLT_v2s32*//*Label 2346*/ 100729, /*GILLT_v2s64*//*Label 2347*/ 100761, 0, /*GILLT_v4s16*//*Label 2348*/ 100793, /*GILLT_v4s32*//*Label 2349*/ 100825, 0, 0, /*GILLT_v8s16*//*Label 2350*/ 100857, // Label 2343: @100321 GIM_Try, /*On fail goto*//*Label 2352*/ 100352, // Rule ID 496 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 496, GIR_Done, // Label 2352: @100352 GIM_Reject, // Label 2344: @100353 GIM_Try, /*On fail goto*//*Label 2353*/ 100563, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2354*/ 100455, // Rule ID 4042 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4042, GIR_Done, // Label 2354: @100455 GIM_Try, /*On fail goto*//*Label 2355*/ 100543, // Rule ID 5816 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR128*/38, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5816, GIR_Done, // Label 2355: @100543 GIM_Try, /*On fail goto*//*Label 2356*/ 100562, // Rule ID 497 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 497, GIR_Done, // Label 2356: @100562 GIM_Reject, // Label 2353: @100563 GIM_Reject, // Label 2345: @100564 GIM_Try, /*On fail goto*//*Label 2357*/ 100728, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2358*/ 100643, // Rule ID 4041 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4041, GIR_Done, // Label 2358: @100643 GIM_Try, /*On fail goto*//*Label 2359*/ 100708, // Rule ID 5815 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, // MIs[2] Rn GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5815, GIR_Done, // Label 2359: @100708 GIM_Try, /*On fail goto*//*Label 2360*/ 100727, // Rule ID 498 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 498, GIR_Done, // Label 2360: @100727 GIM_Reject, // Label 2357: @100728 GIM_Reject, // Label 2346: @100729 GIM_Try, /*On fail goto*//*Label 2361*/ 100760, // Rule ID 943 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 943, GIR_Done, // Label 2361: @100760 GIM_Reject, // Label 2347: @100761 GIM_Try, /*On fail goto*//*Label 2362*/ 100792, // Rule ID 945 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 945, GIR_Done, // Label 2362: @100792 GIM_Reject, // Label 2348: @100793 GIM_Try, /*On fail goto*//*Label 2363*/ 100824, // Rule ID 941 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 941, GIR_Done, // Label 2363: @100824 GIM_Reject, // Label 2349: @100825 GIM_Try, /*On fail goto*//*Label 2364*/ 100856, // Rule ID 944 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 944, GIR_Done, // Label 2364: @100856 GIM_Reject, // Label 2350: @100857 GIM_Try, /*On fail goto*//*Label 2365*/ 100888, // Rule ID 942 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 942, GIR_Done, // Label 2365: @100888 GIM_Reject, // Label 2351: @100889 GIM_Reject, // Label 43: @100890 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2374*/ 101165, /*GILLT_s16*//*Label 2366*/ 100909, /*GILLT_s32*//*Label 2367*/ 100941, /*GILLT_s64*//*Label 2368*/ 100973, 0, 0, /*GILLT_v2s32*//*Label 2369*/ 101005, /*GILLT_v2s64*//*Label 2370*/ 101037, 0, /*GILLT_v4s16*//*Label 2371*/ 101069, /*GILLT_v4s32*//*Label 2372*/ 101101, 0, 0, /*GILLT_v8s16*//*Label 2373*/ 101133, // Label 2366: @100909 GIM_Try, /*On fail goto*//*Label 2375*/ 100940, // Rule ID 520 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 520, GIR_Done, // Label 2375: @100940 GIM_Reject, // Label 2367: @100941 GIM_Try, /*On fail goto*//*Label 2376*/ 100972, // Rule ID 521 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 521, GIR_Done, // Label 2376: @100972 GIM_Reject, // Label 2368: @100973 GIM_Try, /*On fail goto*//*Label 2377*/ 101004, // Rule ID 522 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 522, GIR_Done, // Label 2377: @101004 GIM_Reject, // Label 2369: @101005 GIM_Try, /*On fail goto*//*Label 2378*/ 101036, // Rule ID 1038 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1038, GIR_Done, // Label 2378: @101036 GIM_Reject, // Label 2370: @101037 GIM_Try, /*On fail goto*//*Label 2379*/ 101068, // Rule ID 1040 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1040, GIR_Done, // Label 2379: @101068 GIM_Reject, // Label 2371: @101069 GIM_Try, /*On fail goto*//*Label 2380*/ 101100, // Rule ID 1036 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1036, GIR_Done, // Label 2380: @101100 GIM_Reject, // Label 2372: @101101 GIM_Try, /*On fail goto*//*Label 2381*/ 101132, // Rule ID 1039 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1039, GIR_Done, // Label 2381: @101132 GIM_Reject, // Label 2373: @101133 GIM_Try, /*On fail goto*//*Label 2382*/ 101164, // Rule ID 1037 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1037, GIR_Done, // Label 2382: @101164 GIM_Reject, // Label 2374: @101165 GIM_Reject, // Label 44: @101166 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2391*/ 101834, /*GILLT_s16*//*Label 2383*/ 101185, /*GILLT_s32*//*Label 2384*/ 101348, /*GILLT_s64*//*Label 2385*/ 101511, 0, 0, /*GILLT_v2s32*//*Label 2386*/ 101674, /*GILLT_v2s64*//*Label 2387*/ 101706, 0, /*GILLT_v4s16*//*Label 2388*/ 101738, /*GILLT_v4s32*//*Label 2389*/ 101770, 0, 0, /*GILLT_v8s16*//*Label 2390*/ 101802, // Label 2383: @101185 GIM_Try, /*On fail goto*//*Label 2392*/ 101347, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 2393*/ 101263, // Rule ID 5573 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5573, GIR_Done, // Label 2393: @101263 GIM_Try, /*On fail goto*//*Label 2394*/ 101327, // Rule ID 1586 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1586, GIR_Done, // Label 2394: @101327 GIM_Try, /*On fail goto*//*Label 2395*/ 101346, // Rule ID 514 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 514, GIR_Done, // Label 2395: @101346 GIM_Reject, // Label 2392: @101347 GIM_Reject, // Label 2384: @101348 GIM_Try, /*On fail goto*//*Label 2396*/ 101510, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2397*/ 101426, // Rule ID 5574 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5574, GIR_Done, // Label 2397: @101426 GIM_Try, /*On fail goto*//*Label 2398*/ 101490, // Rule ID 1587 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1587, GIR_Done, // Label 2398: @101490 GIM_Try, /*On fail goto*//*Label 2399*/ 101509, // Rule ID 515 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 515, GIR_Done, // Label 2399: @101509 GIM_Reject, // Label 2396: @101510 GIM_Reject, // Label 2385: @101511 GIM_Try, /*On fail goto*//*Label 2400*/ 101673, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2401*/ 101589, // Rule ID 5575 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5575, GIR_Done, // Label 2401: @101589 GIM_Try, /*On fail goto*//*Label 2402*/ 101653, // Rule ID 1588 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1588, GIR_Done, // Label 2402: @101653 GIM_Try, /*On fail goto*//*Label 2403*/ 101672, // Rule ID 516 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 516, GIR_Done, // Label 2403: @101672 GIM_Reject, // Label 2400: @101673 GIM_Reject, // Label 2386: @101674 GIM_Try, /*On fail goto*//*Label 2404*/ 101705, // Rule ID 1023 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1023, GIR_Done, // Label 2404: @101705 GIM_Reject, // Label 2387: @101706 GIM_Try, /*On fail goto*//*Label 2405*/ 101737, // Rule ID 1025 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1025, GIR_Done, // Label 2405: @101737 GIM_Reject, // Label 2388: @101738 GIM_Try, /*On fail goto*//*Label 2406*/ 101769, // Rule ID 1021 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1021, GIR_Done, // Label 2406: @101769 GIM_Reject, // Label 2389: @101770 GIM_Try, /*On fail goto*//*Label 2407*/ 101801, // Rule ID 1024 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1024, GIR_Done, // Label 2407: @101801 GIM_Reject, // Label 2390: @101802 GIM_Try, /*On fail goto*//*Label 2408*/ 101833, // Rule ID 1022 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1022, GIR_Done, // Label 2408: @101833 GIM_Reject, // Label 2391: @101834 GIM_Reject, // Label 45: @101835 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2417*/ 105506, /*GILLT_s16*//*Label 2409*/ 101854, /*GILLT_s32*//*Label 2410*/ 102188, /*GILLT_s64*//*Label 2411*/ 103818, 0, 0, /*GILLT_v2s32*//*Label 2412*/ 104796, /*GILLT_v2s64*//*Label 2413*/ 104960, 0, /*GILLT_v4s16*//*Label 2414*/ 105124, /*GILLT_v4s32*//*Label 2415*/ 105233, 0, 0, /*GILLT_v8s16*//*Label 2416*/ 105397, // Label 2409: @101854 GIM_Try, /*On fail goto*//*Label 2418*/ 102187, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 2419*/ 101938, // Rule ID 2813 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2813, GIR_Done, // Label 2419: @101938 GIM_Try, /*On fail goto*//*Label 2420*/ 102004, // Rule ID 2816 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2816, GIR_Done, // Label 2420: @102004 GIM_Try, /*On fail goto*//*Label 2421*/ 102057, // Rule ID 2810 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2810, GIR_Done, // Label 2421: @102057 GIM_Try, /*On fail goto*//*Label 2422*/ 102110, // Rule ID 526 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 526, GIR_Done, // Label 2422: @102110 GIM_Try, /*On fail goto*//*Label 2423*/ 102163, // Rule ID 532 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 532, GIR_Done, // Label 2423: @102163 GIM_Try, /*On fail goto*//*Label 2424*/ 102186, // Rule ID 523 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDHrrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 523, GIR_Done, // Label 2424: @102186 GIM_Reject, // Label 2418: @102187 GIM_Reject, // Label 2410: @102188 GIM_Try, /*On fail goto*//*Label 2425*/ 103817, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2426*/ 102289, // Rule ID 3472 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3472, GIR_Done, // Label 2426: @102289 GIM_Try, /*On fail goto*//*Label 2427*/ 102374, // Rule ID 3443 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3443, GIR_Done, // Label 2427: @102374 GIM_Try, /*On fail goto*//*Label 2428*/ 102487, // Rule ID 3444 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3444, GIR_Done, // Label 2428: @102487 GIM_Try, /*On fail goto*//*Label 2429*/ 102572, // Rule ID 3452 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3452, GIR_Done, // Label 2429: @102572 GIM_Try, /*On fail goto*//*Label 2430*/ 102685, // Rule ID 3453 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3453, GIR_Done, // Label 2430: @102685 GIM_Try, /*On fail goto*//*Label 2431*/ 102770, // Rule ID 3461 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3461, GIR_Done, // Label 2431: @102770 GIM_Try, /*On fail goto*//*Label 2432*/ 102883, // Rule ID 3462 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3462, GIR_Done, // Label 2432: @102883 GIM_Try, /*On fail goto*//*Label 2433*/ 102966, // Rule ID 3483 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3483, GIR_Done, // Label 2433: @102966 GIM_Try, /*On fail goto*//*Label 2434*/ 103051, // Rule ID 3434 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3434, GIR_Done, // Label 2434: @103051 GIM_Try, /*On fail goto*//*Label 2435*/ 103164, // Rule ID 3435 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3435, GIR_Done, // Label 2435: @103164 GIM_Try, /*On fail goto*//*Label 2436*/ 103236, // Rule ID 1902 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1902, GIR_Done, // Label 2436: @103236 GIM_Try, /*On fail goto*//*Label 2437*/ 103336, // Rule ID 1903 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1903, GIR_Done, // Label 2437: @103336 GIM_Try, /*On fail goto*//*Label 2438*/ 103408, // Rule ID 3425 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3425, GIR_Done, // Label 2438: @103408 GIM_Try, /*On fail goto*//*Label 2439*/ 103508, // Rule ID 3426 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2f32] }:$Rm, dsub:{ *:[i32] }), (imm:{ *:[i64] })<>:$idx) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/1, /*Imm*/2, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR128*/38, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR64*/16, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3426, GIR_Done, // Label 2439: @103508 GIM_Try, /*On fail goto*//*Label 2440*/ 103572, // Rule ID 2814 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2814, GIR_Done, // Label 2440: @103572 GIM_Try, /*On fail goto*//*Label 2441*/ 103636, // Rule ID 2817 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2817, GIR_Done, // Label 2441: @103636 GIM_Try, /*On fail goto*//*Label 2442*/ 103687, // Rule ID 2811 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2811, GIR_Done, // Label 2442: @103687 GIM_Try, /*On fail goto*//*Label 2443*/ 103740, // Rule ID 527 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 527, GIR_Done, // Label 2443: @103740 GIM_Try, /*On fail goto*//*Label 2444*/ 103793, // Rule ID 533 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 533, GIR_Done, // Label 2444: @103793 GIM_Try, /*On fail goto*//*Label 2445*/ 103816, // Rule ID 524 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDSrrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 524, GIR_Done, // Label 2445: @103816 GIM_Reject, // Label 2425: @103817 GIM_Reject, // Label 2411: @103818 GIM_Try, /*On fail goto*//*Label 2446*/ 104795, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2447*/ 103919, // Rule ID 3474 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3474, GIR_Done, // Label 2447: @103919 GIM_Try, /*On fail goto*//*Label 2448*/ 104004, // Rule ID 3445 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3445, GIR_Done, // Label 2448: @104004 GIM_Try, /*On fail goto*//*Label 2449*/ 104089, // Rule ID 3454 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3454, GIR_Done, // Label 2449: @104089 GIM_Try, /*On fail goto*//*Label 2450*/ 104174, // Rule ID 3463 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3463, GIR_Done, // Label 2450: @104174 GIM_Try, /*On fail goto*//*Label 2451*/ 104257, // Rule ID 3485 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3485, GIR_Done, // Label 2451: @104257 GIM_Try, /*On fail goto*//*Label 2452*/ 104342, // Rule ID 3436 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[3] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3436, GIR_Done, // Label 2452: @104342 GIM_Try, /*On fail goto*//*Label 2453*/ 104414, // Rule ID 1904 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1904, GIR_Done, // Label 2453: @104414 GIM_Try, /*On fail goto*//*Label 2454*/ 104486, // Rule ID 3427 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3427, GIR_Done, // Label 2454: @104486 GIM_Try, /*On fail goto*//*Label 2455*/ 104550, // Rule ID 2815 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2815, GIR_Done, // Label 2455: @104550 GIM_Try, /*On fail goto*//*Label 2456*/ 104614, // Rule ID 2818 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2818, GIR_Done, // Label 2456: @104614 GIM_Try, /*On fail goto*//*Label 2457*/ 104665, // Rule ID 2812 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2812, GIR_Done, // Label 2457: @104665 GIM_Try, /*On fail goto*//*Label 2458*/ 104718, // Rule ID 528 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 528, GIR_Done, // Label 2458: @104718 GIM_Try, /*On fail goto*//*Label 2459*/ 104771, // Rule ID 534 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 534, GIR_Done, // Label 2459: @104771 GIM_Try, /*On fail goto*//*Label 2460*/ 104794, // Rule ID 525 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDDrrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 525, GIR_Done, // Label 2460: @104794 GIM_Reject, // Label 2446: @104795 GIM_Reject, // Label 2412: @104796 GIM_Try, /*On fail goto*//*Label 2461*/ 104959, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2462*/ 104865, // Rule ID 2904 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2904, GIR_Done, // Label 2462: @104865 GIM_Try, /*On fail goto*//*Label 2463*/ 104918, // Rule ID 1013 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1013, GIR_Done, // Label 2463: @104918 GIM_Try, /*On fail goto*//*Label 2464*/ 104958, // Rule ID 1008 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1008, GIR_Done, // Label 2464: @104958 GIM_Reject, // Label 2461: @104959 GIM_Reject, // Label 2413: @104960 GIM_Try, /*On fail goto*//*Label 2465*/ 105123, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2466*/ 105029, // Rule ID 2906 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2906, GIR_Done, // Label 2466: @105029 GIM_Try, /*On fail goto*//*Label 2467*/ 105082, // Rule ID 1015 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1015, GIR_Done, // Label 2467: @105082 GIM_Try, /*On fail goto*//*Label 2468*/ 105122, // Rule ID 1010 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1010, GIR_Done, // Label 2468: @105122 GIM_Reject, // Label 2465: @105123 GIM_Reject, // Label 2414: @105124 GIM_Try, /*On fail goto*//*Label 2469*/ 105232, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2470*/ 105195, // Rule ID 1011 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1011, GIR_Done, // Label 2470: @105195 GIM_Try, /*On fail goto*//*Label 2471*/ 105231, // Rule ID 1006 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1006, GIR_Done, // Label 2471: @105231 GIM_Reject, // Label 2469: @105232 GIM_Reject, // Label 2415: @105233 GIM_Try, /*On fail goto*//*Label 2472*/ 105396, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2473*/ 105302, // Rule ID 2905 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2905, GIR_Done, // Label 2473: @105302 GIM_Try, /*On fail goto*//*Label 2474*/ 105355, // Rule ID 1014 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1014, GIR_Done, // Label 2474: @105355 GIM_Try, /*On fail goto*//*Label 2475*/ 105395, // Rule ID 1009 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1009, GIR_Done, // Label 2475: @105395 GIM_Reject, // Label 2472: @105396 GIM_Reject, // Label 2416: @105397 GIM_Try, /*On fail goto*//*Label 2476*/ 105505, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2477*/ 105468, // Rule ID 1012 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1012, GIR_Done, // Label 2477: @105468 GIM_Try, /*On fail goto*//*Label 2478*/ 105504, // Rule ID 1007 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1007, GIR_Done, // Label 2478: @105504 GIM_Reject, // Label 2476: @105505 GIM_Reject, // Label 2417: @105506 GIM_Reject, // Label 46: @105507 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2487*/ 105782, /*GILLT_s16*//*Label 2479*/ 105526, /*GILLT_s32*//*Label 2480*/ 105558, /*GILLT_s64*//*Label 2481*/ 105590, 0, 0, /*GILLT_v2s32*//*Label 2482*/ 105622, /*GILLT_v2s64*//*Label 2483*/ 105654, 0, /*GILLT_v4s16*//*Label 2484*/ 105686, /*GILLT_v4s32*//*Label 2485*/ 105718, 0, 0, /*GILLT_v8s16*//*Label 2486*/ 105750, // Label 2479: @105526 GIM_Try, /*On fail goto*//*Label 2488*/ 105557, // Rule ID 499 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 499, GIR_Done, // Label 2488: @105557 GIM_Reject, // Label 2480: @105558 GIM_Try, /*On fail goto*//*Label 2489*/ 105589, // Rule ID 500 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 500, GIR_Done, // Label 2489: @105589 GIM_Reject, // Label 2481: @105590 GIM_Try, /*On fail goto*//*Label 2490*/ 105621, // Rule ID 501 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 501, GIR_Done, // Label 2490: @105621 GIM_Reject, // Label 2482: @105622 GIM_Try, /*On fail goto*//*Label 2491*/ 105653, // Rule ID 963 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 963, GIR_Done, // Label 2491: @105653 GIM_Reject, // Label 2483: @105654 GIM_Try, /*On fail goto*//*Label 2492*/ 105685, // Rule ID 965 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 965, GIR_Done, // Label 2492: @105685 GIM_Reject, // Label 2484: @105686 GIM_Try, /*On fail goto*//*Label 2493*/ 105717, // Rule ID 961 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 961, GIR_Done, // Label 2493: @105717 GIM_Reject, // Label 2485: @105718 GIM_Try, /*On fail goto*//*Label 2494*/ 105749, // Rule ID 964 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 964, GIR_Done, // Label 2494: @105749 GIM_Reject, // Label 2486: @105750 GIM_Try, /*On fail goto*//*Label 2495*/ 105781, // Rule ID 962 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 962, GIR_Done, // Label 2495: @105781 GIM_Reject, // Label 2487: @105782 GIM_Reject, // Label 47: @105783 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2504*/ 106333, /*GILLT_s16*//*Label 2496*/ 105802, /*GILLT_s32*//*Label 2497*/ 105939, /*GILLT_s64*//*Label 2498*/ 106076, 0, 0, /*GILLT_v2s32*//*Label 2499*/ 106213, /*GILLT_v2s64*//*Label 2500*/ 106237, 0, /*GILLT_v4s16*//*Label 2501*/ 106261, /*GILLT_v4s32*//*Label 2502*/ 106285, 0, 0, /*GILLT_v8s16*//*Label 2503*/ 106309, // Label 2496: @105802 GIM_Try, /*On fail goto*//*Label 2505*/ 105938, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 2506*/ 105873, // Rule ID 529 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 529, GIR_Done, // Label 2506: @105873 GIM_Try, /*On fail goto*//*Label 2507*/ 105922, // Rule ID 517 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 517, GIR_Done, // Label 2507: @105922 GIM_Try, /*On fail goto*//*Label 2508*/ 105937, // Rule ID 469 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 469, GIR_Done, // Label 2508: @105937 GIM_Reject, // Label 2505: @105938 GIM_Reject, // Label 2497: @105939 GIM_Try, /*On fail goto*//*Label 2509*/ 106075, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2510*/ 106010, // Rule ID 530 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 530, GIR_Done, // Label 2510: @106010 GIM_Try, /*On fail goto*//*Label 2511*/ 106059, // Rule ID 518 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 518, GIR_Done, // Label 2511: @106059 GIM_Try, /*On fail goto*//*Label 2512*/ 106074, // Rule ID 470 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 470, GIR_Done, // Label 2512: @106074 GIM_Reject, // Label 2509: @106075 GIM_Reject, // Label 2498: @106076 GIM_Try, /*On fail goto*//*Label 2513*/ 106212, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2514*/ 106147, // Rule ID 531 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 531, GIR_Done, // Label 2514: @106147 GIM_Try, /*On fail goto*//*Label 2515*/ 106196, // Rule ID 519 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 519, GIR_Done, // Label 2515: @106196 GIM_Try, /*On fail goto*//*Label 2516*/ 106211, // Rule ID 471 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 471, GIR_Done, // Label 2516: @106211 GIM_Reject, // Label 2513: @106212 GIM_Reject, // Label 2499: @106213 GIM_Try, /*On fail goto*//*Label 2517*/ 106236, // Rule ID 711 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 711, GIR_Done, // Label 2517: @106236 GIM_Reject, // Label 2500: @106237 GIM_Try, /*On fail goto*//*Label 2518*/ 106260, // Rule ID 713 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 713, GIR_Done, // Label 2518: @106260 GIM_Reject, // Label 2501: @106261 GIM_Try, /*On fail goto*//*Label 2519*/ 106284, // Rule ID 709 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 709, GIR_Done, // Label 2519: @106284 GIM_Reject, // Label 2502: @106285 GIM_Try, /*On fail goto*//*Label 2520*/ 106308, // Rule ID 712 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 712, GIR_Done, // Label 2520: @106308 GIM_Reject, // Label 2503: @106309 GIM_Try, /*On fail goto*//*Label 2521*/ 106332, // Rule ID 710 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 710, GIR_Done, // Label 2521: @106332 GIM_Reject, // Label 2504: @106333 GIM_Reject, // Label 48: @106334 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 2526*/ 106464, /*GILLT_s32*//*Label 2522*/ 106349, /*GILLT_s64*//*Label 2523*/ 106373, 0, 0, 0, /*GILLT_v2s64*//*Label 2524*/ 106420, 0, 0, /*GILLT_v4s32*//*Label 2525*/ 106442, // Label 2522: @106349 GIM_Try, /*On fail goto*//*Label 2527*/ 106372, // Rule ID 462 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) => (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 462, GIR_Done, // Label 2527: @106372 GIM_Reject, // Label 2523: @106373 GIM_Try, /*On fail goto*//*Label 2528*/ 106396, // Rule ID 461 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) => (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 461, GIR_Done, // Label 2528: @106396 GIM_Try, /*On fail goto*//*Label 2529*/ 106419, // Rule ID 463 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) => (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 463, GIR_Done, // Label 2529: @106419 GIM_Reject, // Label 2524: @106420 GIM_Try, /*On fail goto*//*Label 2530*/ 106441, // Rule ID 2829 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) => (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2829, GIR_Done, // Label 2530: @106441 GIM_Reject, // Label 2525: @106442 GIM_Try, /*On fail goto*//*Label 2531*/ 106463, // Rule ID 2830 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2830, GIR_Done, // Label 2531: @106463 GIM_Reject, // Label 2526: @106464 GIM_Reject, // Label 49: @106465 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 2536*/ 106595, /*GILLT_s16*//*Label 2532*/ 106480, /*GILLT_s32*//*Label 2533*/ 106527, 0, 0, 0, /*GILLT_v2s32*//*Label 2534*/ 106551, 0, 0, /*GILLT_v4s16*//*Label 2535*/ 106573, // Label 2532: @106480 GIM_Try, /*On fail goto*//*Label 2537*/ 106503, // Rule ID 458 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) => (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 458, GIR_Done, // Label 2537: @106503 GIM_Try, /*On fail goto*//*Label 2538*/ 106526, // Rule ID 465 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) => (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 465, GIR_Done, // Label 2538: @106526 GIM_Reject, // Label 2533: @106527 GIM_Try, /*On fail goto*//*Label 2539*/ 106550, // Rule ID 460 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) => (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 460, GIR_Done, // Label 2539: @106550 GIM_Reject, // Label 2534: @106551 GIM_Try, /*On fail goto*//*Label 2540*/ 106572, // Rule ID 2833 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) => (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2833, GIR_Done, // Label 2540: @106572 GIM_Reject, // Label 2535: @106573 GIM_Try, /*On fail goto*//*Label 2541*/ 106594, // Rule ID 2834 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2834, GIR_Done, // Label 2541: @106594 GIM_Reject, // Label 2536: @106595 GIM_Reject, // Label 50: @106596 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 13, /*)*//*default:*//*Label 2549*/ 107498, /*GILLT_s32*//*Label 2542*/ 106614, /*GILLT_s64*//*Label 2543*/ 106996, 0, 0, /*GILLT_v2s32*//*Label 2544*/ 107378, /*GILLT_v2s64*//*Label 2545*/ 107402, 0, /*GILLT_v4s16*//*Label 2546*/ 107426, /*GILLT_v4s32*//*Label 2547*/ 107450, 0, 0, /*GILLT_v8s16*//*Label 2548*/ 107474, // Label 2542: @106614 GIM_Try, /*On fail goto*//*Label 2550*/ 106653, // Rule ID 2755 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2755, GIR_Done, // Label 2550: @106653 GIM_Try, /*On fail goto*//*Label 2551*/ 106692, // Rule ID 2757 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2757, GIR_Done, // Label 2551: @106692 GIM_Try, /*On fail goto*//*Label 2552*/ 106731, // Rule ID 2763 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2763, GIR_Done, // Label 2552: @106731 GIM_Try, /*On fail goto*//*Label 2553*/ 106770, // Rule ID 2765 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2765, GIR_Done, // Label 2553: @106770 GIM_Try, /*On fail goto*//*Label 2554*/ 106809, // Rule ID 2779 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2779, GIR_Done, // Label 2554: @106809 GIM_Try, /*On fail goto*//*Label 2555*/ 106848, // Rule ID 2781 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2781, GIR_Done, // Label 2555: @106848 GIM_Try, /*On fail goto*//*Label 2556*/ 106887, // Rule ID 2771 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2771, GIR_Done, // Label 2556: @106887 GIM_Try, /*On fail goto*//*Label 2557*/ 106926, // Rule ID 2773 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2773, GIR_Done, // Label 2557: @106926 GIM_Try, /*On fail goto*//*Label 2558*/ 106949, // Rule ID 359 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 359, GIR_Done, // Label 2558: @106949 GIM_Try, /*On fail goto*//*Label 2559*/ 106972, // Rule ID 363 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 363, GIR_Done, // Label 2559: @106972 GIM_Try, /*On fail goto*//*Label 2560*/ 106995, // Rule ID 367 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 367, GIR_Done, // Label 2560: @106995 GIM_Reject, // Label 2543: @106996 GIM_Try, /*On fail goto*//*Label 2561*/ 107035, // Rule ID 2756 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2756, GIR_Done, // Label 2561: @107035 GIM_Try, /*On fail goto*//*Label 2562*/ 107074, // Rule ID 2758 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2758, GIR_Done, // Label 2562: @107074 GIM_Try, /*On fail goto*//*Label 2563*/ 107113, // Rule ID 2764 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2764, GIR_Done, // Label 2563: @107113 GIM_Try, /*On fail goto*//*Label 2564*/ 107152, // Rule ID 2766 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2766, GIR_Done, // Label 2564: @107152 GIM_Try, /*On fail goto*//*Label 2565*/ 107191, // Rule ID 2780 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2780, GIR_Done, // Label 2565: @107191 GIM_Try, /*On fail goto*//*Label 2566*/ 107230, // Rule ID 2782 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2782, GIR_Done, // Label 2566: @107230 GIM_Try, /*On fail goto*//*Label 2567*/ 107269, // Rule ID 2772 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2772, GIR_Done, // Label 2567: @107269 GIM_Try, /*On fail goto*//*Label 2568*/ 107308, // Rule ID 2774 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2774, GIR_Done, // Label 2568: @107308 GIM_Try, /*On fail goto*//*Label 2569*/ 107331, // Rule ID 361 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 361, GIR_Done, // Label 2569: @107331 GIM_Try, /*On fail goto*//*Label 2570*/ 107354, // Rule ID 365 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 365, GIR_Done, // Label 2570: @107354 GIM_Try, /*On fail goto*//*Label 2571*/ 107377, // Rule ID 369 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 369, GIR_Done, // Label 2571: @107377 GIM_Reject, // Label 2544: @107378 GIM_Try, /*On fail goto*//*Label 2572*/ 107401, // Rule ID 701 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 701, GIR_Done, // Label 2572: @107401 GIM_Reject, // Label 2545: @107402 GIM_Try, /*On fail goto*//*Label 2573*/ 107425, // Rule ID 703 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 703, GIR_Done, // Label 2573: @107425 GIM_Reject, // Label 2546: @107426 GIM_Try, /*On fail goto*//*Label 2574*/ 107449, // Rule ID 699 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 699, GIR_Done, // Label 2574: @107449 GIM_Reject, // Label 2547: @107450 GIM_Try, /*On fail goto*//*Label 2575*/ 107473, // Rule ID 702 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 702, GIR_Done, // Label 2575: @107473 GIM_Reject, // Label 2548: @107474 GIM_Try, /*On fail goto*//*Label 2576*/ 107497, // Rule ID 700 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 700, GIR_Done, // Label 2576: @107497 GIM_Reject, // Label 2549: @107498 GIM_Reject, // Label 51: @107499 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 13, /*)*//*default:*//*Label 2584*/ 108401, /*GILLT_s32*//*Label 2577*/ 107517, /*GILLT_s64*//*Label 2578*/ 107899, 0, 0, /*GILLT_v2s32*//*Label 2579*/ 108281, /*GILLT_v2s64*//*Label 2580*/ 108305, 0, /*GILLT_v4s16*//*Label 2581*/ 108329, /*GILLT_v4s32*//*Label 2582*/ 108353, 0, 0, /*GILLT_v8s16*//*Label 2583*/ 108377, // Label 2577: @107517 GIM_Try, /*On fail goto*//*Label 2585*/ 107556, // Rule ID 2759 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2759, GIR_Done, // Label 2585: @107556 GIM_Try, /*On fail goto*//*Label 2586*/ 107595, // Rule ID 2761 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2761, GIR_Done, // Label 2586: @107595 GIM_Try, /*On fail goto*//*Label 2587*/ 107634, // Rule ID 2767 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2767, GIR_Done, // Label 2587: @107634 GIM_Try, /*On fail goto*//*Label 2588*/ 107673, // Rule ID 2769 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2769, GIR_Done, // Label 2588: @107673 GIM_Try, /*On fail goto*//*Label 2589*/ 107712, // Rule ID 2783 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2783, GIR_Done, // Label 2589: @107712 GIM_Try, /*On fail goto*//*Label 2590*/ 107751, // Rule ID 2785 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2785, GIR_Done, // Label 2590: @107751 GIM_Try, /*On fail goto*//*Label 2591*/ 107790, // Rule ID 2775 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2775, GIR_Done, // Label 2591: @107790 GIM_Try, /*On fail goto*//*Label 2592*/ 107829, // Rule ID 2777 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2777, GIR_Done, // Label 2592: @107829 GIM_Try, /*On fail goto*//*Label 2593*/ 107852, // Rule ID 371 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 371, GIR_Done, // Label 2593: @107852 GIM_Try, /*On fail goto*//*Label 2594*/ 107875, // Rule ID 375 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 375, GIR_Done, // Label 2594: @107875 GIM_Try, /*On fail goto*//*Label 2595*/ 107898, // Rule ID 379 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 379, GIR_Done, // Label 2595: @107898 GIM_Reject, // Label 2578: @107899 GIM_Try, /*On fail goto*//*Label 2596*/ 107938, // Rule ID 2760 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2760, GIR_Done, // Label 2596: @107938 GIM_Try, /*On fail goto*//*Label 2597*/ 107977, // Rule ID 2762 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2762, GIR_Done, // Label 2597: @107977 GIM_Try, /*On fail goto*//*Label 2598*/ 108016, // Rule ID 2768 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2768, GIR_Done, // Label 2598: @108016 GIM_Try, /*On fail goto*//*Label 2599*/ 108055, // Rule ID 2770 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2770, GIR_Done, // Label 2599: @108055 GIM_Try, /*On fail goto*//*Label 2600*/ 108094, // Rule ID 2784 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2784, GIR_Done, // Label 2600: @108094 GIM_Try, /*On fail goto*//*Label 2601*/ 108133, // Rule ID 2786 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2786, GIR_Done, // Label 2601: @108133 GIM_Try, /*On fail goto*//*Label 2602*/ 108172, // Rule ID 2776 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2776, GIR_Done, // Label 2602: @108172 GIM_Try, /*On fail goto*//*Label 2603*/ 108211, // Rule ID 2778 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2778, GIR_Done, // Label 2603: @108211 GIM_Try, /*On fail goto*//*Label 2604*/ 108234, // Rule ID 373 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 373, GIR_Done, // Label 2604: @108234 GIM_Try, /*On fail goto*//*Label 2605*/ 108257, // Rule ID 377 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 377, GIR_Done, // Label 2605: @108257 GIM_Try, /*On fail goto*//*Label 2606*/ 108280, // Rule ID 381 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 381, GIR_Done, // Label 2606: @108280 GIM_Reject, // Label 2579: @108281 GIM_Try, /*On fail goto*//*Label 2607*/ 108304, // Rule ID 706 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 706, GIR_Done, // Label 2607: @108304 GIM_Reject, // Label 2580: @108305 GIM_Try, /*On fail goto*//*Label 2608*/ 108328, // Rule ID 708 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 708, GIR_Done, // Label 2608: @108328 GIM_Reject, // Label 2581: @108329 GIM_Try, /*On fail goto*//*Label 2609*/ 108352, // Rule ID 704 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 704, GIR_Done, // Label 2609: @108352 GIM_Reject, // Label 2582: @108353 GIM_Try, /*On fail goto*//*Label 2610*/ 108376, // Rule ID 707 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 707, GIR_Done, // Label 2610: @108376 GIM_Reject, // Label 2583: @108377 GIM_Try, /*On fail goto*//*Label 2611*/ 108400, // Rule ID 705 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 705, GIR_Done, // Label 2611: @108400 GIM_Reject, // Label 2584: @108401 GIM_Reject, // Label 52: @108402 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2620*/ 108682, /*GILLT_s16*//*Label 2612*/ 108421, /*GILLT_s32*//*Label 2613*/ 108468, /*GILLT_s64*//*Label 2614*/ 108515, 0, 0, /*GILLT_v2s32*//*Label 2615*/ 108562, /*GILLT_v2s64*//*Label 2616*/ 108586, 0, /*GILLT_v4s16*//*Label 2617*/ 108610, /*GILLT_v4s32*//*Label 2618*/ 108634, 0, 0, /*GILLT_v8s16*//*Label 2619*/ 108658, // Label 2612: @108421 GIM_Try, /*On fail goto*//*Label 2621*/ 108444, // Rule ID 407 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWHri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 407, GIR_Done, // Label 2621: @108444 GIM_Try, /*On fail goto*//*Label 2622*/ 108467, // Rule ID 413 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXHri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 413, GIR_Done, // Label 2622: @108467 GIM_Reject, // Label 2613: @108468 GIM_Try, /*On fail goto*//*Label 2623*/ 108491, // Rule ID 409 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWSri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 409, GIR_Done, // Label 2623: @108491 GIM_Try, /*On fail goto*//*Label 2624*/ 108514, // Rule ID 415 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXSri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 415, GIR_Done, // Label 2624: @108514 GIM_Reject, // Label 2614: @108515 GIM_Try, /*On fail goto*//*Label 2625*/ 108538, // Rule ID 411 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWDri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 411, GIR_Done, // Label 2625: @108538 GIM_Try, /*On fail goto*//*Label 2626*/ 108561, // Rule ID 417 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXDri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 417, GIR_Done, // Label 2626: @108561 GIM_Reject, // Label 2615: @108562 GIM_Try, /*On fail goto*//*Label 2627*/ 108585, // Rule ID 801 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 801, GIR_Done, // Label 2627: @108585 GIM_Reject, // Label 2616: @108586 GIM_Try, /*On fail goto*//*Label 2628*/ 108609, // Rule ID 803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 803, GIR_Done, // Label 2628: @108609 GIM_Reject, // Label 2617: @108610 GIM_Try, /*On fail goto*//*Label 2629*/ 108633, // Rule ID 799 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 799, GIR_Done, // Label 2629: @108633 GIM_Reject, // Label 2618: @108634 GIM_Try, /*On fail goto*//*Label 2630*/ 108657, // Rule ID 802 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 802, GIR_Done, // Label 2630: @108657 GIM_Reject, // Label 2619: @108658 GIM_Try, /*On fail goto*//*Label 2631*/ 108681, // Rule ID 800 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 800, GIR_Done, // Label 2631: @108681 GIM_Reject, // Label 2620: @108682 GIM_Reject, // Label 53: @108683 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2640*/ 110439, /*GILLT_s16*//*Label 2632*/ 108702, /*GILLT_s32*//*Label 2633*/ 108749, /*GILLT_s64*//*Label 2634*/ 109288, 0, 0, /*GILLT_v2s32*//*Label 2635*/ 110319, /*GILLT_v2s64*//*Label 2636*/ 110343, 0, /*GILLT_v4s16*//*Label 2637*/ 110367, /*GILLT_v4s32*//*Label 2638*/ 110391, 0, 0, /*GILLT_v8s16*//*Label 2639*/ 110415, // Label 2632: @108702 GIM_Try, /*On fail goto*//*Label 2641*/ 108725, // Rule ID 431 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWHri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 431, GIR_Done, // Label 2641: @108725 GIM_Try, /*On fail goto*//*Label 2642*/ 108748, // Rule ID 437 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXHri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 437, GIR_Done, // Label 2642: @108748 GIM_Reject, // Label 2633: @108749 GIM_Try, /*On fail goto*//*Label 2643*/ 108874, // Rule ID 3052 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3052, GIR_Done, // Label 2643: @108874 GIM_Try, /*On fail goto*//*Label 2644*/ 108999, // Rule ID 3053 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3053, GIR_Done, // Label 2644: @108999 GIM_Try, /*On fail goto*//*Label 2645*/ 109120, // Rule ID 3054 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3054, GIR_Done, // Label 2645: @109120 GIM_Try, /*On fail goto*//*Label 2646*/ 109241, // Rule ID 3055 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR32*/5, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3055, GIR_Done, // Label 2646: @109241 GIM_Try, /*On fail goto*//*Label 2647*/ 109264, // Rule ID 433 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWSri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 433, GIR_Done, // Label 2647: @109264 GIM_Try, /*On fail goto*//*Label 2648*/ 109287, // Rule ID 439 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXSri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 439, GIR_Done, // Label 2648: @109287 GIM_Reject, // Label 2634: @109288 GIM_Try, /*On fail goto*//*Label 2649*/ 109413, // Rule ID 3064 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3064, GIR_Done, // Label 2649: @109413 GIM_Try, /*On fail goto*//*Label 2650*/ 109538, // Rule ID 3065 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3065, GIR_Done, // Label 2650: @109538 GIM_Try, /*On fail goto*//*Label 2651*/ 109663, // Rule ID 3060 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3060, GIR_Done, // Label 2651: @109663 GIM_Try, /*On fail goto*//*Label 2652*/ 109788, // Rule ID 3061 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3061, GIR_Done, // Label 2652: @109788 GIM_Try, /*On fail goto*//*Label 2653*/ 109909, // Rule ID 3066 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3066, GIR_Done, // Label 2653: @109909 GIM_Try, /*On fail goto*//*Label 2654*/ 110030, // Rule ID 3067 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), ssub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURSi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR32*/5, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3067, GIR_Done, // Label 2654: @110030 GIM_Try, /*On fail goto*//*Label 2655*/ 110151, // Rule ID 3062 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3062, GIR_Done, // Label 2655: @110151 GIM_Try, /*On fail goto*//*Label 2656*/ 110272, // Rule ID 3063 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset))<><><>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<>:$offset), hsub:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/7, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC FPR64*/16, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC FPR16*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3063, GIR_Done, // Label 2656: @110272 GIM_Try, /*On fail goto*//*Label 2657*/ 110295, // Rule ID 435 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWDri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 435, GIR_Done, // Label 2657: @110295 GIM_Try, /*On fail goto*//*Label 2658*/ 110318, // Rule ID 441 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXDri, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 441, GIR_Done, // Label 2658: @110318 GIM_Reject, // Label 2635: @110319 GIM_Try, /*On fail goto*//*Label 2659*/ 110342, // Rule ID 845 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 845, GIR_Done, // Label 2659: @110342 GIM_Reject, // Label 2636: @110343 GIM_Try, /*On fail goto*//*Label 2660*/ 110366, // Rule ID 847 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 847, GIR_Done, // Label 2660: @110366 GIM_Reject, // Label 2637: @110367 GIM_Try, /*On fail goto*//*Label 2661*/ 110390, // Rule ID 843 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 843, GIR_Done, // Label 2661: @110390 GIM_Reject, // Label 2638: @110391 GIM_Try, /*On fail goto*//*Label 2662*/ 110414, // Rule ID 846 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 846, GIR_Done, // Label 2662: @110414 GIM_Reject, // Label 2639: @110415 GIM_Try, /*On fail goto*//*Label 2663*/ 110438, // Rule ID 844 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 844, GIR_Done, // Label 2663: @110438 GIM_Reject, // Label 2640: @110439 GIM_Reject, // Label 54: @110440 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2672*/ 110999, /*GILLT_s16*//*Label 2664*/ 110459, /*GILLT_s32*//*Label 2665*/ 110527, /*GILLT_s64*//*Label 2666*/ 110593, 0, 0, /*GILLT_v2s32*//*Label 2667*/ 110659, /*GILLT_v2s64*//*Label 2668*/ 110727, 0, /*GILLT_v4s16*//*Label 2669*/ 110795, /*GILLT_v4s32*//*Label 2670*/ 110863, 0, 0, /*GILLT_v8s16*//*Label 2671*/ 110931, // Label 2664: @110459 GIM_Try, /*On fail goto*//*Label 2673*/ 110526, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_Try, /*On fail goto*//*Label 2674*/ 110510, // Rule ID 2967 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)) => (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2967, GIR_Done, // Label 2674: @110510 GIM_Try, /*On fail goto*//*Label 2675*/ 110525, // Rule ID 466 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 466, GIR_Done, // Label 2675: @110525 GIM_Reject, // Label 2673: @110526 GIM_Reject, // Label 2665: @110527 GIM_Try, /*On fail goto*//*Label 2676*/ 110592, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2677*/ 110576, // Rule ID 2968 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)) => (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2968, GIR_Done, // Label 2677: @110576 GIM_Try, /*On fail goto*//*Label 2678*/ 110591, // Rule ID 467 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 467, GIR_Done, // Label 2678: @110591 GIM_Reject, // Label 2676: @110592 GIM_Reject, // Label 2666: @110593 GIM_Try, /*On fail goto*//*Label 2679*/ 110658, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2680*/ 110642, // Rule ID 2969 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)) => (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2969, GIR_Done, // Label 2680: @110642 GIM_Try, /*On fail goto*//*Label 2681*/ 110657, // Rule ID 468 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 468, GIR_Done, // Label 2681: @110657 GIM_Reject, // Label 2679: @110658 GIM_Reject, // Label 2667: @110659 GIM_Try, /*On fail goto*//*Label 2682*/ 110726, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2683*/ 110710, // Rule ID 2899 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)) => (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2899, GIR_Done, // Label 2683: @110710 GIM_Try, /*On fail goto*//*Label 2684*/ 110725, // Rule ID 630 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 630, GIR_Done, // Label 2684: @110725 GIM_Reject, // Label 2682: @110726 GIM_Reject, // Label 2668: @110727 GIM_Try, /*On fail goto*//*Label 2685*/ 110794, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2686*/ 110778, // Rule ID 2901 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)) => (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2901, GIR_Done, // Label 2686: @110778 GIM_Try, /*On fail goto*//*Label 2687*/ 110793, // Rule ID 632 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 632, GIR_Done, // Label 2687: @110793 GIM_Reject, // Label 2685: @110794 GIM_Reject, // Label 2669: @110795 GIM_Try, /*On fail goto*//*Label 2688*/ 110862, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2689*/ 110846, // Rule ID 2902 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)) => (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2902, GIR_Done, // Label 2689: @110846 GIM_Try, /*On fail goto*//*Label 2690*/ 110861, // Rule ID 628 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 628, GIR_Done, // Label 2690: @110861 GIM_Reject, // Label 2688: @110862 GIM_Reject, // Label 2670: @110863 GIM_Try, /*On fail goto*//*Label 2691*/ 110930, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2692*/ 110914, // Rule ID 2900 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)) => (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2900, GIR_Done, // Label 2692: @110914 GIM_Try, /*On fail goto*//*Label 2693*/ 110929, // Rule ID 631 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 631, GIR_Done, // Label 2693: @110929 GIM_Reject, // Label 2691: @110930 GIM_Reject, // Label 2671: @110931 GIM_Try, /*On fail goto*//*Label 2694*/ 110998, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_Try, /*On fail goto*//*Label 2695*/ 110982, // Rule ID 2903 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)) => (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2903, GIR_Done, // Label 2695: @110982 GIM_Try, /*On fail goto*//*Label 2696*/ 110997, // Rule ID 629 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 629, GIR_Done, // Label 2696: @110997 GIM_Reject, // Label 2694: @110998 GIM_Reject, // Label 2672: @110999 GIM_Reject, // Label 55: @111000 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2705*/ 111287, /*GILLT_s16*//*Label 2697*/ 111019, /*GILLT_s32*//*Label 2698*/ 111051, /*GILLT_s64*//*Label 2699*/ 111083, 0, 0, /*GILLT_v2s32*//*Label 2700*/ 111127, /*GILLT_v2s64*//*Label 2701*/ 111159, 0, /*GILLT_v4s16*//*Label 2702*/ 111191, /*GILLT_v4s32*//*Label 2703*/ 111223, 0, 0, /*GILLT_v8s16*//*Label 2704*/ 111255, // Label 2697: @111019 GIM_Try, /*On fail goto*//*Label 2706*/ 111050, // Rule ID 508 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 508, GIR_Done, // Label 2706: @111050 GIM_Reject, // Label 2698: @111051 GIM_Try, /*On fail goto*//*Label 2707*/ 111082, // Rule ID 509 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 509, GIR_Done, // Label 2707: @111082 GIM_Reject, // Label 2699: @111083 GIM_Try, /*On fail goto*//*Label 2708*/ 111126, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2709*/ 111116, // Rule ID 510 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 510, GIR_Done, // Label 2709: @111116 GIM_Try, /*On fail goto*//*Label 2710*/ 111125, // Rule ID 2809 // // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2809, GIR_Done, // Label 2710: @111125 GIM_Reject, // Label 2708: @111126 GIM_Reject, // Label 2700: @111127 GIM_Try, /*On fail goto*//*Label 2711*/ 111158, // Rule ID 993 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 993, GIR_Done, // Label 2711: @111158 GIM_Reject, // Label 2701: @111159 GIM_Try, /*On fail goto*//*Label 2712*/ 111190, // Rule ID 995 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 995, GIR_Done, // Label 2712: @111190 GIM_Reject, // Label 2702: @111191 GIM_Try, /*On fail goto*//*Label 2713*/ 111222, // Rule ID 991 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 991, GIR_Done, // Label 2713: @111222 GIM_Reject, // Label 2703: @111223 GIM_Try, /*On fail goto*//*Label 2714*/ 111254, // Rule ID 994 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 994, GIR_Done, // Label 2714: @111254 GIM_Reject, // Label 2704: @111255 GIM_Try, /*On fail goto*//*Label 2715*/ 111286, // Rule ID 992 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 992, GIR_Done, // Label 2715: @111286 GIM_Reject, // Label 2705: @111287 GIM_Reject, // Label 56: @111288 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2724*/ 111575, /*GILLT_s16*//*Label 2716*/ 111307, /*GILLT_s32*//*Label 2717*/ 111339, /*GILLT_s64*//*Label 2718*/ 111371, 0, 0, /*GILLT_v2s32*//*Label 2719*/ 111415, /*GILLT_v2s64*//*Label 2720*/ 111447, 0, /*GILLT_v4s16*//*Label 2721*/ 111479, /*GILLT_v4s32*//*Label 2722*/ 111511, 0, 0, /*GILLT_v8s16*//*Label 2723*/ 111543, // Label 2716: @111307 GIM_Try, /*On fail goto*//*Label 2725*/ 111338, // Rule ID 502 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMHrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 502, GIR_Done, // Label 2725: @111338 GIM_Reject, // Label 2717: @111339 GIM_Try, /*On fail goto*//*Label 2726*/ 111370, // Rule ID 503 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMSrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 503, GIR_Done, // Label 2726: @111370 GIM_Reject, // Label 2718: @111371 GIM_Try, /*On fail goto*//*Label 2727*/ 111414, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2728*/ 111404, // Rule ID 504 // GIM_CheckFeatures, GIFBS_HasFPARMv8, // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 504, GIR_Done, // Label 2728: @111404 GIM_Try, /*On fail goto*//*Label 2729*/ 111413, // Rule ID 2808 // // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2808, GIR_Done, // Label 2729: @111413 GIM_Reject, // Label 2727: @111414 GIM_Reject, // Label 2719: @111415 GIM_Try, /*On fail goto*//*Label 2730*/ 111446, // Rule ID 973 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 973, GIR_Done, // Label 2730: @111446 GIM_Reject, // Label 2720: @111447 GIM_Try, /*On fail goto*//*Label 2731*/ 111478, // Rule ID 975 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 975, GIR_Done, // Label 2731: @111478 GIM_Reject, // Label 2721: @111479 GIM_Try, /*On fail goto*//*Label 2732*/ 111510, // Rule ID 971 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 971, GIR_Done, // Label 2732: @111510 GIM_Reject, // Label 2722: @111511 GIM_Try, /*On fail goto*//*Label 2733*/ 111542, // Rule ID 974 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 974, GIR_Done, // Label 2733: @111542 GIM_Reject, // Label 2723: @111543 GIM_Try, /*On fail goto*//*Label 2734*/ 111574, // Rule ID 972 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 972, GIR_Done, // Label 2734: @111574 GIM_Reject, // Label 2724: @111575 GIM_Reject, // Label 57: @111576 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 15, /*)*//*default:*//*Label 2741*/ 111784, /*GILLT_v2s32*//*Label 2735*/ 111592, 0, 0, /*GILLT_v4s16*//*Label 2736*/ 111624, /*GILLT_v4s32*//*Label 2737*/ 111656, 0, /*GILLT_v8s8*//*Label 2738*/ 111688, /*GILLT_v8s16*//*Label 2739*/ 111720, 0, /*GILLT_v16s8*//*Label 2740*/ 111752, // Label 2735: @111592 GIM_Try, /*On fail goto*//*Label 2742*/ 111623, // Rule ID 1095 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1095, GIR_Done, // Label 2742: @111623 GIM_Reject, // Label 2736: @111624 GIM_Try, /*On fail goto*//*Label 2743*/ 111655, // Rule ID 1093 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1093, GIR_Done, // Label 2743: @111655 GIM_Reject, // Label 2737: @111656 GIM_Try, /*On fail goto*//*Label 2744*/ 111687, // Rule ID 1096 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1096, GIR_Done, // Label 2744: @111687 GIM_Reject, // Label 2738: @111688 GIM_Try, /*On fail goto*//*Label 2745*/ 111719, // Rule ID 1091 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1091, GIR_Done, // Label 2745: @111719 GIM_Reject, // Label 2739: @111720 GIM_Try, /*On fail goto*//*Label 2746*/ 111751, // Rule ID 1094 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1094, GIR_Done, // Label 2746: @111751 GIM_Reject, // Label 2740: @111752 GIM_Try, /*On fail goto*//*Label 2747*/ 111783, // Rule ID 1092 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1092, GIR_Done, // Label 2747: @111783 GIM_Reject, // Label 2741: @111784 GIM_Reject, // Label 58: @111785 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 15, /*)*//*default:*//*Label 2754*/ 111993, /*GILLT_v2s32*//*Label 2748*/ 111801, 0, 0, /*GILLT_v4s16*//*Label 2749*/ 111833, /*GILLT_v4s32*//*Label 2750*/ 111865, 0, /*GILLT_v8s8*//*Label 2751*/ 111897, /*GILLT_v8s16*//*Label 2752*/ 111929, 0, /*GILLT_v16s8*//*Label 2753*/ 111961, // Label 2748: @111801 GIM_Try, /*On fail goto*//*Label 2755*/ 111832, // Rule ID 1083 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1083, GIR_Done, // Label 2755: @111832 GIM_Reject, // Label 2749: @111833 GIM_Try, /*On fail goto*//*Label 2756*/ 111864, // Rule ID 1081 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1081, GIR_Done, // Label 2756: @111864 GIM_Reject, // Label 2750: @111865 GIM_Try, /*On fail goto*//*Label 2757*/ 111896, // Rule ID 1084 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1084, GIR_Done, // Label 2757: @111896 GIM_Reject, // Label 2751: @111897 GIM_Try, /*On fail goto*//*Label 2758*/ 111928, // Rule ID 1079 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1079, GIR_Done, // Label 2758: @111928 GIM_Reject, // Label 2752: @111929 GIM_Try, /*On fail goto*//*Label 2759*/ 111960, // Rule ID 1082 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1082, GIR_Done, // Label 2759: @111960 GIM_Reject, // Label 2753: @111961 GIM_Try, /*On fail goto*//*Label 2760*/ 111992, // Rule ID 1080 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1080, GIR_Done, // Label 2760: @111992 GIM_Reject, // Label 2754: @111993 GIM_Reject, // Label 59: @111994 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 15, /*)*//*default:*//*Label 2767*/ 112202, /*GILLT_v2s32*//*Label 2761*/ 112010, 0, 0, /*GILLT_v4s16*//*Label 2762*/ 112042, /*GILLT_v4s32*//*Label 2763*/ 112074, 0, /*GILLT_v8s8*//*Label 2764*/ 112106, /*GILLT_v8s16*//*Label 2765*/ 112138, 0, /*GILLT_v16s8*//*Label 2766*/ 112170, // Label 2761: @112010 GIM_Try, /*On fail goto*//*Label 2768*/ 112041, // Rule ID 1206 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1206, GIR_Done, // Label 2768: @112041 GIM_Reject, // Label 2762: @112042 GIM_Try, /*On fail goto*//*Label 2769*/ 112073, // Rule ID 1204 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1204, GIR_Done, // Label 2769: @112073 GIM_Reject, // Label 2763: @112074 GIM_Try, /*On fail goto*//*Label 2770*/ 112105, // Rule ID 1207 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1207, GIR_Done, // Label 2770: @112105 GIM_Reject, // Label 2764: @112106 GIM_Try, /*On fail goto*//*Label 2771*/ 112137, // Rule ID 1202 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1202, GIR_Done, // Label 2771: @112137 GIM_Reject, // Label 2765: @112138 GIM_Try, /*On fail goto*//*Label 2772*/ 112169, // Rule ID 1205 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1205, GIR_Done, // Label 2772: @112169 GIM_Reject, // Label 2766: @112170 GIM_Try, /*On fail goto*//*Label 2773*/ 112201, // Rule ID 1203 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1203, GIR_Done, // Label 2773: @112201 GIM_Reject, // Label 2767: @112202 GIM_Reject, // Label 60: @112203 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 15, /*)*//*default:*//*Label 2780*/ 112411, /*GILLT_v2s32*//*Label 2774*/ 112219, 0, 0, /*GILLT_v4s16*//*Label 2775*/ 112251, /*GILLT_v4s32*//*Label 2776*/ 112283, 0, /*GILLT_v8s8*//*Label 2777*/ 112315, /*GILLT_v8s16*//*Label 2778*/ 112347, 0, /*GILLT_v16s8*//*Label 2779*/ 112379, // Label 2774: @112219 GIM_Try, /*On fail goto*//*Label 2781*/ 112250, // Rule ID 1194 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1194, GIR_Done, // Label 2781: @112250 GIM_Reject, // Label 2775: @112251 GIM_Try, /*On fail goto*//*Label 2782*/ 112282, // Rule ID 1192 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1192, GIR_Done, // Label 2782: @112282 GIM_Reject, // Label 2776: @112283 GIM_Try, /*On fail goto*//*Label 2783*/ 112314, // Rule ID 1195 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1195, GIR_Done, // Label 2783: @112314 GIM_Reject, // Label 2777: @112315 GIM_Try, /*On fail goto*//*Label 2784*/ 112346, // Rule ID 1190 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1190, GIR_Done, // Label 2784: @112346 GIM_Reject, // Label 2778: @112347 GIM_Try, /*On fail goto*//*Label 2785*/ 112378, // Rule ID 1193 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1193, GIR_Done, // Label 2785: @112378 GIM_Reject, // Label 2779: @112379 GIM_Try, /*On fail goto*//*Label 2786*/ 112410, // Rule ID 1191 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1191, GIR_Done, // Label 2786: @112410 GIM_Reject, // Label 2780: @112411 GIM_Reject, // Label 61: @112412 GIM_Try, /*On fail goto*//*Label 2787*/ 112424, // Rule ID 191 // // MIs[0] addr GIM_CheckIsMBB, /*MI*/0, /*Op*/0, // (br (bb:{ *:[Other] }):$addr) => (B (bb:{ *:[Other] }):$addr) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 191, GIR_Done, // Label 2787: @112424 GIM_Reject, // Label 62: @112425 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2791*/ 112783, /*GILLT_s16*//*Label 2788*/ 112434, /*GILLT_s32*//*Label 2789*/ 112484, /*GILLT_s64*//*Label 2790*/ 112687, // Label 2788: @112434 GIM_Try, /*On fail goto*//*Label 2792*/ 112483, // Rule ID 3278 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (CPYi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3278, GIR_Done, // Label 2792: @112483 GIM_Reject, // Label 2789: @112484 GIM_Try, /*On fail goto*//*Label 2793*/ 112535, // Rule ID 1528 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1528, GIR_Done, // Label 2793: @112535 GIM_Try, /*On fail goto*//*Label 2794*/ 112586, // Rule ID 1529 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1529, GIR_Done, // Label 2794: @112586 GIM_Try, /*On fail goto*//*Label 2795*/ 112637, // Rule ID 1530 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1530, GIR_Done, // Label 2795: @112637 GIM_Try, /*On fail goto*//*Label 2796*/ 112686, // Rule ID 3277 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (CPYi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3277, GIR_Done, // Label 2796: @112686 GIM_Reject, // Label 2790: @112687 GIM_Try, /*On fail goto*//*Label 2797*/ 112782, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 2798*/ 112740, // Rule ID 1531 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1531, GIR_Done, // Label 2798: @112740 GIM_Try, /*On fail goto*//*Label 2799*/ 112781, // Rule ID 3276 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$idx) => (CPYi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<>:$idx) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3276, GIR_Done, // Label 2799: @112781 GIM_Reject, // Label 2797: @112782 GIM_Reject, // Label 2791: @112783 GIM_Reject, // Label 63: @112784 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2802*/ 112886, /*GILLT_s32*//*Label 2800*/ 112792, /*GILLT_s64*//*Label 2801*/ 112839, // Label 2800: @112792 GIM_Try, /*On fail goto*//*Label 2803*/ 112838, // Rule ID 2406 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITWr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2406, GIR_Done, // Label 2803: @112838 GIM_Reject, // Label 2801: @112839 GIM_Try, /*On fail goto*//*Label 2804*/ 112885, // Rule ID 2407 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITXr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2407, GIR_Done, // Label 2804: @112885 GIM_Reject, // Label 2802: @112886 GIM_Reject, // Label 64: @112887 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2813*/ 113513, /*GILLT_s32*//*Label 2805*/ 112907, /*GILLT_s64*//*Label 2806*/ 113138, 0, 0, /*GILLT_v2s32*//*Label 2807*/ 113369, 0, 0, /*GILLT_v4s16*//*Label 2808*/ 113393, /*GILLT_v4s32*//*Label 2809*/ 113417, 0, /*GILLT_v8s8*//*Label 2810*/ 113441, /*GILLT_v8s16*//*Label 2811*/ 113465, 0, /*GILLT_v16s8*//*Label 2812*/ 113489, // Label 2805: @112907 GIM_Try, /*On fail goto*//*Label 2814*/ 113137, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_Try, /*On fail goto*//*Label 2815*/ 113020, // Rule ID 2408 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, // MIs[3] Rn GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2408, GIR_Done, // Label 2815: @113020 GIM_Try, /*On fail goto*//*Label 2816*/ 113123, // Rule ID 5650 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5650, GIR_Done, // Label 2816: @113123 GIM_Try, /*On fail goto*//*Label 2817*/ 113136, // Rule ID 150 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 150, GIR_Done, // Label 2817: @113136 GIM_Reject, // Label 2814: @113137 GIM_Reject, // Label 2806: @113138 GIM_Try, /*On fail goto*//*Label 2818*/ 113368, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_Try, /*On fail goto*//*Label 2819*/ 113251, // Rule ID 2409 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, // MIs[3] Rn GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2409, GIR_Done, // Label 2819: @113251 GIM_Try, /*On fail goto*//*Label 2820*/ 113354, // Rule ID 5651 // GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, // MIs[4] Rn GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 5651, GIR_Done, // Label 2820: @113354 GIM_Try, /*On fail goto*//*Label 2821*/ 113367, // Rule ID 151 // GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 151, GIR_Done, // Label 2821: @113367 GIM_Reject, // Label 2818: @113368 GIM_Reject, // Label 2807: @113369 GIM_Try, /*On fail goto*//*Label 2822*/ 113392, // Rule ID 589 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv2i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 589, GIR_Done, // Label 2822: @113392 GIM_Reject, // Label 2808: @113393 GIM_Try, /*On fail goto*//*Label 2823*/ 113416, // Rule ID 587 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 587, GIR_Done, // Label 2823: @113416 GIM_Reject, // Label 2809: @113417 GIM_Try, /*On fail goto*//*Label 2824*/ 113440, // Rule ID 590 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 590, GIR_Done, // Label 2824: @113440 GIM_Reject, // Label 2810: @113441 GIM_Try, /*On fail goto*//*Label 2825*/ 113464, // Rule ID 585 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 585, GIR_Done, // Label 2825: @113464 GIM_Reject, // Label 2811: @113465 GIM_Try, /*On fail goto*//*Label 2826*/ 113488, // Rule ID 588 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 588, GIR_Done, // Label 2826: @113488 GIM_Reject, // Label 2812: @113489 GIM_Try, /*On fail goto*//*Label 2827*/ 113512, // Rule ID 586 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 586, GIR_Done, // Label 2827: @113512 GIM_Reject, // Label 2813: @113513 GIM_Reject, // Label 65: @113514 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/11, 15, /*)*//*default:*//*Label 2830*/ 113572, /*GILLT_v8s8*//*Label 2828*/ 113524, 0, 0, /*GILLT_v16s8*//*Label 2829*/ 113548, // Label 2828: @113524 GIM_Try, /*On fail goto*//*Label 2831*/ 113547, // Rule ID 626 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv8i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 626, GIR_Done, // Label 2831: @113547 GIM_Reject, // Label 2829: @113548 GIM_Try, /*On fail goto*//*Label 2832*/ 113571, // Rule ID 627 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv16i8, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 627, GIR_Done, // Label 2832: @113571 GIM_Reject, // Label 2830: @113572 GIM_Reject, // Label 66: @113573 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2835*/ 113625, /*GILLT_s32*//*Label 2833*/ 113581, /*GILLT_s64*//*Label 2834*/ 113603, // Label 2833: @113581 GIM_Try, /*On fail goto*//*Label 2836*/ 113602, // Rule ID 155 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 155, GIR_Done, // Label 2836: @113602 GIM_Reject, // Label 2834: @113603 GIM_Try, /*On fail goto*//*Label 2837*/ 113624, // Rule ID 156 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 156, GIR_Done, // Label 2837: @113624 GIM_Reject, // Label 2835: @113625 GIM_Reject, // Label 67: @113626 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2840*/ 113678, /*GILLT_s32*//*Label 2838*/ 113634, /*GILLT_s64*//*Label 2839*/ 113656, // Label 2838: @113634 GIM_Try, /*On fail goto*//*Label 2841*/ 113655, // Rule ID 152 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITWr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 152, GIR_Done, // Label 2841: @113655 GIM_Reject, // Label 2839: @113656 GIM_Try, /*On fail goto*//*Label 2842*/ 113677, // Rule ID 153 // GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITXr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 153, GIR_Done, // Label 2842: @113677 GIM_Reject, // Label 2840: @113678 GIM_Reject, // Label 68: @113679 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2851*/ 113890, /*GILLT_s16*//*Label 2843*/ 113698, /*GILLT_s32*//*Label 2844*/ 113722, /*GILLT_s64*//*Label 2845*/ 113746, 0, 0, /*GILLT_v2s32*//*Label 2846*/ 113770, /*GILLT_v2s64*//*Label 2847*/ 113794, 0, /*GILLT_v4s16*//*Label 2848*/ 113818, /*GILLT_v4s32*//*Label 2849*/ 113842, 0, 0, /*GILLT_v8s16*//*Label 2850*/ 113866, // Label 2843: @113698 GIM_Try, /*On fail goto*//*Label 2852*/ 113721, // Rule ID 484 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 484, GIR_Done, // Label 2852: @113721 GIM_Reject, // Label 2844: @113722 GIM_Try, /*On fail goto*//*Label 2853*/ 113745, // Rule ID 485 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 485, GIR_Done, // Label 2853: @113745 GIM_Reject, // Label 2845: @113746 GIM_Try, /*On fail goto*//*Label 2854*/ 113769, // Rule ID 486 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 486, GIR_Done, // Label 2854: @113769 GIM_Reject, // Label 2846: @113770 GIM_Try, /*On fail goto*//*Label 2855*/ 113793, // Rule ID 741 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 741, GIR_Done, // Label 2855: @113793 GIM_Reject, // Label 2847: @113794 GIM_Try, /*On fail goto*//*Label 2856*/ 113817, // Rule ID 743 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 743, GIR_Done, // Label 2856: @113817 GIM_Reject, // Label 2848: @113818 GIM_Try, /*On fail goto*//*Label 2857*/ 113841, // Rule ID 739 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 739, GIR_Done, // Label 2857: @113841 GIM_Reject, // Label 2849: @113842 GIM_Try, /*On fail goto*//*Label 2858*/ 113865, // Rule ID 742 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 742, GIR_Done, // Label 2858: @113865 GIM_Reject, // Label 2850: @113866 GIM_Try, /*On fail goto*//*Label 2859*/ 113889, // Rule ID 740 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 740, GIR_Done, // Label 2859: @113889 GIM_Reject, // Label 2851: @113890 GIM_Reject, // Label 69: @113891 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2868*/ 114102, /*GILLT_s16*//*Label 2860*/ 113910, /*GILLT_s32*//*Label 2861*/ 113934, /*GILLT_s64*//*Label 2862*/ 113958, 0, 0, /*GILLT_v2s32*//*Label 2863*/ 113982, /*GILLT_v2s64*//*Label 2864*/ 114006, 0, /*GILLT_v4s16*//*Label 2865*/ 114030, /*GILLT_v4s32*//*Label 2866*/ 114054, 0, 0, /*GILLT_v8s16*//*Label 2867*/ 114078, // Label 2860: @113910 GIM_Try, /*On fail goto*//*Label 2869*/ 113933, // Rule ID 493 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 493, GIR_Done, // Label 2869: @113933 GIM_Reject, // Label 2861: @113934 GIM_Try, /*On fail goto*//*Label 2870*/ 113957, // Rule ID 494 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 494, GIR_Done, // Label 2870: @113957 GIM_Reject, // Label 2862: @113958 GIM_Try, /*On fail goto*//*Label 2871*/ 113981, // Rule ID 495 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 495, GIR_Done, // Label 2871: @113981 GIM_Reject, // Label 2863: @113982 GIM_Try, /*On fail goto*//*Label 2872*/ 114005, // Rule ID 761 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 761, GIR_Done, // Label 2872: @114005 GIM_Reject, // Label 2864: @114006 GIM_Try, /*On fail goto*//*Label 2873*/ 114029, // Rule ID 763 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 763, GIR_Done, // Label 2873: @114029 GIM_Reject, // Label 2865: @114030 GIM_Try, /*On fail goto*//*Label 2874*/ 114053, // Rule ID 759 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 759, GIR_Done, // Label 2874: @114053 GIM_Reject, // Label 2866: @114054 GIM_Try, /*On fail goto*//*Label 2875*/ 114077, // Rule ID 762 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 762, GIR_Done, // Label 2875: @114077 GIM_Reject, // Label 2867: @114078 GIM_Try, /*On fail goto*//*Label 2876*/ 114101, // Rule ID 760 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 760, GIR_Done, // Label 2876: @114101 GIM_Reject, // Label 2868: @114102 GIM_Reject, // Label 70: @114103 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2885*/ 114314, /*GILLT_s16*//*Label 2877*/ 114122, /*GILLT_s32*//*Label 2878*/ 114146, /*GILLT_s64*//*Label 2879*/ 114170, 0, 0, /*GILLT_v2s32*//*Label 2880*/ 114194, /*GILLT_v2s64*//*Label 2881*/ 114218, 0, /*GILLT_v4s16*//*Label 2882*/ 114242, /*GILLT_v4s32*//*Label 2883*/ 114266, 0, 0, /*GILLT_v8s16*//*Label 2884*/ 114290, // Label 2877: @114122 GIM_Try, /*On fail goto*//*Label 2886*/ 114145, // Rule ID 478 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 478, GIR_Done, // Label 2886: @114145 GIM_Reject, // Label 2878: @114146 GIM_Try, /*On fail goto*//*Label 2887*/ 114169, // Rule ID 479 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 479, GIR_Done, // Label 2887: @114169 GIM_Reject, // Label 2879: @114170 GIM_Try, /*On fail goto*//*Label 2888*/ 114193, // Rule ID 480 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 480, GIR_Done, // Label 2888: @114193 GIM_Reject, // Label 2880: @114194 GIM_Try, /*On fail goto*//*Label 2889*/ 114217, // Rule ID 731 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 731, GIR_Done, // Label 2889: @114217 GIM_Reject, // Label 2881: @114218 GIM_Try, /*On fail goto*//*Label 2890*/ 114241, // Rule ID 733 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 733, GIR_Done, // Label 2890: @114241 GIM_Reject, // Label 2882: @114242 GIM_Try, /*On fail goto*//*Label 2891*/ 114265, // Rule ID 729 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 729, GIR_Done, // Label 2891: @114265 GIM_Reject, // Label 2883: @114266 GIM_Try, /*On fail goto*//*Label 2892*/ 114289, // Rule ID 732 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 732, GIR_Done, // Label 2892: @114289 GIM_Reject, // Label 2884: @114290 GIM_Try, /*On fail goto*//*Label 2893*/ 114313, // Rule ID 730 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 730, GIR_Done, // Label 2893: @114313 GIM_Reject, // Label 2885: @114314 GIM_Reject, // Label 71: @114315 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2902*/ 114526, /*GILLT_s16*//*Label 2894*/ 114334, /*GILLT_s32*//*Label 2895*/ 114358, /*GILLT_s64*//*Label 2896*/ 114382, 0, 0, /*GILLT_v2s32*//*Label 2897*/ 114406, /*GILLT_v2s64*//*Label 2898*/ 114430, 0, /*GILLT_v4s16*//*Label 2899*/ 114454, /*GILLT_v4s32*//*Label 2900*/ 114478, 0, 0, /*GILLT_v8s16*//*Label 2901*/ 114502, // Label 2894: @114334 GIM_Try, /*On fail goto*//*Label 2903*/ 114357, // Rule ID 487 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 487, GIR_Done, // Label 2903: @114357 GIM_Reject, // Label 2895: @114358 GIM_Try, /*On fail goto*//*Label 2904*/ 114381, // Rule ID 488 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXSr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 488, GIR_Done, // Label 2904: @114381 GIM_Reject, // Label 2896: @114382 GIM_Try, /*On fail goto*//*Label 2905*/ 114405, // Rule ID 489 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 489, GIR_Done, // Label 2905: @114405 GIM_Reject, // Label 2897: @114406 GIM_Try, /*On fail goto*//*Label 2906*/ 114429, // Rule ID 746 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 746, GIR_Done, // Label 2906: @114429 GIM_Reject, // Label 2898: @114430 GIM_Try, /*On fail goto*//*Label 2907*/ 114453, // Rule ID 748 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 748, GIR_Done, // Label 2907: @114453 GIM_Reject, // Label 2899: @114454 GIM_Try, /*On fail goto*//*Label 2908*/ 114477, // Rule ID 744 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 744, GIR_Done, // Label 2908: @114477 GIM_Reject, // Label 2900: @114478 GIM_Try, /*On fail goto*//*Label 2909*/ 114501, // Rule ID 747 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 747, GIR_Done, // Label 2909: @114501 GIM_Reject, // Label 2901: @114502 GIM_Try, /*On fail goto*//*Label 2910*/ 114525, // Rule ID 745 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 745, GIR_Done, // Label 2910: @114525 GIM_Reject, // Label 2902: @114526 GIM_Reject, // Label 72: @114527 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 13, /*)*//*default:*//*Label 2919*/ 114738, /*GILLT_s16*//*Label 2911*/ 114546, /*GILLT_s32*//*Label 2912*/ 114570, /*GILLT_s64*//*Label 2913*/ 114594, 0, 0, /*GILLT_v2s32*//*Label 2914*/ 114618, /*GILLT_v2s64*//*Label 2915*/ 114642, 0, /*GILLT_v4s16*//*Label 2916*/ 114666, /*GILLT_v4s32*//*Label 2917*/ 114690, 0, 0, /*GILLT_v8s16*//*Label 2918*/ 114714, // Label 2911: @114546 GIM_Try, /*On fail goto*//*Label 2920*/ 114569, // Rule ID 475 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIHr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 475, GIR_Done, // Label 2920: @114569 GIM_Reject, // Label 2912: @114570 GIM_Try, /*On fail goto*//*Label 2921*/ 114593, // Rule ID 476 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTISr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 476, GIR_Done, // Label 2921: @114593 GIM_Reject, // Label 2913: @114594 GIM_Try, /*On fail goto*//*Label 2922*/ 114617, // Rule ID 477 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIDr, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 477, GIR_Done, // Label 2922: @114617 GIM_Reject, // Label 2914: @114618 GIM_Try, /*On fail goto*//*Label 2923*/ 114641, // Rule ID 726 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 726, GIR_Done, // Label 2923: @114641 GIM_Reject, // Label 2915: @114642 GIM_Try, /*On fail goto*//*Label 2924*/ 114665, // Rule ID 728 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f64, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 728, GIR_Done, // Label 2924: @114665 GIM_Reject, // Label 2916: @114666 GIM_Try, /*On fail goto*//*Label 2925*/ 114689, // Rule ID 724 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 724, GIR_Done, // Label 2925: @114689 GIM_Reject, // Label 2917: @114690 GIM_Try, /*On fail goto*//*Label 2926*/ 114713, // Rule ID 727 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f32, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 727, GIR_Done, // Label 2926: @114713 GIM_Reject, // Label 2918: @114714 GIM_Try, /*On fail goto*//*Label 2927*/ 114737, // Rule ID 725 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv8f16, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 725, GIR_Done, // Label 2927: @114737 GIM_Reject, // Label 2919: @114738 GIM_Reject, // Label 73: @114739 GIM_Reject, }; return MatchTable0; } #endif // ifdef GET_GLOBALISEL_IMPL #ifdef GET_GLOBALISEL_PREDICATES_DECL PredicateBitset AvailableModuleFeatures; mutable PredicateBitset AvailableFunctionFeatures; PredicateBitset getAvailableFeatures() const { return AvailableModuleFeatures | AvailableFunctionFeatures; } PredicateBitset computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const; PredicateBitset computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const; void setupGeneratedPerFunctionState(MachineFunction &MF) override; #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL #ifdef GET_GLOBALISEL_PREDICATES_INIT AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), AvailableFunctionFeatures() #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT