Lines Matching full:way

68 	 * Data cache operations by set/way to the level specified
108 	ubfx	r4, r12, #3, #10	// r4 = maximum way number (right aligned)
109 	clz	r5, r4			// r5 = the bit position of the way size increment
110 	mov	r9, r4			// r9 working copy of the aligned max way number
116 	orr	r0, r1, r9, LSL r5	// factor in the way number and cache level into r0
122 	subs	r9, r9, #1		// decrement the way number
149 	 * Data cache operations by set/way till PoU.
161 	 * Data cache operations by set/way till PoC.
174 	 *  Helper macro for data cache operations by set/way for the
186 	 * Data cache operations by set/way for level 1 cache
198 	 * Data cache operations by set/way for level 2 cache
210 	 * Data cache operations by set/way for level 3 cache