Lines Matching refs:arm64
73 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in set_mem_access()
76 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; in set_mem_access()
77 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_… in set_mem_access()
78 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG… in set_mem_access()
79 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; in set_mem_access()
82 MI->flat_insn->detail->arm64.op_count++; in set_mem_access()
142 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
145 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
146 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
147 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
150 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
153 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
154 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg… in AArch64_printInst()
155 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
207 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
210 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
211 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
212 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
215 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
218 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
219 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
220 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
223 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
226 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
227 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; in AArch64_printInst()
228 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
250 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
253 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
254 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
255 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
258 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
261 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
262 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
263 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
266 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
269 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
270 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 :… in AArch64_printInst()
271 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
274 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
277 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
278 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getIm… in AArch64_printInst()
279 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
299 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
302 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
303 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
304 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
307 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
310 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
311 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
312 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
315 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
318 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
319 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getIm… in AArch64_printInst()
320 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
323 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
326 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
327 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getIm… in AArch64_printInst()
328 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
358 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
361 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
362 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
363 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
366 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
369 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
370 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
371 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
374 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
377 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
378 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; in AArch64_printInst()
379 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
382 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
385 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
386 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; in AArch64_printInst()
387 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
408 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
411 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
412 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
413 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
416 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
419 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in AArch64_printInst()
420 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in AArch64_printInst()
421 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
424 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
427 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
428 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; in AArch64_printInst()
429 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
432 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in AArch64_printInst()
435 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in AArch64_printInst()
436 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; in AArch64_printInst()
437 MI->flat_insn->detail->arm64.op_count++; in AArch64_printInst()
702 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSysAlias()
705 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; in printSysAlias()
706 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = op_ic + op_dc +… in printSysAlias()
707 MI->flat_insn->detail->arm64.op_count++; in printSysAlias()
717 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSysAlias()
720 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printSysAlias()
721 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; in printSysAlias()
722 MI->flat_insn->detail->arm64.op_count++; in printSysAlias()
739 …if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64… in printOperand()
740 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; in printOperand()
742 …else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index ==… in printOperand()
743 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; in printOperand()
749 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printOperand()
752 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printOperand()
753 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; in printOperand()
754 MI->flat_insn->detail->arm64.op_count++; in printOperand()
776 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)i… in printOperand()
781 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printOperand()
784 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printOperand()
785 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; in printOperand()
786 MI->flat_insn->detail->arm64.op_count++; in printOperand()
800 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printHexImm()
803 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printHexImm()
804 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getIm… in printHexImm()
805 MI->flat_insn->detail->arm64.op_count++; in printHexImm()
822 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printPostIncOperand()
825 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printPostIncOperand()
826 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; in printPostIncOperand()
827 MI->flat_insn->detail->arm64.op_count++; in printPostIncOperand()
835 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printPostIncOperand()
838 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printPostIncOperand()
839 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; in printPostIncOperand()
840 MI->flat_insn->detail->arm64.op_count++; in printPostIncOperand()
862 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printVRegOperand()
865 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printVRegOperand()
866 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vre… in printVRegOperand()
867 MI->flat_insn->detail->arm64.op_count++; in printVRegOperand()
880 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSysCROperand()
883 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; in printSysCROperand()
884 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getIm… in printSysCROperand()
885 MI->flat_insn->detail->arm64.op_count++; in printSysCROperand()
903 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printAddSubImm()
906 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printAddSubImm()
907 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; in printAddSubImm()
908 MI->flat_insn->detail->arm64.op_count++; in printAddSubImm()
927 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printLogicalImm32()
930 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printLogicalImm32()
931 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; in printLogicalImm32()
932 MI->flat_insn->detail->arm64.op_count++; in printLogicalImm32()
961 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printLogicalImm64()
964 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printLogicalImm64()
965 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val; in printLogicalImm64()
966 MI->flat_insn->detail->arm64.op_count++; in printLogicalImm64()
1002 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shif… in printShifter()
1003 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AAr… in printShifter()
1014 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printShiftedRegister()
1017 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printShiftedRegister()
1018 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getRe… in printShiftedRegister()
1019 MI->flat_insn->detail->arm64.op_count++; in printShiftedRegister()
1044 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM6… in printArithExtend()
1045 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = Shi… in printArithExtend()
1084 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; in printArithExtend()
1091 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM6… in printArithExtend()
1092 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = Shi… in printArithExtend()
1106 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printExtendedRegister()
1109 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printExtendedRegister()
1110 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; in printExtendedRegister()
1111 MI->flat_insn->detail->arm64.op_count++; in printExtendedRegister()
1127 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SF… in printMemExtend()
1136 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; in printMemExtend()
1139 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; in printMemExtend()
1142 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; in printMemExtend()
1149 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; in printMemExtend()
1152 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; in printMemExtend()
1155 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; in printMemExtend()
1158 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; in printMemExtend()
1168 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SF… in printMemExtend()
1169 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32… in printMemExtend()
1180 MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); in printCondCode()
1189 MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); in printInverseCondCode()
1201 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)v… in printImmScale()
1206 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printImmScale()
1209 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printImmScale()
1210 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; in printImmScale()
1211 MI->flat_insn->detail->arm64.op_count++; in printImmScale()
1225 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)v… in printUImm12Offset()
1230 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printUImm12Offset()
1233 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printUImm12Offset()
1234 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val; in printUImm12Offset()
1235 MI->flat_insn->detail->arm64.op_count++; in printUImm12Offset()
1255 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PREFE… in printPrefetchOp()
1257 … MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].prefetch = prfop + 1; in printPrefetchOp()
1258 MI->flat_insn->detail->arm64.op_count++; in printPrefetchOp()
1266 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printPrefetchOp()
1269 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printPrefetchOp()
1270 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; in printPrefetchOp()
1271 MI->flat_insn->detail->arm64.op_count++; in printPrefetchOp()
1292 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printFPImmOperand()
1295 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; in printFPImmOperand()
1296 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; in printFPImmOperand()
1297 MI->flat_insn->detail->arm64.op_count++; in printFPImmOperand()
1389 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printVectorList()
1392 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; in printVectorList()
1393 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vre… in printVectorList()
1394 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; in printVectorList()
1395 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess; in printVectorList()
1396 MI->flat_insn->detail->arm64.op_count++; in printVectorList()
1494 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (i… in printVectorIndex()
1511 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printAlignedLabel()
1514 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printAlignedLabel()
1515 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; in printAlignedLabel()
1516 MI->flat_insn->detail->arm64.op_count++; in printAlignedLabel()
1536 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printAdrpLabel()
1539 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printAdrpLabel()
1540 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; in printAdrpLabel()
1541 MI->flat_insn->detail->arm64.op_count++; in printAdrpLabel()
1565 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printBarrierOption()
1568 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRI… in printBarrierOption()
1569 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; in printBarrierOption()
1570 MI->flat_insn->detail->arm64.op_count++; in printBarrierOption()
1578 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printBarrierOption()
1581 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printBarrierOption()
1582 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; in printBarrierOption()
1583 MI->flat_insn->detail->arm64.op_count++; in printBarrierOption()
1600 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printMRSSystemRegister()
1603 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_M… in printMRSSystemRegister()
1604 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; in printMRSSystemRegister()
1605 MI->flat_insn->detail->arm64.op_count++; in printMRSSystemRegister()
1621 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printMSRSystemRegister()
1624 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_M… in printMSRSystemRegister()
1625 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; in printMSRSystemRegister()
1626 MI->flat_insn->detail->arm64.op_count++; in printMSRSystemRegister()
1643 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSystemPStateField()
1646 …MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTAT… in printSystemPStateField()
1647 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; in printSystemPStateField()
1648 MI->flat_insn->detail->arm64.op_count++; in printSystemPStateField()
1657 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSystemPStateField()
1660 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printSystemPStateField()
1661 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; in printSystemPStateField()
1662 MI->flat_insn->detail->arm64.op_count++; in printSystemPStateField()
1675 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in printSIMDType10Operand()
1678 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; in printSIMDType10Operand()
1679 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; in printSIMDType10Operand()
1680 MI->flat_insn->detail->arm64.op_count++; in printSIMDType10Operand()
1936 flat_insn->detail->arm64.writeback = true; in AArch64_post_printer()