409   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
411     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
413     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
415     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
446   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
542     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
544       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
546       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
548       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
590     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
685       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
715     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1257         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1307             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1348         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1399       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1400         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
1403       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()