Lines Matching defs:DAG
1448 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, in LowerCallResult()
1531 SelectionDAG &DAG, in LowerMemOpCallTo()
1544 void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, in PassF64ArgInRegs()
1577 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
2224 const SDLoc &DL, SelectionDAG &DAG) { in LowerInterruptReturn()
2470 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) { in LowerWRITE_REGISTER()
2492 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { in LowerConstantPool()
2712 SelectionDAG &DAG, in LowerToTLSExecModels()
2920 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, in LowerINTRINSIC_WO_CHAIN()
2999 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, in LowerATOMIC_FENCE()
3032 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, in LowerPREFETCH()
3059 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { in LowerVASTART()
3076 SelectionDAG &DAG, in GetF64FormalArgument()
3119 int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, in StoreByValRegs()
3174 void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, in VarArgStyleRegisters()
3196 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { in LowerFormalArguments()
3422 SDValue &ARMcc, SelectionDAG &DAG, in getARMCmp()
3480 SelectionDAG &DAG, const SDLoc &dl) const { in getVFPCmp()
3512 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, in getARMXALUOOp()
3961 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { in bitcastf32Toi32()
3974 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, in expandf64Toi32()
4152 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { in LowerVectorFP_TO_INT()
4190 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { in LowerVectorINT_TO_FP()
4383 SelectionDAG &DAG) { in ExpandREAD_REGISTER()
4408 SelectionDAG &DAG) { in CombineVMOVDRRCandidateWithVecOp()
4455 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { in ExpandBITCAST()
4506 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) { in getZeroVector()
4603 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, in LowerCTTZ()
4702 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) { in getCTPOP16BitCounts()
4724 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) { in lowerCTPOP16BitElements()
4759 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) { in lowerCTPOP32BitElements()
4782 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG, in LowerCTPOP()
4797 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, in LowerShift()
4833 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, in Expand64BitShift()
4870 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { in LowerVSETCC()
5010 static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) { in LowerSETCCE()
5038 unsigned SplatBitSize, SelectionDAG &DAG, in isNEONModifiedImm()
5173 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG, in LowerConstantFP()
5628 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, in IsSingleInstrConstant()
5647 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, in LowerBUILD_VECTOR()
6102 SDValue RHS, SelectionDAG &DAG, in GeneratePerfectShuffle()
6179 SelectionDAG &DAG) { in LowerVECTOR_SHUFFLEv8i8()
6199 SelectionDAG &DAG) { in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6215 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { in LowerVECTOR_SHUFFLE()
6388 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { in LowerINSERT_VECTOR_ELT()
6397 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { in LowerEXTRACT_VECTOR_ELT()
6413 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { in LowerCONCAT_VECTORS()
6436 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, in isExtendedBUILD_VECTOR()
6489 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended()
6499 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended()
6527 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, in AddRequiredExtensionForVMULL()
6549 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) { in SkipLoadExtensionForVMULL()
6574 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) { in SkipExtensionForVMULL()
6613 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { in isAddSubSExt()
6624 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { in isAddSubZExt()
6635 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { in LowerMUL()
6711 SelectionDAG &DAG) { in LowerSDIV_v4i8()
6742 SelectionDAG &DAG) { in LowerSDIV_v4i16()
6780 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { in LowerSDIV()
6815 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { in LowerUDIV()
6891 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { in LowerADDC_ADDE_SUBC_SUBE()
6988 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, in LowerWindowsDIVLibCall()
7025 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, in LowerDIV_Windows()
7038 SDValue Op, SelectionDAG &DAG, bool Signed, in ExpandDIV_Windows()
7067 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { in LowerAtomicLoadStore()
7079 SelectionDAG &DAG, in ReplaceREADCYCLECOUNTER()
7100 static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) { in createGPRPairNode()
7117 SelectionDAG &DAG) { in ReplaceCMP_SWAP_64Results()
8607 SelectionDAG &DAG) { in isConditionalZeroOrAllOnes()
8681 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse() local
8779 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL() local
8924 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitMLAL() local
9010 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitUMAAL() local
9112 SelectionDAG &DAG = DCI.DAG; in PerformVMULCombine() local
9140 SelectionDAG &DAG = DCI.DAG; in PerformMULCombine() local
9229 SelectionDAG &DAG = DCI.DAG; in PerformANDCombine() local
9271 SelectionDAG &DAG = DCI.DAG; in PerformORCombine() local
9464 SelectionDAG &DAG = DCI.DAG; in PerformXORCombine() local
9630 SelectionDAG &DAG = DCI.DAG; in PerformVMOVRRDCombine() local
9657 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { in PerformVMOVDRRCombine()
9696 SelectionDAG &DAG = DCI.DAG; in PerformBUILD_VECTORCombine() local
9775 SelectionDAG &DAG = DCI.DAG; in PerformARMBUILD_VECTORCombine() local
9824 SelectionDAG &DAG = DCI.DAG; in PerformInsertEltCombine() local
9840 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { in PerformVECTOR_SHUFFLECombine()
9897 SelectionDAG &DAG = DCI.DAG; in CombineBaseUpdate() local
10113 SelectionDAG &DAG = DCI.DAG; in CombineVLDDUP() local
10247 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
10330 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
10353 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
10390 static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, in PerformVCVTCombine()
10447 static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, in PerformVDIVCombine()
10550 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { in PerformIntrinsicCombine()
10697 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, in PerformShiftCombine()
10747 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, in PerformExtendCombine()
10785 static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero, in computeKnownBits()
11457 SelectionDAG &DAG) { in getARMIndexedAddressParts()
11516 SelectionDAG &DAG) { in getT2IndexedAddressParts()
11631 const SelectionDAG &DAG, in computeKnownBitsForTargetNode()