Lines Matching refs:TUL
98 void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { in SetupTUL() argument
99 (*TUL)[HexagonII::TypeCVI_VA] = in SetupTUL()
101 (*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); in SetupTUL()
102 (*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); in SetupTUL()
103 (*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2); in SetupTUL()
104 (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); in SetupTUL()
105 (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); in SetupTUL()
106 (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); in SetupTUL()
107 (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1); in SetupTUL()
108 (*TUL)[HexagonII::TypeCVI_VM_LD] = in SetupTUL()
110 (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0); in SetupTUL()
111 (*TUL)[HexagonII::TypeCVI_VM_CUR_LD] = in SetupTUL()
113 (*TUL)[HexagonII::TypeCVI_VM_VP_LDU] = UnitsAndLanes(CVI_XLANE, 1); in SetupTUL()
114 (*TUL)[HexagonII::TypeCVI_VM_ST] = in SetupTUL()
116 (*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0); in SetupTUL()
117 (*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1); in SetupTUL()
118 (*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4); in SetupTUL()
121 HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL, in HexagonCVIResource() argument
124 : HexagonResource(s), TUL(TUL) { in HexagonCVIResource()
127 if (TUL->count(T)) { in HexagonCVIResource()
130 setUnits((*TUL)[T].first); in HexagonCVIResource()
131 setLanes((*TUL)[T].second); in HexagonCVIResource()
148 HexagonCVIResource::SetupTUL(&TUL, STI.getCPU()); in HexagonShuffler()
159 HexagonInstr PI(&TUL, MCII, ID, Extender, S, X); in append()