Lines Matching refs:opstr
1096 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1100 !strconcat(opstr, "\t$rd, $rs, $rt"),
1101 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1108 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1113 !strconcat(opstr, "\t$rt, $rs, $imm16"),
1115 Itin, FrmI, opstr> {
1121 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
1123 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
1130 class LogicNOR<string opstr, RegisterOperand RO>:
1132 !strconcat(opstr, "\t$rd, $rs, $rt"),
1133 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1138 class shift_rotate_imm<string opstr, Operand ImmOpnd,
1143 !strconcat(opstr, "\t$rd, $rt, $shamt"),
1144 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1148 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
1151 !strconcat(opstr, "\t$rd, $rt, $rs"),
1153 opstr>;
1156 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
1157 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
1158 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
1164 class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
1168 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1169 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
1175 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1177 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1179 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
1182 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1183 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
1188 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1191 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1195 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1198 !strconcat(opstr, "\t$rt, $addr"),
1204 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1206 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1212 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
1215 !strconcat(opstr, "\t$rt, $addr"),
1216 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
1221 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
1224 !strconcat(opstr, "\t$rt, $addr"),
1225 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
1231 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
1233 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1234 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
1239 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
1241 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1242 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
1248 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
1251 !strconcat(opstr, "\t$rs, $rt, $offset"),
1253 FrmI, opstr> {
1261 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
1264 !strconcat(opstr, "\t$rs, $offset"),
1266 FrmI, opstr> {
1275 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1277 !strconcat(opstr, "\t$rd, $rs, $rt"),
1279 II_SLT_SLTU, FrmR, opstr>;
1281 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1284 !strconcat(opstr, "\t$rt, $rs, $imm16"),
1286 II_SLTI_SLTIU, FrmI, opstr>;
1289 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
1291 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
1316 class JumpFR<string opstr, RegisterOperand RO,
1319 FrmR, opstr>;
1322 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
1329 class JumpLink<string opstr, DAGOperand opnd> :
1330 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
1331 [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> {
1340 class JumpLinkReg<string opstr, RegisterOperand RO>:
1341 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1342 [], II_JALR, FrmR, opstr>;
1344 class BGEZAL_FT<string opstr, DAGOperand opnd,
1347 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
1378 class SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> :
1380 !strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>;
1382 class BRK_FT<string opstr> :
1384 !strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK,
1385 FrmOther, opstr>;
1388 class ER_FT<string opstr, InstrItinClass itin = NoItinerary> :
1390 opstr, [], itin, FrmOther, opstr>;
1393 class WAIT_FT<string opstr> :
1394 InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>;
1398 class DEI_FT<string opstr, RegisterOperand RO,
1401 !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;
1405 class SYNC_FT<string opstr> :
1407 [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;
1409 class SYNCI_FT<string opstr> :
1410 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
1411 II_SYNCI, FrmOther, opstr> {
1417 class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
1420 !strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>;
1422 class TEQI_FT<string opstr, RegisterOperand RO,
1425 !strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>;
1429 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1431 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1432 itin, FrmR, opstr> {
1465 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1467 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1468 [], itin, FrmR, opstr> {
1477 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1478 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1479 FrmR, opstr> {
1489 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1490 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1491 FrmR, opstr> {
1496 class EffectiveAddress<string opstr, RegisterOperand RO> :
1497 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1499 !strconcat(opstr, "_lea")> {
1506 class CountLeading0<string opstr, RegisterOperand RO,
1508 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1509 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
1511 class CountLeading1<string opstr, RegisterOperand RO,
1513 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1514 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
1517 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1519 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1520 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1523 class SubwordSwap<string opstr, RegisterOperand RO,
1525 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1526 FrmR, opstr> {
1536 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1540 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1542 FrmR, opstr>, ISA_MIPS32R2;
1544 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1547 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1549 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1563 class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
1564 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1565 [], II_LL, FrmI, opstr> {
1570 class SCBase<string opstr, RegisterOperand RO> :
1572 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {