Lines Matching refs:dst
18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, cl}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, cl}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, cl}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 "shl{q}\t{%cl, $dst|$dst, cl}",
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
49 "shl{q}\t{$src2, $dst|$dst, $src2}",
50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
57 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
58 "shl{b}\t$dst", [], IIC_SR>;
59 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
60 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
61 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
62 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
63 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
64 "shl{q}\t$dst", [], IIC_SR>;
66 } // Constraints = "$src = $dst", SchedRW
73 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
74 "shl{b}\t{%cl, $dst|$dst, cl}",
75 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
76 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
77 "shl{w}\t{%cl, $dst|$dst, cl}",
78 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
80 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
81 "shl{l}\t{%cl, $dst|$dst, cl}",
82 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
84 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
85 "shl{q}\t{%cl, $dst|$dst, cl}",
86 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
88 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
89 "shl{b}\t{$src, $dst|$dst, $src}",
90 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
92 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
93 "shl{w}\t{$src, $dst|$dst, $src}",
94 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
96 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
97 "shl{l}\t{$src, $dst|$dst, $src}",
98 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
100 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
101 "shl{q}\t{$src, $dst|$dst, $src}",
102 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
106 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
107 "shl{b}\t$dst",
108 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
110 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
111 "shl{w}\t$dst",
112 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
114 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
115 "shl{l}\t$dst",
116 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
118 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
119 "shl{q}\t$dst",
120 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
127 "shr{b}\t{%cl, $dst|$dst, cl}",
128 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
130 "shr{w}\t{%cl, $dst|$dst, cl}",
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
133 "shr{l}\t{%cl, $dst|$dst, cl}",
134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
136 "shr{q}\t{%cl, $dst|$dst, cl}",
137 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
141 "shr{b}\t{$src2, $dst|$dst, $src2}",
142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
144 "shr{w}\t{$src2, $dst|$dst, $src2}",
145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
148 "shr{l}\t{$src2, $dst|$dst, $src2}",
149 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
152 "shr{q}\t{$src2, $dst|$dst, $src2}",
153 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
157 "shr{b}\t$dst",
158 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
160 "shr{w}\t$dst",
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
162 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
163 "shr{l}\t$dst",
164 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
165 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
166 "shr{q}\t$dst",
167 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
168 } // Constraints = "$src = $dst", SchedRW
173 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
174 "shr{b}\t{%cl, $dst|$dst, cl}",
175 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
176 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
177 "shr{w}\t{%cl, $dst|$dst, cl}",
178 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
180 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
181 "shr{l}\t{%cl, $dst|$dst, cl}",
182 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
184 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
185 "shr{q}\t{%cl, $dst|$dst, cl}",
186 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
188 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
189 "shr{b}\t{$src, $dst|$dst, $src}",
190 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
192 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
193 "shr{w}\t{$src, $dst|$dst, $src}",
194 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
196 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
197 "shr{l}\t{$src, $dst|$dst, $src}",
198 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
200 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
201 "shr{q}\t{$src, $dst|$dst, $src}",
202 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
206 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
207 "shr{b}\t$dst",
208 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
210 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
211 "shr{w}\t$dst",
212 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
214 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
215 "shr{l}\t$dst",
216 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
218 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
219 "shr{q}\t$dst",
220 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
226 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
227 "sar{b}\t{%cl, $dst|$dst, cl}",
228 [(set GR8:$dst, (sra GR8:$src1, CL))],
230 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
231 "sar{w}\t{%cl, $dst|$dst, cl}",
232 [(set GR16:$dst, (sra GR16:$src1, CL))],
234 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
235 "sar{l}\t{%cl, $dst|$dst, cl}",
236 [(set GR32:$dst, (sra GR32:$src1, CL))],
238 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
239 "sar{q}\t{%cl, $dst|$dst, cl}",
240 [(set GR64:$dst, (sra GR64:$src1, CL))],
244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
245 "sar{b}\t{$src2, $dst|$dst, $src2}",
246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
249 "sar{w}\t{$src2, $dst|$dst, $src2}",
250 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
252 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
253 "sar{l}\t{$src2, $dst|$dst, $src2}",
254 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
256 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
258 "sar{q}\t{$src2, $dst|$dst, $src2}",
259 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
263 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
264 "sar{b}\t$dst",
265 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
267 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
268 "sar{w}\t$dst",
269 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
271 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
272 "sar{l}\t$dst",
273 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
275 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
276 "sar{q}\t$dst",
277 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
279 } // Constraints = "$src = $dst", SchedRW
284 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
285 "sar{b}\t{%cl, $dst|$dst, cl}",
286 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
288 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
289 "sar{w}\t{%cl, $dst|$dst, cl}",
290 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
292 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
293 "sar{l}\t{%cl, $dst|$dst, cl}",
294 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
296 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
297 "sar{q}\t{%cl, $dst|$dst, cl}",
298 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
301 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
302 "sar{b}\t{$src, $dst|$dst, $src}",
303 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
305 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
306 "sar{w}\t{$src, $dst|$dst, $src}",
307 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
309 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
310 "sar{l}\t{$src, $dst|$dst, $src}",
311 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
313 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
314 "sar{q}\t{$src, $dst|$dst, $src}",
315 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
319 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
320 "sar{b}\t$dst",
321 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
323 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
324 "sar{w}\t$dst",
325 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
327 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
328 "sar{l}\t$dst",
329 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
331 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
332 "sar{q}\t$dst",
333 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
342 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
344 "rcl{b}\t$dst", [], IIC_SR>;
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
348 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
349 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
351 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
352 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
353 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
354 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
357 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
359 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
360 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
362 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
364 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
365 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
368 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
369 "rcl{q}\t$dst", [], IIC_SR>;
370 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
371 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
373 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
374 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
377 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
378 "rcr{b}\t$dst", [], IIC_SR>;
379 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
380 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
382 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
383 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
385 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
386 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
387 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
388 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
390 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
391 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
394 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
398 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
399 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
401 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
402 "rcr{q}\t$dst", [], IIC_SR>;
403 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
404 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
406 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
407 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
409 } // Constraints = "$src = $dst"
412 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
413 "rcl{b}\t$dst", [], IIC_SR>;
414 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt),
415 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
416 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
417 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
418 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt),
419 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
420 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
421 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
422 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt),
423 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
424 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
425 "rcl{q}\t$dst", [], IIC_SR>;
426 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt),
427 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
429 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
430 "rcr{b}\t$dst", [], IIC_SR>;
431 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt),
432 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
433 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
434 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
435 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt),
436 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
437 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
438 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
439 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt),
440 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
441 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
442 "rcr{q}\t$dst", [], IIC_SR>;
443 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt),
444 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
447 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
448 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
449 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
450 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
451 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
452 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
453 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
454 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
456 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
457 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
458 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
459 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
460 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
461 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
462 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
463 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
468 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
471 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
472 "rol{b}\t{%cl, $dst|$dst, cl}",
473 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
474 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
475 "rol{w}\t{%cl, $dst|$dst, cl}",
476 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
477 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
478 "rol{l}\t{%cl, $dst|$dst, cl}",
479 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
480 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
481 "rol{q}\t{%cl, $dst|$dst, cl}",
482 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
485 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
486 "rol{b}\t{$src2, $dst|$dst, $src2}",
487 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
489 "rol{w}\t{$src2, $dst|$dst, $src2}",
490 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
493 "rol{l}\t{$src2, $dst|$dst, $src2}",
494 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
496 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
498 "rol{q}\t{$src2, $dst|$dst, $src2}",
499 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
503 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
504 "rol{b}\t$dst",
505 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
507 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
508 "rol{w}\t$dst",
509 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
511 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
512 "rol{l}\t$dst",
513 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
515 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
516 "rol{q}\t$dst",
517 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
519 } // Constraints = "$src = $dst", SchedRW
523 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
524 "rol{b}\t{%cl, $dst|$dst, cl}",
525 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
527 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
528 "rol{w}\t{%cl, $dst|$dst, cl}",
529 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
531 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
532 "rol{l}\t{%cl, $dst|$dst, cl}",
533 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
535 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
536 "rol{q}\t{%cl, $dst|$dst, cl}",
537 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
540 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
541 "rol{b}\t{$src1, $dst|$dst, $src1}",
542 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
544 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1),
545 "rol{w}\t{$src1, $dst|$dst, $src1}",
546 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
548 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1),
549 "rol{l}\t{$src1, $dst|$dst, $src1}",
550 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
552 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
553 "rol{q}\t{$src1, $dst|$dst, $src1}",
554 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
558 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
559 "rol{b}\t$dst",
560 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
562 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
563 "rol{w}\t$dst",
564 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
566 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
567 "rol{l}\t$dst",
568 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
570 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
571 "rol{q}\t$dst",
572 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
576 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
578 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
579 "ror{b}\t{%cl, $dst|$dst, cl}",
580 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
581 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
582 "ror{w}\t{%cl, $dst|$dst, cl}",
583 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
584 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
585 "ror{l}\t{%cl, $dst|$dst, cl}",
586 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
587 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
588 "ror{q}\t{%cl, $dst|$dst, cl}",
589 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
592 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
593 "ror{b}\t{$src2, $dst|$dst, $src2}",
594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
596 "ror{w}\t{$src2, $dst|$dst, $src2}",
597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
600 "ror{l}\t{$src2, $dst|$dst, $src2}",
601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
603 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
605 "ror{q}\t{$src2, $dst|$dst, $src2}",
606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
610 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
611 "ror{b}\t$dst",
612 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
615 "ror{w}\t$dst",
616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
618 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
619 "ror{l}\t$dst",
620 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
622 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
623 "ror{q}\t$dst",
624 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
626 } // Constraints = "$src = $dst", SchedRW
630 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
631 "ror{b}\t{%cl, $dst|$dst, cl}",
632 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
634 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
635 "ror{w}\t{%cl, $dst|$dst, cl}",
636 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
638 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
639 "ror{l}\t{%cl, $dst|$dst, cl}",
640 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
642 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
643 "ror{q}\t{%cl, $dst|$dst, cl}",
644 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
647 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
648 "ror{b}\t{$src, $dst|$dst, $src}",
649 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
651 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src),
652 "ror{w}\t{$src, $dst|$dst, $src}",
653 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
655 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src),
656 "ror{l}\t{$src, $dst|$dst, $src}",
657 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
659 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
660 "ror{q}\t{$src, $dst|$dst, $src}",
661 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
665 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
666 "ror{b}\t$dst",
667 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
669 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
670 "ror{w}\t$dst",
671 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
673 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
674 "ror{l}\t$dst",
675 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
677 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
678 "ror{q}\t$dst",
679 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
688 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
691 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
694 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
697 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
699 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
700 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
703 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
706 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
708 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
710 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
711 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
713 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
716 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
719 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
721 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
722 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
729 (outs GR16:$dst),
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
736 (outs GR16:$dst),
738 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
739 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
743 (outs GR32:$dst),
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
746 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
750 (outs GR32:$dst),
752 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
753 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
757 (outs GR64:$dst),
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
760 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
764 (outs GR64:$dst),
766 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
767 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
771 } // Constraints = "$src = $dst", SchedRW
775 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
777 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
778 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
779 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
780 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
781 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
782 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
784 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
786 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
787 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
788 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
789 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
790 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
791 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
793 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
795 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
796 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
797 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
798 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
799 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
800 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
804 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
806 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
807 (i8 imm:$src3)), addr:$dst)],
811 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
812 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
813 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
814 (i8 imm:$src3)), addr:$dst)],
819 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
820 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
821 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
822 (i8 imm:$src3)), addr:$dst)],
826 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
827 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
828 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
829 (i8 imm:$src3)), addr:$dst)],
834 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
835 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
836 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
837 (i8 imm:$src3)), addr:$dst)],
841 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
842 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
843 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
844 (i8 imm:$src3)), addr:$dst)],
863 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
864 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
867 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
869 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
876 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
877 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
880 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
881 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,