Lines Matching full:x86
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
262 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
280 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
281 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
282 NewOpcode = X86::CBW; in SimplifyMOVSX()
284 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
285 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
286 NewOpcode = X86::CWDE; in SimplifyMOVSX()
288 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
289 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
290 NewOpcode = X86::CDQE; in SimplifyMOVSX()
313 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
314 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && in SimplifyShortMoveForm()
315 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
316 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && in SimplifyShortMoveForm()
323 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
338 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in SimplifyShortMoveForm()
339 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || in SimplifyShortMoveForm()
340 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
345 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); in SimplifyShortMoveForm()
353 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; in getRetOpcode()
399 case X86::LEA64_32r: in Lower()
400 case X86::LEA64r: in Lower()
401 case X86::LEA16r: in Lower()
402 case X86::LEA32r: in Lower()
404 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
406 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
412 case X86::VMOVZPQILo2PQIrr: in Lower()
413 case X86::VMOVAPDrr: in Lower()
414 case X86::VMOVAPDYrr: in Lower()
415 case X86::VMOVAPSrr: in Lower()
416 case X86::VMOVAPSYrr: in Lower()
417 case X86::VMOVDQArr: in Lower()
418 case X86::VMOVDQAYrr: in Lower()
419 case X86::VMOVDQUrr: in Lower()
420 case X86::VMOVDQUYrr: in Lower()
421 case X86::VMOVUPDrr: in Lower()
422 case X86::VMOVUPDYrr: in Lower()
423 case X86::VMOVUPSrr: in Lower()
424 case X86::VMOVUPSYrr: { in Lower()
430 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
431 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
432 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
433 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
434 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
435 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
436 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
437 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
438 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
439 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; in Lower()
440 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; in Lower()
441 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; in Lower()
442 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; in Lower()
448 case X86::VMOVSDrr: in Lower()
449 case X86::VMOVSSrr: { in Lower()
455 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; in Lower()
456 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; in Lower()
466 case X86::TAILJMPr64: in Lower()
467 case X86::TAILJMPr64_REX: in Lower()
468 case X86::CALL64r: in Lower()
469 case X86::CALL64pcrel32: { in Lower()
478 case X86::EH_RETURN: in Lower()
479 case X86::EH_RETURN64: { in Lower()
485 case X86::CLEANUPRET: { in Lower()
492 case X86::CATCHRET: { in Lower()
495 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; in Lower()
503 case X86::TAILJMPr: in Lower()
504 case X86::TAILJMPd: in Lower()
505 case X86::TAILJMPd64: { in Lower()
509 case X86::TAILJMPr: Opcode = X86::JMP32r; break; in Lower()
510 case X86::TAILJMPd: in Lower()
511 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; in Lower()
521 case X86::DEC16r: in Lower()
522 case X86::DEC32r: in Lower()
523 case X86::INC16r: in Lower()
524 case X86::INC32r: in Lower()
530 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; in Lower()
531 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; in Lower()
532 case X86::INC16r: Opcode = X86::INC16r_alt; break; in Lower()
533 case X86::INC32r: Opcode = X86::INC32r_alt; break; in Lower()
542 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; in Lower()
543 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; in Lower()
544 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; in Lower()
545 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; in Lower()
546 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; in Lower()
547 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; in Lower()
548 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; in Lower()
549 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; in Lower()
550 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; in Lower()
555 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; in Lower()
556 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; in Lower()
557 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; in Lower()
558 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; in Lower()
559 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; in Lower()
560 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; in Lower()
561 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; in Lower()
562 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; in Lower()
563 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify; in Lower()
564 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify; in Lower()
565 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify; in Lower()
566 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify; in Lower()
567 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify; in Lower()
568 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify; in Lower()
569 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify; in Lower()
570 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify; in Lower()
571 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify; in Lower()
572 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify; in Lower()
573 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify; in Lower()
574 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify; in Lower()
575 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify; in Lower()
576 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify; in Lower()
577 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify; in Lower()
578 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify; in Lower()
579 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify; in Lower()
580 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify; in Lower()
581 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify; in Lower()
582 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify; in Lower()
583 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify; in Lower()
584 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify; in Lower()
585 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify; in Lower()
586 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify; in Lower()
587 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify; in Lower()
588 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify; in Lower()
589 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify; in Lower()
590 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify; in Lower()
591 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify; in Lower()
592 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify; in Lower()
593 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify; in Lower()
594 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify; in Lower()
595 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify; in Lower()
596 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify; in Lower()
597 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify; in Lower()
598 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify; in Lower()
607 case X86::MOV8mr_NOREX: in Lower()
608 case X86::MOV8mr: in Lower()
609 case X86::MOV8rm_NOREX: in Lower()
610 case X86::MOV8rm: in Lower()
611 case X86::MOV16mr: in Lower()
612 case X86::MOV16rm: in Lower()
613 case X86::MOV32mr: in Lower()
614 case X86::MOV32rm: { in Lower()
618 case X86::MOV8mr_NOREX: in Lower()
619 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; in Lower()
620 case X86::MOV8rm_NOREX: in Lower()
621 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; in Lower()
622 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; in Lower()
623 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; in Lower()
624 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; in Lower()
625 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; in Lower()
631 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: in Lower()
632 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: in Lower()
633 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: in Lower()
634 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: in Lower()
635 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: in Lower()
636 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: in Lower()
637 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: in Lower()
638 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: in Lower()
639 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { in Lower()
643 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; in Lower()
644 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; in Lower()
645 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; in Lower()
646 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; in Lower()
647 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; in Lower()
648 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; in Lower()
649 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; in Lower()
650 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; in Lower()
651 case X86::AND8ri: NewOpc = X86::AND8i8; break; in Lower()
652 case X86::AND16ri: NewOpc = X86::AND16i16; break; in Lower()
653 case X86::AND32ri: NewOpc = X86::AND32i32; break; in Lower()
654 case X86::AND64ri32: NewOpc = X86::AND64i32; break; in Lower()
655 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; in Lower()
656 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; in Lower()
657 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; in Lower()
658 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; in Lower()
659 case X86::OR8ri: NewOpc = X86::OR8i8; break; in Lower()
660 case X86::OR16ri: NewOpc = X86::OR16i16; break; in Lower()
661 case X86::OR32ri: NewOpc = X86::OR32i32; break; in Lower()
662 case X86::OR64ri32: NewOpc = X86::OR64i32; break; in Lower()
663 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; in Lower()
664 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; in Lower()
665 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; in Lower()
666 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; in Lower()
667 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; in Lower()
668 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; in Lower()
669 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; in Lower()
670 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; in Lower()
671 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; in Lower()
672 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; in Lower()
673 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; in Lower()
674 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; in Lower()
675 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; in Lower()
676 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; in Lower()
677 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; in Lower()
678 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; in Lower()
685 case X86::MOVSX16rr8: in Lower()
686 case X86::MOVSX32rr16: in Lower()
687 case X86::MOVSX64rr32: in Lower()
696 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || in LowerTlsAddr()
697 MI.getOpcode() == X86::TLS_base_addr64; in LowerTlsAddr()
699 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; in LowerTlsAddr()
704 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
708 case X86::TLS_addr32: in LowerTlsAddr()
709 case X86::TLS_addr64: in LowerTlsAddr()
712 case X86::TLS_base_addr32: in LowerTlsAddr()
715 case X86::TLS_base_addr64: in LowerTlsAddr()
727 LEA.setOpcode(X86::LEA64r); in LowerTlsAddr()
728 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest in LowerTlsAddr()
729 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base in LowerTlsAddr()
735 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
736 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest in LowerTlsAddr()
737 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base in LowerTlsAddr()
743 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
744 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest in LowerTlsAddr()
747 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index in LowerTlsAddr()
754 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
755 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
756 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); in LowerTlsAddr()
766 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 in LowerTlsAddr()
767 : X86::CALLpcrel32) in LowerTlsAddr()
777 assert(Is64Bit && "EmitNops only supports X86-64"); in EmitNop()
782 BaseReg = X86::RAX; in EmitNop()
786 case 1: NopSize = 1; Opc = X86::NOOP; break; in EmitNop()
787 case 2: NopSize = 2; Opc = X86::XCHG16ar; break; in EmitNop()
788 case 3: NopSize = 3; Opc = X86::NOOPL; break; in EmitNop()
789 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break; in EmitNop()
790 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8; in EmitNop()
791 IndexReg = X86::RAX; break; in EmitNop()
792 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8; in EmitNop()
793 IndexReg = X86::RAX; break; in EmitNop()
794 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break; in EmitNop()
795 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512; in EmitNop()
796 IndexReg = X86::RAX; break; in EmitNop()
797 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512; in EmitNop()
798 IndexReg = X86::RAX; break; in EmitNop()
799 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512; in EmitNop()
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNop()
812 case X86::NOOP: in EmitNop()
815 case X86::XCHG16ar: in EmitNop()
816 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); in EmitNop()
818 case X86::NOOPL: in EmitNop()
819 case X86::NOOPW: in EmitNop()
833 /// \brief Emit the optimal amount of multi-byte nops on X86.
846 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); in LowerSTATEPOINT()
862 CallOpcode = X86::CALL64pcrel32; in LowerSTATEPOINT()
870 CallOpcode = X86::CALL64pcrel32; in LowerSTATEPOINT()
878 CallOpcode = X86::CALL64r; in LowerSTATEPOINT()
911 if (LoadDefRegister != X86::NoRegister) in LowerFAULTING_LOAD_OP()
942 if (MinSize == 2 && Opcode == X86::PUSH64r) { in LowerPATCHABLE_OP()
948 MCI.setOpcode(X86::PUSH64rmr); in LowerPATCHABLE_OP()
973 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); in LowerPATCHPOINT()
1014 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); in LowerPATCHPOINT()
1015 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); in LowerPATCHPOINT()
1073 // PATCHABLE_RET X86::RET ... in LowerPATCHABLE_RET()
1229 case X86::Int_MemBarrier: in EmitInstruction()
1234 case X86::EH_RETURN: in EmitInstruction()
1235 case X86::EH_RETURN64: { in EmitInstruction()
1242 case X86::CLEANUPRET: { in EmitInstruction()
1248 case X86::CATCHRET: { in EmitInstruction()
1254 case X86::TAILJMPr: in EmitInstruction()
1255 case X86::TAILJMPm: in EmitInstruction()
1256 case X86::TAILJMPd: in EmitInstruction()
1257 case X86::TAILJMPr64: in EmitInstruction()
1258 case X86::TAILJMPm64: in EmitInstruction()
1259 case X86::TAILJMPd64: in EmitInstruction()
1260 case X86::TAILJMPr64_REX: in EmitInstruction()
1261 case X86::TAILJMPm64_REX: in EmitInstruction()
1262 case X86::TAILJMPd64_REX: in EmitInstruction()
1267 case X86::TLS_addr32: in EmitInstruction()
1268 case X86::TLS_addr64: in EmitInstruction()
1269 case X86::TLS_base_addr32: in EmitInstruction()
1270 case X86::TLS_base_addr64: in EmitInstruction()
1273 case X86::MOVPC32r: { in EmitInstruction()
1284 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32) in EmitInstruction()
1305 EmitAndCountInstruction(MCInstBuilder(X86::POP32r) in EmitInstruction()
1314 case X86::ADD32ri: { in EmitInstruction()
1340 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) in EmitInstruction()
1367 case X86::MORESTACK_RET: in EmitInstruction()
1371 case X86::MORESTACK_RET_RESTORE_R10: in EmitInstruction()
1374 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr) in EmitInstruction()
1375 .addReg(X86::R10) in EmitInstruction()
1376 .addReg(X86::RAX)); in EmitInstruction()
1379 case X86::SEH_PushReg: in EmitInstruction()
1383 case X86::SEH_SaveReg: in EmitInstruction()
1388 case X86::SEH_SaveXMM: in EmitInstruction()
1393 case X86::SEH_StackAlloc: in EmitInstruction()
1397 case X86::SEH_SetFrame: in EmitInstruction()
1402 case X86::SEH_PushFrame: in EmitInstruction()
1406 case X86::SEH_EndPrologue: in EmitInstruction()
1410 case X86::SEH_Epilogue: { in EmitInstruction()
1420 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); in EmitInstruction()
1430 case X86::PSHUFBrm: in EmitInstruction()
1431 case X86::VPSHUFBrm: in EmitInstruction()
1432 case X86::VPSHUFBYrm: in EmitInstruction()
1433 case X86::VPSHUFBZ128rm: in EmitInstruction()
1434 case X86::VPSHUFBZ128rmk: in EmitInstruction()
1435 case X86::VPSHUFBZ128rmkz: in EmitInstruction()
1436 case X86::VPSHUFBZ256rm: in EmitInstruction()
1437 case X86::VPSHUFBZ256rmk: in EmitInstruction()
1438 case X86::VPSHUFBZ256rmkz: in EmitInstruction()
1439 case X86::VPSHUFBZrm: in EmitInstruction()
1440 case X86::VPSHUFBZrmk: in EmitInstruction()
1441 case X86::VPSHUFBZrmkz: { in EmitInstruction()
1447 case X86::PSHUFBrm: in EmitInstruction()
1448 case X86::VPSHUFBrm: in EmitInstruction()
1449 case X86::VPSHUFBYrm: in EmitInstruction()
1450 case X86::VPSHUFBZ128rm: in EmitInstruction()
1451 case X86::VPSHUFBZ256rm: in EmitInstruction()
1452 case X86::VPSHUFBZrm: in EmitInstruction()
1454 case X86::VPSHUFBZ128rmkz: in EmitInstruction()
1455 case X86::VPSHUFBZ256rmkz: in EmitInstruction()
1456 case X86::VPSHUFBZrmkz: in EmitInstruction()
1458 case X86::VPSHUFBZ128rmk: in EmitInstruction()
1459 case X86::VPSHUFBZ256rmk: in EmitInstruction()
1460 case X86::VPSHUFBZrmk: in EmitInstruction()
1479 case X86::VPERMILPDrm: in EmitInstruction()
1480 case X86::VPERMILPDYrm: in EmitInstruction()
1481 case X86::VPERMILPDZ128rm: in EmitInstruction()
1482 case X86::VPERMILPDZ256rm: in EmitInstruction()
1483 case X86::VPERMILPDZrm: { in EmitInstruction()
1501 case X86::VPERMILPSrm: in EmitInstruction()
1502 case X86::VPERMILPSYrm: in EmitInstruction()
1503 case X86::VPERMILPSZ128rm: in EmitInstruction()
1504 case X86::VPERMILPSZ256rm: in EmitInstruction()
1505 case X86::VPERMILPSZrm: { in EmitInstruction()
1523 case X86::VPERMIL2PDrm: in EmitInstruction()
1524 case X86::VPERMIL2PSrm: in EmitInstruction()
1525 case X86::VPERMIL2PDrmY: in EmitInstruction()
1526 case X86::VPERMIL2PSrmY: { in EmitInstruction()
1543 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break; in EmitInstruction()
1544 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break; in EmitInstruction()
1556 case X86::VPPERMrrm: { in EmitInstruction()
1576 case X86::Prefix##MOVAPD##Suffix##rm: \ in EmitInstruction()
1577 case X86::Prefix##MOVAPS##Suffix##rm: \ in EmitInstruction()
1578 case X86::Prefix##MOVUPD##Suffix##rm: \ in EmitInstruction()
1579 case X86::Prefix##MOVUPS##Suffix##rm: \ in EmitInstruction()
1580 case X86::Prefix##MOVDQA##Suffix##rm: \ in EmitInstruction()
1581 case X86::Prefix##MOVDQU##Suffix##rm: in EmitInstruction()
1584 case X86::VMOVDQA64##Suffix##rm: \ in EmitInstruction()
1585 case X86::VMOVDQA32##Suffix##rm: \ in EmitInstruction()
1586 case X86::VMOVDQU64##Suffix##rm: \ in EmitInstruction()
1587 case X86::VMOVDQU32##Suffix##rm: \ in EmitInstruction()
1588 case X86::VMOVDQU16##Suffix##rm: \ in EmitInstruction()
1589 case X86::VMOVDQU8##Suffix##rm: \ in EmitInstruction()
1590 case X86::VMOVAPS##Suffix##rm: \ in EmitInstruction()
1591 case X86::VMOVAPD##Suffix##rm: \ in EmitInstruction()
1592 case X86::VMOVUPS##Suffix##rm: \ in EmitInstruction()
1593 case X86::VMOVUPD##Suffix##rm: in EmitInstruction()